3D Integrated Circuits

By:

Pravesh Prabhu Chirag S P 3rd Year E&C

ABSTRACT: 3D IC extends interconnect technology across multiple chips, multiple domains (digital, custom/RF, memory) and multiple technology nodes. In addition to the heterogeneous system integration, 3D IC offers multiple types of configuration such as 3D IC vertical stack, and silicon interposer. Another dimension of 3D IC is the integration with package, that adds a large number of configuration. All these types of 3D IC integration bring together multiple design system (digital design, custom/analog design, and package design). As such it will require a team of designers with different expertise to implement an integrated system of 3D IC. The focus of this invited talk is to explore 3D IC physical modeling, physical design methodology and physical design tools. We have added infrastructure in the database, library interfaces and tools to allow the specification of 3D IC configuration and interconnect components. Both physical design tools and analysis tools have been enabled to support 3D IC design and analysis using the same modeling and infrastructure. We have developed design methodology with early 3D IC designers that allowed focusing on design flow that is optimized for popular stacking styles. 3D IC adds new physical components, which must be modeled and supported by physical design tools. TSV with backside metal layers and micro-bump (cupper pillars) are examples of these components. The new components have design rules associated with them as well as design constraints. The design constraints are added to avoid mechanical stress associated with TSV and substrate thinning. Physical design tools such as placement and routing have been enabled to allow the user to apply these components during the different stages of the physical design flow. These enhancements allow the designer to maintain the investment in IC

Formal specification is developed to allow the description of 3D IC stack configuration and also to describe the types of signals/power that go through the stack. Both the vertical 3D IC stacks and silicon interposer are well supported. In addition to managing the stack, the designer has also the capability to do early planning for special signals and power that should traverse the stack in a shortest distance. High speed signals are examples of those special signals. Early floor planning is one of the strength of EDI system that allows the designer/design team to plan and implement any 3D IC connectivity with new patterns and/or pre-defined patterns (TSV and micro-bumps). We have developed several design methodologies to guide the designer during the planning, placement and routing stages. In every design tape-out we have done so far, there are usually several signals and power that must be pre-defined and put in special location on each chip. We have developed automated features allow the placement and routing of TSV and micro-bump in any user defined pattern. In many cases, the assignment of signals is usually dictated by package/board design and provides assignment constraints that must be propagated through the entire stack.

tools that are being used and apply 3D IC features and design flow in an efficient manner.

WHY 3D IC?
As current scaling trends require enormous investments only affordable to a select few, Moores Law reaches its limit and 3D IC technology becomes inevitable. 3D IC is the natural evolution of our industry; it is the convergence of performance, power and portability. The economic and technical improvements in performance, power, form factor, time-to-market and cost will drive the use of 3D system ICs.

to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.

MANUFACTURING TECHNOLOGIES As of 2008 there are four ways to build a 3D IC: Monolithic: Electronic components and their connections are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or throughsilicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring. This monolithic 3D-IC technology has been researched at Stanford University under a DARPA sponsored grant. Wafer-on-Wafer: Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These through-silicon vias (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300mm), complicating heterogeneous integration. Die-on-Wafer: Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dice may be added to the stacks before dicing.

EVOLUTION OF 3D IC In 2004, Intel presented a 3D version of the Pentium 4 CPU. The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for IO and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4 The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional IO approach would consume 10 to 25W.To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2W. An academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach. One challenge in manufacturing of the three-dimensional chip was

Die-on-Die : Electronic components are built on multiple dice, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack. Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).

routing methods break down the integer program into pieces small enough to be solved exactly Extending to 3D: It consists of routing a set of aligned congruent routing regions on adjacent wafers. Wires can enter from any of the sides of the routing region in addition to its top and bottom 3D router must consider routing on each of the layers in addition to the placement of the inter-waver vias Basis idea is: You connect a inter-waver via to the port you are trying to connect to, and route the wire to that via on the 2D plane. All we need now is enough area in the 2D routing space to route to the appropriate via 3D Routing Results: Percentage Of 2D Total wire Length Minimizing for Wire Length: 2 Layers ~ 28% 5 Layers ~ 51 % Minimizing for via count: 2 Layers ~ 7% 5 Layers ~ 17% 3D-MAGIC:It is an open source layout editor developed at UC Berkeley 3D-MAGIC is an extension to MAGIC by providing support for Multi-layer IC design Whats different New Command :bond Bonds existing 2D ICs and places inter-layer Vias in the design file Once Two layers are bonded they are treated as one entity

3D STANDARD CELL TOOL DESIGN 3D Standard Cell Placement:To think of a 3D integrated circuit as being partitioned into device layers or planes Min cut part-itioning along the 3rd dimension is same as minimizing vias Total wire length vs. Vias: It Can trade off increased total wire length for fewer inter-plane vias by varying the point at which the design is partitioned into planes Plane assignment performed prior to detailed placement Yields smaller number of vias, but greater overall wire length Total wire length vs. Vias (Cont): Plane assignment not made until detailed placement stage Yields smaller total wire length but greater number of vias Intro to Global Routing: It involves generating a loose route for each net. Assigns a list of routing regions to a net without actually specifying the geometrical layout of the wires. Followed by detailed routing Finds the actual geometrical shape of the net within the assigned routing regions. Usually either sequential or hierarchical algorithms Hierarchical Global Routing : This uses a hierarchical global routing algorithm Based on Integer programming and Steiner trees Integer programming approach still too slow for size of problem and complexity (NP-hard) Hierarchical

CONCERNS IN 3D CIRCUIT Thermal Issues in 3D Circuits : Thermal Effects dramatically impact interconnect and device reliability in 2D circuits Due to reduction in chip size of a 3D implementation, 3D circuits exhibit a sharp increase in power density Analysis of Thermal problems in 3D is necessary to evaluate thermal robustness of different 3D technology and design options. Heat Flow in 2D: It arises due to switching In 2D circuits we have only one layer of Si to consider. Heat Flow in 3D: With multi-layer circuits, the upper layers will also generate a significant fraction of the heat. Heat increases linearly with level increase

Heat Dissipation: All active layers will be insulated from each other by layers of dielectrics with much lower thermal conductivity than Si Therefore heat dissipation in 3D circuits can accelerate many failure mechanisms. EMI in 3D ICs: Interconnect Coupling Capacitance and cross talk Coupling between the top layer metal of the first active layer and the device on the second active layer devices is expected EMI :Interconnect Inductance Effects Shorter wire lengths help reduce the inductance Presence of second substrate close to global wires might help lower inductance by providing shorter return paths Reliability Issues: Electro thermal and Thermomechanical effects between various active layers can influence electro-migration and chip performance Die yield issues may arise due to mismatches between die yields of different layers, which affect net yield of 3D chips.

researchers are on the order of 10-15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.

Power Keeping a signal on-chip can reduce its power consumption by 10-100 times. Shorter wires also reduce power consumption by producing less parasitic capacitance. Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation. Design The vertical dimension adds a higher order of connectivity and offers new design possibilities. Circuit security The stacked structure complicates attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.

ADVANTAGES Footprint More functionality fits into a small space. This extends Moores Law and enables a new generation of tiny but powerful devices. Cost Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately. Heterogeneous integration Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC. Shorter interconnect The average wire length is reduced. Common figures reported by PRESENT SCENARIO OF THE 3-D IC INDUSTRY Many companies are working on the 3-D chips, including groups at Massachusetts institute of technology (MI T), international business machines (IBM).First products will be memory chips called 3-Dmemory, for consumer electronics like digital cameras and audio players. current flash memory cards for such devices are rewritable but expensive .The cost is so largely because the stacked chips contain the same amount of circuitry as flash cards but use a much smaller area of the extremely expensive silicon wafers that form the basis for all silicon chips.

APPLICATIONS Portable electronic digital cameras, digital audio players, PDAs, smart cellular phones, and handheld gaming devices are among the fastest growing technology market for both business and consumers. Manufacturers of memory driven devices can now reach price points previously inaccessible and develop richer, easier to use products. Existing mask ROM and NAND flash non volatile technology force designers and product planners to make the difficult choice between low cost or field programmability and Flexibility.

both cheap and convenient enough to replace the photographic film and audio tape. The multilayer chip building technology opens up a whole new world of design like a city skyline transformed by skyscrapers, the world of chips may never look at the same again.

REFERENCES S. Borkar, 3D integration for energy efficient system design, Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs" Real World Technologies. "3D Integration: A Revolution in Design" J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2D Blocks into 3D Chips,"

FUTURE OF THE 3-D IC INDUSTRY Thomson electronics, the European electronic giant, will begin to incorporate 3-Dmemory chips from matrix semiconductor in portable storage cards, a strong endorsement for the chip start up. Matrix is working with partners including Microsoft Corp, Thomas Multimedia, Eastman Kodak and Sony Corp. three product categories are planned: bland memory cards: cards sold preloaded with content, such as software or music ; and standard memory packages, for using embedded applications such as PDAs and set-top boxes . T he first Technicolor cards will offer 64 MB of memory; version with 128 MB and 192 MB will appear later. T he first 3-D chips will contain 64 MB.Taiwan Semiconductor Manufacturing Co. is producing the chips on behalf of matrix . CONCLUSION The 3 D memory will just be the first of a new generation of dense, inexpensive chips that promise to make digital recording media