!

NANOSCIENCE & NANOTECHNOLOGY 1 OALISCO B)

15:20 [NSN-52] Wave propagation in periodic ~odic structures. Jose Luis Arag6n [ D] [NSN-39]SPI.oNs the future for cancer nanotherapy. Jaime Santoyo Salazar 15:40

MICROElECTRONICS &MEMS (JAUSCOO

[MEM-14] Characterization differential variable capacitor P.oLYMUMPS process. Ivan Cano, Juan Luis Ibarra, Jose of a build on Javier Munoz Mireles Jr.

COURSE 7 (JALISCO

- A)

[MEM-06] A data ac'}.uisition system for integrated biosensor m 0.5 um CM.oS techDolojP'. Juan Manuel G6mez Cruz, Zaid MOiSes Morales Martinez, Annel Krisali Hurtado .orozco, Esteban Martinez Guerrero [MEM-12] Simulation and characterization of a parallel t/ate variable capacitor fabricated with SU MiTV ftocess. Juan Luis Ibarra D., Ivan Munoz, ustavo Lara, Jose Mireles Jr. [MEM-07] Modeling and simulation of microluids in microchannels for ctlications in micro fuel cells. Casimiro omez Gonzalez, Sonia Lizeth Ramos Pedr6n

Ellipsometry Juan Antonio Zapien

16:00 [NSN-44] Effect of m~etite and maghernite nanopartic es on radish Kirmination. Nicolaza Pariona, Arturo I. artinez, Roman Castro- Rodriguez 16:20

16:40 [NSN-27] Effect of e1ectror,innin vol~ on the formation 0 micro bers ofPo:fo:inJt.l{'yrrolidone. Jose Alfredo Pesca or 0jas, Jose Francisco Sanchez Ramirez, Alejandro Bautista Hernandez, Emesto Chigo Anota, JesUs Antonio Fuentes Garda

COFFEE

COFFEE

17:00

[MEM-03] Study of 45 nmPD SOl M.oSFET under forward bias using 2D simulation. Abimael Jimenez P., Roberto c. Ambrosio L., Jose Mireles G., Karim Monfil L., Zurika Blanco

17:20

[NSN-17] Reinforcement with nanopartides of a liquid aluminum based alloy. Salom6n Rojas Trevino, Ana Maria Arizmendi Mor,;echo, Roberto Martinez Sanchez, Ser~io arda Villarreal, A1ejandra C avez Valdez [NSN-07] Modification of Multi- Walled Carbon Nanotubes Usin~ Acetic Acid and Aniline by U1trasomc Radiation. Christian Javier Cabello Alvarado, Aide Saenz Galindo, Catalina Perez Berumen, L1uvia L6pez L6p~ Leticia Barajas Bermudez, Carlos Avila .orta, Janett Valdez Garza [NSN-05] H2 ads0d:tion and storage inside and outside e C120 nanotorus effect of Be, Sc and Ca, atoms on the molecular hydrogen adsortion. Juan Salvador Arellano, Arman 0 Cruz- Torres, Jaime .ortiz- L6ez, Fray de Landa Castillo- A1vara 0

[MEM-17] Pressure microsensor on integrated optics. Marco Antonio Ramirez Barrientos, Aurelio Horacio Heredia Jimenez, Laura Josefina Castro Y Fernandez del Campo [MEM-IO] .ostimization and exr,eriment rocedure of eep dry etchin~ 0 silicon or MEMS development in exico. Jose Mireles Jr., HoraclO Estrada, Roberto Carlos Ambrosio, Abimael Juimenez, Juan Luis Ibarra, Ivan Javier Munoz

Ellipsometry Juan Antonio Zapien

17:40

18:00

[MEM-08] The electrical thermal and mechanical response of a:CH film t,ezoresistor for tensile stress. Luiz tonio Rasia

18:20

PLENARY 9 (JALISCO A) Innovative Design Concepts in Nanocomposite

Coatings for Ali Erdemir

Extreme Tribological Applications

19:00

BANQUET

Study of 45nm PD-SOI MOSFETs under Forward Bias Using 2D Simulation

R.

Ambrosioa ,

A. Jimneza e K. C. Martineza , J. Muozb , Z. Blanco. n a Universidad Autnoma de Ciudad Jurez. o a b Universidad de Guadalajara. Monla ,

September, 2011

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

Overview

Motivation and Background Objectives Simulation Details Results Conclusions

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

Moores Law

Figure: 90nm, 65nm, 45nm, 32nm technology nodes

Revolutionary technologies on a chip Strained silicon and hafnium-based gate-last high-k metal gate, introduced in the 45nm process.
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Moores Law

Figure: Structure and technology innovation for MOSFETs

CMOS technology The limit for SIO2 1 nm Dielectrics with high k = HfO2 , ZrO2 Polysilicon metal
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Partially Depleted - Silicon On Insulator

SOI transistor is known as a substitute for conventional silicon technology. Disadvantage instability, such as hysteresis and self-heating eect. Several techniques for body-contact have been developed. PD-SOI Dynamic Threshold MOSFET (DTMOS) results in a higher current drive than that of bulk CMOS. PD-SOI DTMOS is made by connecting the MOSFET gate to its oating body.

Figure: PD-SOI DTMOS Structure

Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Applications

?
Figure:
DTMOS Based Low Power High Speed Interconnects for FPGA. Kureshi A. K. and Mohd H., Journal of Computers, Vol 4, No 10 (2009), 921-926.

Figure:

The proposed diodes use DTMOS transistors. The idea of their operation is based on the connection of the gate, the drain and the bulk of the transistor together in order to obtain diodes with low-threshold voltage. Integrated power harvesting system including a MEMS generator and a power management circuit, Marzencki, M., et. al., International Solid-State Sensors, Actuators and Microsystems Conference, pp. 887-890, 2007.

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

Objective

General objective Analysis and simulation of PD-SOI MOSFETs under forward bias, incorporating HfO2 dielectrics and metal gates. The analysis is based on a physical study and 2D simulation, paying special attention to the correct modeling of the principal parameters of MOSFET.

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

Simulation Details

Synopsys TCAD simulation NA = 1.6x1018 cm3 , Tbox = 400nm and Tox = 15nm. The structure shows a body contact used for forward biasing the body.
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Results

40
Lg=45nm

For VBS = 0.8V the Source SBJ turns on and a large quantity of mobile charge is injected to the depletion region.

Drain Current,

VBS was swept from 0 to 0.8 V.

A
30

V BS

20
0.8 0

10

0 0.0 0.2 0.4 0.6 0.8 1.0

GS

DTMOS operation DTMOS normally requires gate to body voltages below 0.7 V. The injection of mobile carriers should be considered.

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

Results

0.40

Linear Extrapolation Method Drain Current Method

0.35

0.30

The drain current method predicts the lowest VTH. However both methods present the square root behavior and short channel eects reduction as forward bias is increased.

V TH,

0.25

0.20

V
0.15 0.10

0.05

Lg = 45nm Lg = 0.5 m

0.00 0.0 0.2 0.4 0.6 0.8

V , BS

Threshold Voltage One of the key design parameters in CMOS technology is the threshold voltage (VTH).
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Results
gm =
10
-4

IDS VGS

Lg = 45 nm W = 0.5
-5

90
V 0 V
BS

80
0.8 V

10

70 60

10

),

0 V

50 40

DS

Log(I

10

-7

BS

A/V

-6

As expected, curve families shift to the left as VBS increases in the forward direction. For an increasing forward substrate bias we observe a lower threshold voltage as well as the improvement of the transistor gain.

10

-8

20
0.8 V

10 0

10

-9

0.0

0.2

0.4

0.6

0.8

1.0

VGS,

Transconductance The perpendicular electric eld and the mobility degradation are reduced as forward body bias is increased as a result of this, the behavior of gm and fT are improved.
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

gm,

30

Results
As the channel length shortens and the VDS increases, the barrier lowering between the source and smin (y0 ) increases, thus the DIBL eect is increased. Nevertheless, under forward bias DIBL eect is reduced compared with a MOSFET. Potential The DIBL eect is present in short channel devices when VDS aects the channel potential prole, lowering the barrier at the Source-Body junction.
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Results

n+ poly-Si

p substrate

n+ poly-Si e-

p substrate

e-

eqVGB e- h+ h+ h+

-qVGB

(a) Inversion

(b) Accumulation

IG The higher gate current not only increases the standby power consumption of a highly integrated CMOS circuit, but also can adversely aect MOSFET performance.
Abimael Jimnez Prez e e IV International Conference on Surfaces, Materials and Vacuum

Conclusions
Conclusions We have investigated the performance of short PD-SOI MOSFETs with Poly/SiO2 and Ti/HfO2 gate stacks. The forward biasing voltage can be kept to values below 0.6 V since the SBJ turns on for higher values; nevertheless, a higher VBS may be desirable in order to further improve the transistor gain, then setting a trade-o between these parameters. As the actual dielectric thickness is decreased, the direct gate tunneling current increases. The current circuital models must be improved by considering the eects of the actual surface potential and the mobile charge density.

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

References

1 M. Maymandi-Nejad and M. Sachdev, DTMOS Technique for Low- Voltage Analog Circuits, IEEE Transactions on Very Large Scale Inte- gration (VLSI) Systems, vol. 14, no. 10, pp.1151-1156, 2006. 2 S. L. Jang and Ch. F. Lee, A Low Voltage and Power LC VCO Imple- mented With Dynamic Threshold Voltage MOSFETS, IEEE Microwave and Wireless Components Letters, vol. 17, no. 5, pp.376-378, 2007. 3 H. Singh, R. Rao, K. Agarwal, D. Sylvester and R. Brown, Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 1, pp. 166 - 170, 2010. 4 F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, Ping K. Ko, and Ch. Hu, A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low- Voltage Operation, IEEE Electron Device Lett., vol. 15, no.12, pp. 510- 512, 1994. 5 D. Kumar, P. Kumar and M. Pattanaik, Performance Analysis of Dynamic Threshold MOS (DTMOS) Based 4-Input Multiplexer Switch for Low Power and High Speed FPGA Design, Proceedings of the 23rd Symposium on Integrated Circuits and System Design, NY, USA, 2010. 6 W. C. H. Lin and J. B. Kuo, Low-Voltage SOI CMOS DT- MOS/MTCMOS Circuit Technique for Design Optimization of Low- Power SOC Applications, Proceedings of 2010 IEEE International Sym- posium on Circuits and Systems (ISCAS), pp. 3833 - 3836, Paris, 2010. 7 V. Niranjan and M. Gupta, An Analytical Model of the Bulk-DTMOS Transistor, Journal of Electron Devices, vol. 8, pp. 329-338, 2010.

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum

Questions?

Abimael Jimnez Prez e e

IV International Conference on Surfaces, Materials and Vacuum