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A Low-Cost VLSI Architecture for Robust Distributed Estimation in Wireless Sensor Networks
Li-Yuan Chang, Pei-Yin Chen, Member, IEEE, Tsang-Yi Wang, Member, IEEE, and Ching-Sung Chen
AbstractA robust distributed estimation scheme for fusion center in the presence of sensor faults via collaborative sensor fault detection (CSFD) was proposed in our previous research. The scheme can identify the faulty nodes efciently and improve the accuracy of the estimates signicantly. It achieves very good performance at the expense of such extensive computations as logarithm and division in the detecting process. In many real-time WSN applications, the fusion center might be implemented with the ASIC and included in a standalone device. Therefore, a simple and efcient distributed estimation scheme requiring lower hardware cost and power consumption is extremely desired for fusion center. In this paper, we propose the efcient collaborative sensor fault detection (ECSFD) scheme and its VLSI architecture. Given the low circuit complexity, it is suitable for hardware implementation. The circuit of ECSFD contains 22589 gates and requires a core size of 571 559 m by using TSMC 0.18 m cell library. Simulation results indicate the accuracy of the estimates obtained from the ECSFD is better than that obtained from a conventional approach. Index TermsDistributed estimation, fusion, sensor fault detection, VLSI architecture, wireless sensor networks.

I. INTRODUCTION S WIRELESS communications technology and microelectromechanical systems (MEMS) techniques have matured in recent years, wireless sensor networks (WSN) have emerged as a promising solution for a variety of remote sensing applications, including battleeld surveillance, environmental monitoring, intruder detection systems, weather forecasting, health care, agricultural technology, and so on. Irrespective of their purpose, all WSN are characterized by the requirement for energy efciency, scalability, and fault tolerance [1]. These requirements are particularly crucial in sensor networks designed to perform an estimation function. The fusion center makes the distributed estimation based upon the information received from the local nodes. In such networks, the estimation performance is critically dependent upon the availability and reliability of the local information, and substantial errors are
Manuscript received August 17, 2010; revised October 29, 2010; accepted November 07, 2010. Date of publication January 06, 2011; date of current version May 27, 2011. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 99-2220-E-006-026 and Grant NSC 99-2220-E-006-024, and in part by the Applied Information Services Development & Integration Project, Phase II, Institute for Information Industry, subsidized by the Ministry of Economy Affairs of the Republic of China. This paper was recommended by Associate Editor V. Gaudet. L.-Y Chang, P.-Y. Chen, and C.-S Chen are with the Digital IC Design Laboratory, Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 701, Taiwan (e-mail: lance@csie.ncku.edu.tw; pychen@csie.ncku.edu.tw; claude.chen@sunplus.com). T.-Y. Wang is with the Institute of Communications Engineering at National Sun Yat-sen University, Kaosiung 80424, Taiwan (e-mail: tcwang@faculty.nsysu.edu.tw). Digital Object Identier 10.1109/TCSI.2010.2096117

induced if the nodes become unavailable (e.g., as a result of consuming all their energy) or unreliable (e.g., as a result of intermittent malfunctions). Hence, the design of a robust distributed estimation for fusion center in WSN is essential. The problem of distributed estimation systems have attracted signicant interest in recent years [2][5]. The research focuses principally on the problem of developing energy-efcient and bandwidth-constrained designs. By contrast, the problem of enhancing the fault tolerance capability of decentralized estimation systems has attracted relatively little attention. In practical networks, fault tolerance is a critical concern since the sensor nodes are invariably battery-powered and randomly deployed, and are therefore not easily recharged or replaced. Furthermore, the sensors are generally deployed in outdoor or similarly harsh environments, and thus the occurrence of sensor failures or malfunctions isalmostinevitable.To solvetheproblem,wehaveproposedacollaborative fault detection (CSFD) scheme [6] to detect the faulty nodes within the network such that their quantized messages can be excluded from the parameter estimation process. Some related works about variants of enhancing the fault tolerant capability of decentralized estimation systems have been considered in the following literature. I. Rapoport et al. [7] addressed the problem of sensor fault detection and estimation in dynamic systems using an a priori sensor-fault model. Meanwhile, Delouille et al. [8] used an embedded subgraphs algorithm to design a robust distributed estimation scheme for sensor networks in which the sensors observe different physical phenomena. The scheme considers only temporary communication faults such as failing links and sleeping nodes, whereas the robust CSFD estimation scheme proposed considers all manner of possible sensor failures. Ishwar et al. [9] utilized a packet-erasure model to examine various aspects of distributed estimation in WSN, including its robustness toward sensor unreliability, its power-cycling characteristics, and the effects of uncertainties in the wireless transmissions. However, the estimation problem assumes that the fusion center requires the ability to discriminate between the local messages received from normally operating nodes and those messages received from faulty nodes. In [6], CSFD takes the concept of collaborative signal processing to perform robust distributed estimation. Specically, this work employs the homogeneity test [10] to implement CSFD scheme to detect the faulty nodes within the network such that their quantized messages can be excluded from the parameter estimation process. Utilizing the proposed CSFD mechanism, the fusion center identies the faulty nodes with the WSN and then excludes theirs information when estimating the parameter of interest. With the aid of CSFD scheme, different sensor faults can be tolerated to improve the performance of estimating the parameter of interest. As predicted, CSFD

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performs better than the conventional approach in estimating theta in terms of different sensor faulty types and faulty number. In the detecting process, CSFD requires such extensive computations as logarithm and division though it achieves very good performance. In many real-time WSN applications, the fusion center might be implemented with the ASIC and included in a standalone device, so a simple and good distributed estimation scheme of lower computational complexity is extremely desired. This motivation makes us modify CSFD and propose an efcient collaborative sensor fault detection (ECSFD) scheme and its VLSI architecture in this paper. Compared with CSFD, ECSFD performs slightly better and requires only about 55% of computations. Therefore, it does qualify as a good candidate for hardware implementation. In the recent years, some VLSI circuits for transmitter, receiver, demodulator, sensor node, and specic detector in WSN have been presented. In [11], an on-off LC oscillator-based ultrawideband (UWB) impulse radio transmitter for long-range application is presented. Verhelst et al. proposed a quadrature analog correlation receiver for UWB [12]. In [13], a demodulator architecture capable of dealing with most of the previous limitations in an ASK-utilized medical implant, especially in want of being powered through wireless delivering, is proposed. In [14], Alippi et al. proposed a low-power maximum power point tracker (MPPT) circuit, which conveys solar energy into rechargeable batteries for wireless sensor nodes. Furthermore, Aguilar-Ponce et al.. proposed a VLSI architecture for Wronskian Change Detector [15] and Goldberg et al. proposed a lowpower VLSI wake-up detector for the use in an acoustic surveillance sensor network [16]. To our knowledge, ECSFD circuit is the rst ASIC implementation for fault-tolerance fusion center for distributed estimation and no related state-of-the-art ASIC design exists in the literature. The remainder of the paper is organized as follows. Section II presents the system model, sensor fault models and the overview of CSFD scheme. The details of ECSFD are described in Section III. Section IV shows the VLSI architecture of ECSFD. Section V presents the performance and implementation result of ECSFD. Conclusions are nally drawn in Section VI. II. OVERVIEW OF CSFD Fig. 1 illustrates the basic structure of the distributed estimation network considered in the present study. The Bayesian formulation is considered here. Let be a nite set corresponding to the sensor nodes observing sensor measurement sequences generated from a common status of phenomenon , the parameter under estimation. It is assumed that the distribution of is known and is denoted by . The observation sequences taken by sensor are denoted by , where is the node index and is the time index. Every sensor node quantizes its own observations to output and send it to the fusion center. The local messages are mapped to a binary signal vector where is the number of bits used to represent the local message and is the number of partition levels at the local sensors. In the distributed estimation network shown in Fig. 1, two types of errors may affect the received quantized messages at

Fig. 1. System model for distributed estimation fusion scheme.

the fusion center. The rst error is caused by the faulty node. The considered WSN herein is very possible to contain faulty nodes because of random deployment in a harsh environment. The second error is the channel transmission error due to interference or noise. In this situation, the received at the fusion center may not be equal to and we denote by for all and . Consider the case where the fusion center estimates at some arbitrary time . Note that in performing this estimation process, all the messages received from the local nodes up to time , i.e., are available at the fusion center. If sensor faults exist within the network, the estimated value of is liable to deviate signicantly from the true value. To solve the problem, CSFD adopts the concept of collaborative signal processing to identify the faulty nodes , where is the set of faulty nodes at time . Then, the fusion center can eliminates the local message associated with these nodes , and makes the nal estimate at time , based only on the censored messages, , where denotes and . In CSFD, the following sensor fault models are considered in order to include different misbehavior. Given partition levels for the quantizer, then we denote when node operates in a fault-free manner. In one fault model, the output of local quantizers is independent of the parameter . For example, a stuck-at fault may occur in which the output of the affected node is frozen at a xed quantization level. Alternately, a random fault may arise in which the distribution of the output of a faulty node is different from the normal situation and equals a particular value regardless of the true parameter. By contrast, some nodes may exhibit a -dependent error in which a sensor offset bias transforms the sensor measurement uniformly to a certain value and therefore alters the value of . The process of CSFD can be divided into three stages. The rst stage is to measure the faulty weights of all nodes. Then, the faulty nodes are determined. The nal distributed estimate is generated in the last stage. The detail of each stage is described as follows. Measuring Faulty Weight: This stage consists of two steps and its aim is to decide the faulty weight of each node. The faulty weight is used to measure the deviation of a node. In the

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rst step, we compute the number of and denote it as .

received from sensor

(1) where is the indicator function. As mentioned in [17], the KullbackLeibler (K-L) distance between distributions can be used to measure sensor-fault deviation. In CSFD, we use K-L distance to estimate the faulty weights of all sensors. According to the local decisions , the K-L distance for node is employed to measure the distribution distance from average sensor weight to faulty sensor weight , and is dened as
Fig. 2. Algorithm of CSFD.

(2) where (3) Determining Faulty Nodes: The aim of this stage is to decide which sensor nodes are faulty, based on the faulty weights computed in the previous stage. First, all sensor nodes are sorted in descending order based on their magnitude of to get the faulty-weight-oriented sequence, . After is determined, we can obtain the candidate set of faulty sensors, denoted as where is the possible number of faulty nodes, and let represent the empty set . In order to determine the value of , the following homogeneity testing problem can be formulated to test for the existence of a set of sensor nodes at time .

(4) Then, the following statistics are utilized for homogeneity testing to determine whether or not a candidate set is : (5) where

In CSFD, the maximum value of is constrained to the sensor faults search policy, i.e., , where is the maximum number of possible faulty nodes. The step of determining faulty nodes of CSFD scheme can be summarized as follows: CSFD-1: Set and assign the required signicance level . In addition, choose suitable value of in accordance with the network requirements and/or any prior information regarding the failure characteristic of the network. CSFD-2: Perform (6) for the candidate set . If is accepted, terminate the CSFD process and determine the nal decision . If is rejected, increase the value of by 1. CSFD-3: If , terminate the CSFD process and determine . If , accept hypothesis and decide . Otherwise, rerun to Step CSFD-2 and repeat Steps CSFD-2 to CSFD-3 iteratively until is determined Making Distributed Estimation: Once the set of faulty nodes is determined, the fusion center removes the quantized messages of the faulty nodes and performs the parameter estimation. Then, the estimate obtained by minimum mean square error (MSE) criterion is adopted and is given by (7) Fig. 2 shows the CSFD algorithm in the C language style. More details of CSFD can be found in [6]. III. EFFICIENT CSFD

Utilizing the statistic , the binary hypothesis testing problem given in (4) can be set as follows:

(6) where is a threshold indicating the crit-

ical value of the chi-square distribution with degrees of freedom at a signicance level .

CSFD performs better than the conventional approach with regard to fault tolerance. However, there are three difculties to be overcome for implementing CSFD with a VLSI circuit. The rst one is that it requires some extensive and complex computations, such as logarithm and division in the detecting process (see (2)(6)). The second difculty is that the integration required for the estimate of in (7) is quite complex. The last difculty is that the calculation of numerical integration needs many bits. In order to overcome these difculties, we modify CSFD and propose an efcient collaborative sensor

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fault detection (ECSFD) scheme in this paper. ECSFD is simple and requires lower computational complexity, thus lower hardware cost and power consumption can be achieved. Furthermore, ECSFD achieves almost the same performance as CSFD. The details of ECSFD are described in the following. A. Avoid the Logarithm and Division Operations To avoid the logarithm and division operations required in (2), a simple and efcient sensor faulty weight estimate method is provided. We take advantage of collaborative signal processing to estimate the sensor faulty weight. More concretely, without knowing the true distribution of , most nodes in the networks can be reasonably assumed to normally report their decisions inferring the true distribution of to the fusion center. If the sensor behavior deviates from the average more obviously, the sensor sensor behavior has larger faulty sensor weight. Hence, the faulty weight of the sensor nodes can be estimated by the sum of the absolute differences between and

TABLE I MSE OF CSFD AND ECSFD FOR DIFFERENT TYPES OF FAULTY NODES

TABLE II COMPUTING TIME OF ECSFD FOR TWO PROCESSORS

(11) (8) Besides, the nal purpose of this stage is to calculate the for obtaining the faulty-weight-oriented sequence . By multiplying all with a constant simultaneously, we can further reduce the computational complexity of without affecting the decided . Finally, the can be estimated with less computational complexity and is given as (9) In the stage of determining the faulty nodes, we must calculate rst. The computation of suffers from the problem of massive division which needs large computational complexity. In order to overcome the problem, the hypothesis testing can be rewritten in the following formation by multiplying (6) with a constant: where and . The required division operation in (5) is replaced with multiplication and the corresponding computational complexity cost can be reduced. Using (9) and (11), we can choose the according to the step of determining faulty nodes of CSFD scheme listed in Section II. After deciding , ECSFD using the same operation in (7) to obtain the . By implementing (9), (11), and (7), ECSFD requires less computation than CSFD, and can achieve quite good performance with regard to fault tolerance. We show the performance comparison of CSFD and ECSFD for different types of faulty nodes in Table I. Obviously, the distributed estimation performance of ECSFD is a little better than CSFD. To verify the computational complexity, both CSFD and ECSFD ((9), (11), and (17)) are implemented in C language on the 2.8 GHz Pentium 4 processor with 512 MB memory and the 520 MHz INTEL XScale PXA270 with 64 MB memory, respectively. Table II shows the computing time for the two processors. ECSFD requires about 55% of CSFDs computing time on Pentium 4 processor. B. Simplify the Integration (10) Substituting (5) to (10) gives However, minimum MSE in (7) needs integral operation which is difcult for hardware implementation. Therefore, the numerical integration is used in the stage of making distributed estimation. (7) can be written in the following form:

(12)

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where (13) In the issue of wireless communication, the additional noise model can be reasonable assumed as a Gaussian function . Therefore, can be given as (14) where denotes the quantized range of . Let and denote the number of received from in the fusion center. Then can be calculated by the following equation: (15) can be approximated by Using the numerical integration, integrating from to with an interval (16) In addition, the value of prior distribution of . , and are decided according to the

as 8 and 3, respectively, in the current implementation. This setting, as mentioned in [6], is suitable for general applications in WSN. Furthermore, the word length of signals is decided based on the following two considerations: a) The performance of ECSFD circuit must be comparable to that of CSFD. b) The hardware cost of ECSFD circuit must be minimized. After careful analysis and software simulation, we have chosen the 11-bit widths for representing different signals in the ECSFD circuit to meet the precision requirement and maintain the acceptable performance. The VLSI architecture of ECSFD consists of a logarithm unit, antilogarithm unit, sort unit, register le, 11 11 multiplier unit, comparator unit, and adder/subtractor unit connected to a shared bus. A top-level FSM coordinates the operations among these functional units. In the following subsections, the implementations of four important operations, multiplication, logarithm/antilogarithm, and sorting, are described in detail. A. Multiplication Since the largest width of the signals in ECSFD is 11-bit, a basic 11 11 multiplier is developed where the multiplier is denoted as , the multiplicand is denoted as , and the product is denoted as . Many multiplication operations are required in ECSFD. Since the width of most signals is 11-bit, we need the 11 11 multiplier. These multiplication operations are performed sequentially at different time instant, so we can apply the concept of hardware resource sharing and design special-purpose multipliers (11 22, 22 22, and 22 33) to implement them. Hence, we utilized the 11 11 multiplier to realize the four different multiplications where the multiplier, multiplicand and product are all realized with different bit widths of integer and fractional parts for respective precisions. Let mean that the bit widths of the integer and fractional parts of multiplier are bits and bits respectively. The input/output precisions of four modes based on our 11 22, 22 22, and 22 33 multipliers are dened in Table III respectively. For most WSN applications, the cost issue is more important than timing performance in the design of fusion center. Hence, the 11 22, 22 22, and 22 33 multipliers are realized with a normal 11 11 multiplier circuit (multiplying two 11-bit operands to produce a 22-bit product) and a dedicated control circuit under multicycle implementation to reduce the hardware cost. With the help of the control circuit, the 11 11 multiplier can implement all the required multiplication operations for different modes with multiple clock cycles. The full-precision 11 22 multiplier is realized with a 11 11 multiplier under multicycle implementation. Let , and represent the 11-bit data, and is multiplied by through the 11 22 multiplier to get the product result . The strategy of synthesizing the 11 22 multiplier with a 11 11 multiplier is shown in Fig. 3. The full-precision 22 22 and 22 33 multipliers are designed in the same way as the 11 22 multiplier. The strategies of synthesizing the 22 22 multiplier with a 11 11 multiplier for mode 2 and 3 are shown in Fig. 4(a) and (b) respectively. Furthermore, the strategy of synthesizing the 22 33 multiplier with a 11 11 multiplier is shown in Fig. 5. Specially, some bits

C. Transform the Numerical Integration However, the bit width required for the numerical representations of the numerator and the denominator in (16) are is large enough. With the aid of logaquite large when and rithm property, we transform to and , which need smaller bit width, respectively. Hence, (16) can be rewritten as (17) (18) Then, all the items of the numerators and denominators are sorted to nd the one with the maximum exponent denoted as . According to the found value, all the other items which satisfy or are selected to . (The selected items calculate the value of approximated are times larger than the ignored ones.) With the aid of the can be calculated logarithm and the sorting process, the efciently. By implementing (9), (11), and (17), ECSFD is suitable for hardware implementation and can achieve quite acceptable performance with regard to fault tolerance as demonstrated in Section V. IV. CHIP ARCHITECTURE FOR ECSFD Observing the required operations in ECSFD, we develop a low-cost VLSI architecture for ECSFD where and is set

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TABLE III INPUT/OUTPUT PRECISIONS OF THE 11 22, 22 MULTIPLIERS

22,

AND

22

33

Fig. 5. The strategy for synthesizing the 22 tiplier.

33 multiplier with a 11

11 mul-

Fig. 3. The strategy for synthesizing the 11 tiplier.

22 multiplier with a 11

11 mul-

Fig. 6. Flow chart of the antilogarithm conversion.

Fig. 4. The strategy for synthesizing the 22 22 multiplier for different modes with a 11 11 multiplier. (a) Mode 2. (b) Mode 3.

of the output product is ignored to save the required registers since they have very little inuence on the calculated results. This multimode multiplier realized with multicycle implementation can meet the required precision of ECSFD and achieve the goal of low cost design. B. Logarithm and Antilogarithm As shown in (17), some logarithm and antilogarithm conversion operations are required in ECSFD. Let and represent the input and output, thus the logarithm conversion can be denoted as where is the 22-bit input and is the converted 11-bit output. The reason of using is to match the binary representation. Using a proper lookup table, we can implement the logarithm conversion with a dedicated control circuit. In our implementation, the prior distribution of is a Gaussian function (0, 0.5), the range of the integration is from to 3, the integral interval, is set as 0.05, and .

Hence, the lookup ROM table is constructed with 121 6 entries ( , and ). The antilogarithm conversion operations are also performed based on a lookup table. Let and represent the input and output, thus the antilogarithm conversion can be denoted as , where is the 10-bit input and is the converted 22-bit output. The exponents of the selected items in (18) are normalized (subtracted by a common constant) to the range from 0.00 to 10.00 without affecting the approximated . Fig. 6 shows ow chart of antilogarithm computation in our design. We use 10-bit to represent . The lookup table is constructed with 10 entries and each stores the 17-bit value of , where is an integer to represent the position number and . At every clock cycle, if , we nd by looking up the ROM with the current , multiply it by . Otherwise, remains the same value. The 22 22 multiplier (mode 3) is accessed 0 to 9 times to get the result of 22-bit . After getting the values of numerators and denominators in (18) through the antilogarithm module, can be calculated by a divider. Finally, the division required in (18) is replaced by repeated subtractions to reduce the hardware cost. C. Sorting In ECSFD, the faulty weights of sensors are represented as and is 3 in the current implementation, so we need to nd the three biggest values from these eight

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Fig. 9. Chip layout of ECSFD. TABLE IV IMPLEMENTATION RESULT OF ECSFD

Fig. 7. The structure of the sort module.

Fig. 8. The state diagram of the sort module.

numbers and identify their node indexes for the following usage. The order of the other ve smaller values is not important. Since , and are calculated and generated sequentially in the previous stage, we design a special purpose insertion sorting circuit which maintains both the three bigger values and their indexes through the whole sorting procedure. Fig. 7 shows the structure of controller and data path in sort module. Moreover, the state diagram of sort module is shown in Fig. 8. The calculated data are inputted to the sort module one by one in turn. The start signal will initialize the three registers with a small number and enable the sorting procedure. The current input is compared with the values in one by one from to , and the control signal will be set as 1 if the input is larger than . As soon as , the replacing procedure at is performed to save the current input to a proper register . Thus, the input value can be inserted to an appropriate position and is satised. The sort module spends 1 to 3 clock cycles to nd the appropriate position for inserting the input, and the replacing operation needs another 1 clock cycle. The corresponding sensor numbers are recorded in the three registers and will be nally outputted. V. IMPLEMENTATION RESULTS AND EVALUATION The proposed VLSI architecture of ECSFD was implemented by using Verilog HDL. We used SYNOPSYS Design Vision to synthesize the design with TSMC 0.18 m cell library. The

layout for the design was generated with SYNOPSYS Astro (for auto placement and routing), and veried by MENTOR GRAPHIC Calibre (for DRC and LVS checks), respectively. Nanosim was used for postlayout transistor-level simulation. Finally, we employ SYNOPSYS PrimePower to measure the total power consumption. The performance of ECSFD hardware circuit is only little worse (about 2.5% loss) than that of ECSFD software according to our simulation result. The layout and implementation result of the proposed ECSFD circuit are shown in Fig. 9 and Table IV, respectively. The circuit contains 22589 gates and its core size is about 571 559 m . It works with a clock period of 6 ns and operates at the clock rate of 167 MHz. It can produce an output estimation in about 0.0625 microsecond. The power consumption is 12.83 mW with 1.8 V supply voltage. To reduce the power consumption, the proposed circuit is designed to operate at a lower clock rate. For WSN applications such as the re monitoring and environmental temperature/humidity monitoring systems, the level of emergency is not very high, thus the fusion center is expected to make an output estimation with lower update rate, such as a few seconds or minutes. ECSFD can run the high-speed design (167 MHz) once, and then enters sleep mode until the next computation is required. In the high-speed implementation, it can produce an output estimation in about 0.0000625 s and its power consumption is 12.83 mW. Assume the power consumption of sleep mode is mW. Then, according to the high-speed implementation, the power consumption of the ECSFD chip, which is fast enough to output one estimation in 1 s, can be calculated as the following:

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Fig. 10. Performance comparison of CSFD, ECSFD circuit, and the conventional approach in a fault-free WSN.

Fig. 12. Performance comparison of CSFD, ECSFD circuit, and the conventional approach in a WSN with two sensors with random faults, i.e., .

Fig. 11. Performance comparison of CSFD, ECSFD circuit, and the conventional approach in a WSN with two sensors with stuck-at faults, i.e., .

Fig. 13. Performance comparison of CSFD, ECSFD circuit, and the conventional approach in a WSN with two faulty sensors characterized by and .

For verication, the architecture was also implemented on the Altera Stratix II EP2S60F1020C5 FPGA platform. The implementation result shows that our circuit generates correct output under the operating clock frequency of 87.31 MHz with 2013 logic elements and 1435 registers. Furthermore, we investigate the performance of ECSFD circuit in the presence of different sensor faults. The evaluation is performed in various faulty scenarios where the fault types and the number of faulty nodes are not known in advance. This simulation results obtained for the MSEs of both estimation schemes are also compared with those obtained using a conventional distributed Bayesian estimation system in which the unreliable local messages are included within the parameter estimation. The sensor measurements are processed using an additive noise model, and the sensor observations are given by (19) where is drawn from a Gaussian distribution with zero-mean and a variance , and , i.e., the additive noise at node at time , also has a Gaussian distribution with zero-mean and a variance . It is assumed that all the local nodes apply

the LloydMax quantizer [18] with partitions are given by

. The corresponding

(20) The communication channels between the local sensors and the fusion center are assumed to be binary symmetric channels with a crossover probability of . A value of is specied in all the simulations. Fig. 10 compares the estimation performance of CSFD, ECSFD, and the conventional scheme for the case in which all of the sensors within the network are fault-free. It is evident that the MSE values of CSFD and ECSFD are virtually identical to those of the conventional scheme, implying that CSFD and ECSFD have exceedingly small possibility to remove the normally operating nodes. Fig. 11 compares the estimation performance of the three schemes when two of the nodes within the WSN experience

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stuck-at-zero faults, i.e., . Note that the two faulty nodes are drawn uniformly from the eight nodes within the network. The results conrm that both robust estimation schemes result in a signicantly lower MSE than that obtained using the conventional approach. Moreover, ECSFD performs slight better than CSFD. Fig. 12 illustrates the performance of the three estimation schemes for the case in which two of the eight sensors in the WSN experience a random fault, i.e., . Again, the results conrm that both CSFD and ECSFD schemes yield a far better estimation performance than the conventional approach. The scenario with two different sensor-fault types is simulated in Fig. 13. This gure compares the performance of the three schemes for the case in which the network has two faulty sensors characterized by and , respectively. The objective of this evaluation is to investigate the ability of the proposed estimation schemes to cope with most sensor-fault types without any a priori knowledge of the sensor-fault models. Once again, the results conrm that both CSFD and ECSFD schemes rapidly converge to far lower values of the MSE than that obtained using the conventional method, even when the network is in the presence of the combined sensor-faults. Furthermore, it is observed that the MSE results obtained using the ECSFD scheme are slightly lower than those obtained from the original CSFD scheme. Through the above performance evaluation, we conclude that ECSFD is more fault-tolerant than the conventional approach with a very close level performance as that of CSFD. VI. CONCLUSION The ECSFD is designed in order to reduce the computational complexity required for CSFD in this paper. Based on ECSFD, a low cost VLSI architecture is proposed for fault-tolerant fusion center in WSN. With the multicycle structure, the proposed VLSI architecture can work fast enough to provide the real-time operation but only needs a low hardware cost. According to the performance evaluation, the VLSI architecture for ECSFD can work better than the conventional approach and its performance is close to that of CSFD. REFERENCES
[1] I. F. Akyildiz, W. Su, Y. Sankarasubramaniam, and E. Cayirci, A survey on sensor networks, IEEE Commun. Mag., vol. 40, no. 8, pp. 102114, Aug. 2002. [2] Y. Zhu, E. Song, J. Zhou, and Z. You, Optimal dimensionality reduction of sensor data in multisensor estimation fusion, IEEE Trans. Signal Process., vol. 53, no. 5, pp. 16311639, May 2005. [3] R. Niu and P. K. Varshney, Target location estimation in sensor networks with quantized data, IEEE Trans. Signal Process., vol. 54, no. 12, pp. 45194528, Dec. 2006. [4] A. Ribeiro and G. B. Giannakis, Bandwidth-constrained distributed estimation for wireless sensor networksPart I: Gaussian case, IEEE Trans. Signal Process., vol. 54, no. 7, pp. 27842796, Jul. 2006. [5] A. Ribeiro and G. B. Giannakis, Bandwidth-constrained distributed estimation for wireless sensor networksPart II: Unknown probability density function, IEEE Trans. Signal Process., vol. 54, no. 7, pp. 27842796, Jul. 2006. [6] T.-Y. Wang, L.-Y. Chang, and P.-Y. Chen, A collaborative sensorfault detection scheme for robust distributed estimation in sensor networks, IEEE Trans. Commun.., vol. 57, no. 10, pp. 30453058, Oct. 2009.

[7] I. Rapoport and Y. Oshman, A new estimation error lower bound for interruption indicators in systems with uncertain measurements, IEEE Trans. Inf. Theory, vol. 50, no. 12, pp. 33753384, Dec. 2004. [8] V. Delouille, R. N. Neelamani, and R. G. Baraniuk, Robust distributed estimation using the embedded subgraphs algorithm, IEEE Trans. Signal Process., vol. 54, no. 8, pp. 29983010, Aug. 2006. [9] P. Ishwar, R. Puri, K. Ramchandran, and S. S. Pradhan, On rateconstrained distributed estimation in unreliable sensor networks, IEEE J. Sel. Areas Commun., vol. 23, no. 4, pp. 765775, Apr. 2005. [10] R. C. Elandt-Johnson, Probability Models and Statistical Methods in Genetics. New York: Wiley, 1971. [11] S. Diao, Y. Zheng, and C.-H. Heng, A CMOS ultra low-power and highly efcient UWB-IR transmitter for WPAN applications, IEEE. Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 3, pp. 200204, 2009. [12] M. Verhelst and W. Dehaene, Analysis of the QAC IR-UWB receiver for low energy, low data-rate communications, IEEE. Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 8, pp. 24232432, 2008. [13] C.-S. A. Gong, M.-T. Shiue, K.-W. Yao, T.-Y. Chen, Y. Chang, and C.-H. Su, A truly low-cost high-efciency ASK demodulator based on self-sampling scheme for bioimplantable applications, IEEE. Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 14641477, 2008. [14] C. Alippi and C. Galperti, An adaptive system for optimal solar energy harvesting in wireless sensor network nodes, IEEE. Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 17421750, 2008. [15] R. Aguilar-Ponce, J. Tessier, A. Baker, C. Emmela, J. Das, J. L. Tecpanecatl-Xihuitl, A. Kumar, and M. Bayoumi, VLSI architecture for an object change detector for visual sensors, in IEEE Workshop Signal Process. Syst. Design Implementation, 2005, pp. 290295. [16] D. H. Goldberg, A. G. Andreou, P. Julian, P. O. Pouliquen, L. Riddle, and R. Rosasco, A wakeup detector for an acoustic surveillance sensor network: Algorithm and VLSI implementation, in Proc. IPSN04, pp. 134141. [17] T. M. Cover and J. A. Thomas, Elements of Information Theory. New York: Wiley, 1991. [18] S. P. Lloyd, Least squares quantization in PCM, IEEE Trans. Inf. Theory, vol. IT-28, pp. 129136, Mar. 1982. Li-Yuan Chang received the B.S. and M.S. degrees in computer science and information engineering from National Chi Nan University, Nantou Hsien, Taiwan, in 2004 and 2006, respectively. He is currently working toward the Ph.D. degree in computer science and information engineering at National Cheng Kung University, Tainan, Taiwan. His research interests include wireless sensor networks, distributed detection, and embedded systems.

Pei-Yin Chen (M08) received the B.S. and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1986 and 1999, respectively, and the M.S. degree in electrical engineering from Pennsylvania State University, State College, in 1990. He is currently a Professor in the Department of Computer Science and Information Engineering, National Cheng Kung University. His research interests include VLSI chip design, video compression, fuzzy logic control, and gray prediction.

Tsang-Yi Wang (S01-M04) received the B.S. and M.S. degrees from the National Sun Yat-sen University, Kaohsiung, Taiwan, in 1994 and 1996, respectively, and the Ph.D. degree in electrical engineering from the Syracuse University, Syracuse, NY, in 2003. From 2004 to 2006, he was an Assistant Professor in the Graduate Institute of Communication Engineering, National Chi Nan University, Nantou, Taiwan. In February 2006, he joined the faculty of the Institute of Communications Engineering, National Sun Yatsen University, Kaohsiung, Taiwan, as an Assistant Professor, and in August 2008 he became an Associate Professor.

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He is currently a Reviewer Editor of the Journal of Wireless Communications and Mobile Computing. His research mainly focuses on distributed detection and estimation with applications in wireless communications and wireless sensor networks. Dr. Wang received the 2008 Best Paper Award for Young Scholars awarded from IEEE Information Society Taipei Chapter and IEEE Communications Society Taipei/Tainan Chapter.

Ching-Sung Chen received the B.S. degree in computer science and engineering from Yuan Ze University, Taoyuan County, Taiwan, in 2008, and the M.S. degree in computer science and information engineering from National Cheng Kung University, Tainan County, Taiwan in 2010. His research interests include VLSI chip design and embedded systems.