IEEE JOURNALOF SOLID-STATE (CIRCUITS, SC-9, O.6,DECEMBER1974 VOL.

353

Macromodeling

of Integrated Circuit

Operational Amplifiers
GRAEME R. BOYLE, BARRY M. COHN; DONALD O. PEDERSON, JAMES E. SOLOMON, MEMBER, IEEE
FELLOW, IEEE, AND

AbstracfA macromodel has been developed for integrated circuit (IC) op amps which provides an excellent pin-for-pin representation. The model elements are those which are common to most circuit simulators. The macromodel is a factor of more than six times less complex than the original circuit, and provides simulated circuit responses that have run times which are an order of magnitude faster and less costly in comparison to modeling the op amp at the electronic device level. Expressions for the values of the elements of the macromodel are developed starting from values of typical response characteristics of the op amp. Examples are given for three representative op amps. In addition, the performance of the macromodel in linear and nonlinear systems is presented. For comparison, the simulated circuit performance when modeling at the device level is also demonstrated.

1. INTRODUCTION
NTEGRATED I circuit (IC) simulators have proven

to be a useful tool i;o the IC design engineer. None-

theless, their widespread acceptance in the design of large-scale integrated circuits and IC subsystems has been impeded ing by excessive problems. simulation Present costs and increassimulators model convergence

semiconductor devices at the p-n junction and 2-terminal element level. Becaqse c,f the large number of these devices in large-scale the computers capability, computer. analysis IC yystems, the analysis capability, simulator numerical simulation can surpass circuit-size of the the have memory

or the inherent the required to this problem:

accuracy time

Even if ~n adequate financially impractical.

simulator

and computer makes which describes amplifiers

are available, one solution

Thi~ paper

macromodels

been developed and comparators.

for ICS such as operational

The idea and use of macromodels in electronic circuit design is very common at the system level. For example, in developing an analc)g signal processor, amplifiers, one might utilize a number of ideal voltage integrators,

Manuscript received August 2, 1974; revised August 16, 1974. This research was sponsored in part by the Joint Services Electronics Program under Contract F44620-71-C-0087 and by the National Science Foundation under Grant GK-17931. This paper was presented at the International Solid-State Circuits Conference, Philadelphia, Pa., February 1974. G. R. Boyle and D. O. Pederson are with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California, Berkeley, Calif. B. M. Cohn is with Inte)l Corporation, Santa Clara, Calif. J. E. Solomon is with National Semiconductor Corporation, Santa Clara, Calif.

and other subsystem blocks. In effect, a variety of zeroorder circuit models are used. To determine the actual system performance, a prototype circuit is constructed and tested at the device level. The size and complexity of todays inexpensive ICS are large; therefore, the cost of using present simulators for design and evaluation can be very large. The cost for large ICS can only be justified if very large manufacture is anticipated. The costs and other problems can be relieved by the clevelopment of macromodels for ICS which provide an adequate pin-for-pin representation of the IC. For digital ICS, logic simulation and macromodels have been developed for digital logic blocks [1], [8]. For analog ICS, this paper describes a very effective macromodel that has been developed for IC op amps [2], [3], [9]. The aim of macromodeling is to obtain a circuit model of an IC or a portion of an IC which has a significantly reclucecl complexity to provicle for smaller, less costly simulation time, or to permit the simulation of larger ICS or IC systems for the same time and cost. In the macromodel for IC op amps shown in Fig. 1, a reduction of approximately 6 in branch and node count has been achieved while providing a very close approximation to the actual performing op amp, i.e., accurate modeling of the input and output characteristics, differential- and common-mode gain versus frequency characteristics, quiescent dc characteristics, offset characteristics, and largesignal characteristics, such as slew rate, output voltage swing, and short-circuit current limiting. Further, since much of a simulation run is involved with iterative analysis to an equilibrium circuit solution, the reduction of 60 to 80 p-n junctions in an actual op amp to the 8 junctions in the macromodel of Fig. 1 indicates better how much faster and cheaper can be the simulation using the macromodels instead of device-level moclels. The results with amplifiers, timers, and filters that are cited in this paper show that a reduction in time of 6 to 10 is typical. In many design or evaluation situations, it is not necessary to model an op amp in all of its performance characteristics. For example, maximum short-circuit current limiting may not be of interest. If the elements in the macromodel which provide this feature are eliminated,
further simplification of the macromodel is obtained. As an example, the simulation time of the filter in Section IV is reduced by a factor of 1.4 if the current and voltage limiters are omitted.

354 7 (Vcc)

IEEE JOURNALOF SOLID-STATE CIRCUITS, DECEMBER1974

1 RCI

Rcz

Vc+ :iRp
6

I 11 c,
+va

3. (+) @

-~
INPUT STAGE

-IN TERSTAGE OUTPUT STAGE

Fig.1. Circuit diagram of the op amp macromodel.

II. MACROMODEL

DEVELOPMENT

+&

The circuit model for an IC op amp which is developed in this paper is shown in Fig. 1. The configuration, with a suitable choice of parameters and elements, accurately models a broad class of IC op amps. For a given Op amp, the model provides an essentially pin-for-pin correspondence with the op amp, and accurately represents the circuit behavior for nonlinear dc, ac, and largesignal transient responses. The circuit of Fig. 1 is subdivided into three stages. The input stage consists of ideal transistors ~1 and Q,z and the associated sources and passive elements, This stage produces the necessary linear and nonlinear differential-mode (DM) and common-mode (CM) input characteristics. For convenience, the stage is designed for unity voltage gain. The stage can be designed to provide desired voltage and current offsets. As brought out in the next section, the capacitor CB is used to introduce a second-order effect for the slew rate [4], and thb capacitor Cl introduces a second-order effect to the phase response. The DM and CM voltage gains of the op amp are provided by the linear interstage and output stage elements consisting of Gm, G,., R%, Gb, and Roz. The function of each element is presented in the next section. The dominant time constant of the op amp is produced with the internal feedback capacitor C2. A feedback connection in the macromodel is used for Ca in order to provide
the necessary ac output resistance change with frequency. In addition, the two nodes of C2 can be made available to the outside can introduce be added might world in order that the circuit compensation designer as the same modification

Q,2 Q9

39 k R5

Q,, [
3k

Q,O
R4
I INPUT STAGE I ,N:;TX

:j;:~,c. NETWORK

1
SA 6 Q,T 100 ~ R8
OUTPUT STAGE

Q13

Fig. 2. Circuit diagram of the ICL8741 op amp. ,., ,,. ., and Go produce the desired maximum short-circuit cur-

rent. The elements D3, Vc and 114j VE are voltage-clamp

op amp. Notice the complete isolation that exists between the input and the interior stages. This leads to a simplification of the frequency and the slew i-ate performances. The output stage provides the proper dc and ac output resistance of the op amp. The elements Dl, Dz, Rc,
to the actual

circuits to produce the desired maximum voltage excursion. The circuit model of Fig. 1 has been developed using two basic macromodeling techniques: simplification and build-up. In the simplification technique, representative portions of op amp circuitry are successively simplified by using simple ideal elements to replace numerous real elements. Thus, the final model using this approach bears a strong resemblance to the real circuit. In Fig. 1, the input stage design is an example of the simplification technique. In the build-up technique, a circuit configuration composed of ideal elements is proposed to meet certain external circuit specifications without necessarily resembling a portion of an actual op amp circuit configuration. The build-up technique is employed in the development of the output stage. To illustrate these aspects further, consider the schematic diagram shown in Fig. 2 of the 741-type op amp

BO1-LEtC1l.: e MACROMODELING OPERATIONAL OF AMpL~~lERs TABLE I

DI:SICiN I?CjUziTIONSFOR THE OP ANIP hL4cRoMoD,m,

355

V, = ~

= 25.85 mV for 300 K

A

1s, = I.sD, = 1~~4 = 8.10- R, = 100 k!l

c, = $ tan Ad l?p = ( Vcc + Ga = I/Rc , V. E)/(F, VCC(.21CJ V. EIEE)

C.=+-c, R

Gc. =

1 R,, (CiMRR)

R,, = Ro-.c Roz = Rout Rol

1.2=1.+
~, =
(32 =
IcI/IBI

avDRC1 Gb = R2ROZ Ix = (21 JGbR, Isc

IC2/IB2

R0,18C I SD1 ISD2 = Ix exp =

v,

R. = 200/IRB

s2=
1 = 9?n1

d +%)
v*/Icl

R., = l/2mfo ~BC,

(Intcrsil ICL8741 ). This type is the most common, general purpose IC op amp. In developing a macromodel using the simplification technique, the circuitry employed for biasing can be replaced with ideal passive elements (pure current and voltage sources). Similarly, the active loacl and balance-to-unbalance converter in the input stage can be replaced with ideal elements. Finally, it is not necessary to use composite transistors in the input stage. Thus, as shown in Fig. 1, a, simple differential stage can be proposed to moclel accurately the nonlinear input characteristic of the op amp. The op amp macromodel is developed keeping in mind existing IC simulators. Therefore, the model contains only elements which are common to most IC simulators (i.e., resistors, capacitors, inductors, dependent current sources, independent sources, diodes, and bipolar transistors). In addition, effort is made to minimize the number of p-n junctions. These nonlinear elements make necessary iterative analysis to obtain the equilibrium state of the circuit. A reduction of the number of nonlinear elements leads to smaller simulation time. For the input stage, our investigations showed that at least four ideal junctions were necessary to provide the needed balanced, nonlinear behavior in the macromodel.

It was determined that the simplest arrangement is that of Fig. 1 where the four ideal junctions were obtained with two ideal transistors, each mocleled with the lowest order EbersMoll (EM ) transistor model which includes two ideal p-n junctions and two dependent current sources. For the output stage, a simplified model of an actual op amp does not provide the best solution. A strippecldown class-AB stage with ideal transistors leads to a branch count, of over 13 in comparison with 11 branches in the output stage of Fig. 1. In acldition, the class-AB stage must be augmented with voltage limiters in the drive circuitry to limit the voltage excursion at the transistor bases to the supply potentials. It was found that the idealized built-up procedure provides an output stage which is considerably simpler. III. PARAMETERS
AND ELEMENT OF THE MACROMODEL VALUES

In this section, expressions are developed to relate the performance of the op amp and the macromodel to the parameters and elements of the macromodel. A summary of all design equations is presented in Table I. The determination of the element values of the macro-

356

IEEEJOURNALOF SOLID-STATE CIRCUITS, DECEMBER1974 vos = VBE1 vBE2

model proceeds from the input, transfer, and output characteristics of the op amp. The Input Stage: Icl and CB The value of the necessary collector current of the first stage is established by the slew rate of the op amp. If the op amp is connected as a voltage follower, the positive going slew rate L%+is (1) where an n-p-n stage has been assumed [4]. From a rearrangement of this expression This leads to I S2

= V.ln*.
S2

(9)

-%-=1+%1 0)

The Input Stage: R., and R,l Values for the resistors R,l = R,z are derived from the required value of the O dB frequency j~ ~Eof the fully compensated op amp. The O dB frequency is approximately the product of the DM voltage going a~~ and the 3 dB corner frequency fs tE of the gain function
fOdB = aVDj3dB.

For a quiescent situation, equal collector currents are used in the input stage ICZ = IcI. The negative going slew rate SE- is smaller because of the charge-storage effects in the input stage which is modeled by C~ [4]. (3) or c. 21C, = ~B_ c,. (4)

(11)

The corner frequency can be estimated using a Millereffect approximation in the interior stage.

(12) The DM voltage gain at very low frequencies is av~ = (G.RJ (G5ROJ. (13)

If SE < Sri-, the macromodel should be modified to use p-n-p transistors in the input stage. In the equations above #R,+and 81?- should then be interchanged. In addition to the transient slew rate effects, the element CE also introduces a desirable modification to the ac response of the CM gain of the macromodel. The Transistor Parameters The values of 131and #Z for the two ideal transistors are obtained from the specifications for the average input bias current IB and the desired level of input current offset IBOJ. IB1=IB+LB$, I.,=IF~.
& = ~.

G. is chosen to be equal to l/R,l in order to obtain a convenient slew rate expression as in (1). The last three expressions lead to (14) or R., = -.

2~f0BC2

(15)

Alternately, a relationship between written using (1).

fod~and

Sn+ can be

0 B = 2TRf;IcJ (5)

(16)

pl=~,

(6)

The voltage offset Vo, for the macromodel is produced by specifying different saturation currents Is for the two transistors. Assume a given value for Isl of QI (7) where VT = hT/q = 0.02585 V at T = 300 K. A similar expression holds for Icz = Icl Ic, = 1s, exp ~ The offset voltage is
VBE2 .

The value of R.l is usually small, of the order of 2/g~. Rcl and RC2 should be small in order that saturation of the input stage (and concomittent Iatchup of the op amp model) is avoided with maximum input. The resistances R,l and R.2 in the input stage are introduced to provide a degree of freedom with respect to slew rate and O dB frequency, and to simulate better certain op amps which use emitter resistors for slew rate enhancement, e.g., the LM118. R.l is found from the I)M voltage gain of the first stage, which for convenience is taken to be unity. v
_5_

DIR., + @,R., =
~

(B2 + DR.2

Vi*

1.

(17)

(A

ORI

(8)

BOYLEe~ Uz. MACROMODELINGOF OPERATIONAL : AMPLIFIERS

357

The Input Stage: IBB and Rn The value of the dc current source in the input stage for equal collector currents is (19) The resistor RE is added to provide a finite GM input resistance. Because the current source IDE is often rea]ized with an n-p-n transistor, the resistance RB is taken as its output resistance (20) where VA is the early voltage of the device. VA for a small n-p-n transistor is typically 200 V. The Input Stage: Cl To introduce excess phase effects in the DM amplifier response, another capacitor Cl is added in the input stage. The second pole of the DM gain function is located at p, = l/2Rc,C,. (21)

changed, the current drain varies almost linearly and RP will continue to model accurately the power clissipation. The Interstate: G., R,, and G,,,,

As indicated earlier, the coefficient G. of the voltage dependent current source Gava is chosen equal to l/R~l for convenience. Similarly, the value of Rz or G~ can be arbitrarily chosen. Only the product is determined by the DM gain. For active region considerations, the choice of R2 is not important. However, it must be kept in mind that the voltage response at node b is linear with R2. If too large a value of v~ is developed during a transient excursion through the active region of the op amp, a considerable discharge or recovery time can be encountered after the active region excursion. To prevent these discharge delays in relation to actual op amp behavior, a small value of R2 should be used. Empirically, a value of 100 k~ is found to be appropriate. If a second voltage-controlled current source is introduced across Rz, the CM voltage gain response can be introduced. The CM voltage gain in the input stage from vi. to v, is approximately unity since Rn is large. The CM voltage gain from the input to VOis then approximately

Notice that there is no interaction amongst the three capacitors because of the use of unilateral devices and stages. The excess phase at ~ = f. ~Bdue to the nondominant pole pz is

The differential voltage gain from the input to v~ is v~~~ . v,n~~ G.R, = EL R,. (28)

44 = an-

%rfO = dB IP21

2C, tan- (2rf0 .,)(2RCIC,) = tan- ~. (;2)

c1

The CM rejection ratio (CMRR) gains [5]

is the ratio of the two

The phase margin of the DM open-loop response is then & = 90 A~. (23) Therefore, CMRR = a:

1 = Rc,G;

(29)

The necessary value of Cl to produce the excess phase is C, = DC Power Dvain To model the actual dc power dissipation of an op amp, a resistor RP is introduced into the macromodel. For the circuit of Fig. 1, in a quiescent state, the power dissipation is P, = Vcc21c1 + VEJE, +
(Vcc + v..)

$ tan A+.

(24)

. = (CM;R)R.,

(30)

The dominant behavior of the CM frequency response will be approximately the same as the DM frequency response except that the presence of the capacitor Cm in the input stage introduces a transmission zero in the CM gain function at l/RBCB. The Output Stage: R~l, RU,, and Gb

R,

(25)

The necessary value of RP to produce this dissipation is R= = (v,, + VEE) Vcc21c1 VE.IEE (26)

The output stage provides the desired dc and ac output resistances and the output current and voltage limitations. From Fig. 1, it is seen that the output resistance at very low frequencies for the quiescent state is R 0
t =

P.

R,, + R,,.

(31)

In a typical op amp, most of the current drain from the voltage supplies is due to diode-resistor current defining paths. Therefore, as the supply voltages are

At high frequencies, RO, is shorted out by the (current) Miller-effect output capacitance across it due to Cz. The effective shunt capacitance is C,fi e CZ( 1 + R2 Gb). For

358

IEEE JOURNALOF SOLID-STATE CIRCUITS, DECEMBER1974

the situation where a large load resistance is presented to the macromodel, the corner frequency of the output impedance is (32) For frequencies well above this value, the output resistance is RO1. Therefore, R,, = R, . . . . (33)

v~
R02
+
avdvin

ROI DI ~IX
+ V. . .

lL~

+
v~

-m- .

Fig. 3. Simplified circuit diagram of the output stage

With this value established, Roz from (31) and G~ from (13) are R,, = Ro., R,, and aV~RC1 = Z,E, (35) (34)

to I~Rol. The approximate from I. = I..,

limiting condition is found

exp 9
T

(38)

The limiting value of lx is determined by an overdrive condition at the input. The short-circuit available current from Gbvb is I~~x Imax = Ix + Iscs = 21c,R,G,,. A typical value of &.X is 100 A. From the equation above, I I .SD1 Ix ,SD2 (39)

The Output Stage: Current Limiting In the output stage of Fig. 1, the desired output-current limiting is provided by the elements GcV6, Rc~ Dl, D2, and Rol. The Rc, GCV6 combination is an equivalent to a voltage-controlled voltage source (which is not available in simulators such as program SPICE). Thus, V,..t = V6 also appears across Rc. If both of the voltageclamp diodes D3 and D4 are off, the maximum current to the output is the ratio of the potential across Dl, D2, and RO1 (36)

@d-R*)
of Rol, the value may lead to numerical

40)
diffi-

For large required values

be extremely small which

of ~fl~l can

culty. In many applications when the output resistance is not critical, a smaller value of Rol can be used neglect-

ing the exact realization of Ro~c, e.g., if lsD1 = ~~1, R,,

C-S

~v~~. in Sc 81

(41)

V. = V, In $: Ix 18~, Maximum current through D, or D,. Saturation current of diodes D,, D,.

(37)

Roz is then increased to Rout ROI, and G~ is decreased to maintain the same value of the G~ Roz product. In order to approximate well a voltage-controlled voltage source, Rc must be very small. If the voltage drop across Rc is to be only 1 percent of VD1 or VD!2, R.=& In ~IK. (42) current

Since Rol is known, 1~~1 can be established once Ix is determined. In Fig. 3, a reduced portion of the output stage is shown which applies for a positive output excursion, and where a very small load resistance is assumed. A Th6venin equivalent for G~v~ and R02 is used. The Th6venin op-en-circuit available voltage is ar~vi.. An ideal voltage-controlled voltage source V. is also used in place of GCV6 and Rc. Assume first that the voltage avDv,i. is not large. The output current flowing through the resistor Rol then produces only a small voltage drop. The polarity of the voltage v. is such as to forward bias diode D,. If the voltage drop across Ro, is small, the current through D1 is very small and can be neglected. As av~vi, increases, so does IL and the voltage drop across Rol. As the latter approaches the (ON voltage of Dl, i.e., the voltage for appreciable current through the diode, the increasing current from the source IDI flows through the diode. IL is then approximately limited because of the exponential increase of 1~1 with respect

100IX

SDl

The necessary value for the voltage-controlled source GCV6 is

(43) The Output Stage: Voltage Limiting The output voltage excursion is limited by the voltage source-diode clamp combinations Vcj D3 and VE, D 1, shown in Fig. 1. With a large, positive output voltage such as to forward bias D3

v+ ut = Vcc Vc + VD3 O
=VccVc+V.ln~-

l..+

(44)

As indicated above, the diode current is limited to the

BOYLE t U1. 43 :MACROMODELINGOF OPERATIONAL AMPLIFIERS TABLE II CIRCUITDATA .4NDGUMMEL-POON TRANSISTOR PARAMETERSFOR THE ICL8741 OP AMP
-. CLrCUit E1.mmt ,? ~ R2 R3 Fib zz Q7 ~: RIO Rli Nodes 02 Ez 02 02 04 12 12 32 02 Zk 02 15 10 10 14 15 14 15 01 10 09 09 05 _D4 20 19 ___Ol 20 of .19 20 20 22 15 02 02 22 17 16 18 08 05 26 25 2s 21 27 22 19 07 06 09 09 16 16 14 10 Data value 1.0< 50. l.o 3.0 39. 77. 22. 100. 50. 40. 50. 30. 13 11 13 ii 17 18 16 Oi .mMODEL_13NPi_ + + + .MO13EL + + + Guom.1-Poon NGP_ RC=300. CJE. O.55P CZ= 1653._ Transistor ?ar.metms 8QM=2. 5__ TF. I.ISN 1s. 1.26 E-15 o ric=3. BRM=6. I iF=O.76N__TR. IS= 0.395:-15 NE=2. O XC=3. _ ERM=3.8 TF=27.4N Is= 3.i5E-i5 NE=2,0 tlc=3. RM=8.8 TF.26.5N Is= 17.6E-15 N:=2. 14 C=4.. o -. RLI= 670.._ TX= 405. N V2=178.6 PE=c .60_ Ril= 185.

359

{ K____+. K K

MS=3. SNP2 NGP _.RC= 15. CJE=2.80P C2= 1543. .ME=3. PGP

0FII=209. _ CC7=1.417P CJC=O. S6P _NE.2. IK=l.611M PC. O.45 13 FM=400. CC S.3.455P_. CJC=l.55P IK=lO. OOH

243. N_ IVA.267. O PE=o .60

.c.
&l :$ Q4 .:;

K ..+ - K .!400EL K + P__+__ DNPI + ONP1 oPNl__:M00EL_BPN2_ 8PNi + 6NP1 + P.NP1 _ 13NP1 QPPJ1 + BPN1_.+ BNP1 ENPi OPNi aPN 3-+ BPN4 3N?2__ BNP1 r3NPi L3!l Pi. _.+. 3!4?1 BNPi BPN2 __+__ BPN1 BxPi BP)/5_ OFN6 BNP1 + + +___ + .I{ODFL .MOOEL + +

Pc=o. k5 QFM= 75. 8PN1 CC S=2.259P RC=150. _cJE. o.io P___cJc=i.05P___ IK=270. ou C2= 1764. ME=3. PC= C.45 P GP..._ - BFM=117. _--_--B Rc=i56. CJE=4.05P . CZ= 478.4 ME=4 . . . ... PGP RC= 80. CJE=O.lOP __._ C2=84.37K t+E=3, PGP_ RC=120. CJE=O. IOP cz. ?4.37K_ CJC. . IK=590.7u .PC=O.60 Z. 80P

Ru= 500. TR=2540. N vA.55. il_ ?E=O.45 RB= ..80. _ N

TR=2430. Vfi=57.94 .. PE=o.60

__::___

10 01
05 05 04 04 04 20 26 15 21 27 20 24 25 22 i9 i9 22 08 02 01 0: 01 26 12 21 23 24 27 25 12 02 24 15 C2

. .._. BPN3

010
oil _Q12 0i3A Q13B _fli4 Q15 Qlb _G:7_ 018 219 _ Q20__.02 a2i QZ2 _.-oz3A_., ciz3a Q24

BFH=i3.8 CC S=2.126P CJC=O.30P__ IK.5. ooi3N PC= O.45 aFM=i4.8 CCS=Z.126P CJC=0,90P IK=ii:.8U _ PC. O.45 !3Fli= 80. _.__. _TF=26.5N CJC=2.40P IK=$o.55u PC= D.60. BFII= 19. cJC=2.40P IK=80.55U pG. o.60 _

13 RM=1.4 TF. z7.4N IS= 2.25E-15 N[=z. o !ic=3. BRM=l.5_. TF.27.4N Is= 2.25E-15 !! E=2. O___ NC=3. OR M=I.5 _ IS= 0.79E-i5 hE. z.o MC=+. C!w. i.fl T<r=2G.5N Is=0,0063E-15 NS=Z. UC=+. O

RB=1OO. T?= 55. N ~vA=s 3.55_ PE=O .95 RD=i60. _ TR= 220. N VA=83 .55 Pi. C.i5 _

+ .HOQEL__BPN4_ + +

tlc=3.
BPN5 -.. PGP RC=170. CJE=i.10P Cz= 12!9. ME=4 . BPN6 PGP lNc=ioo, cJE. i.90P. C2=5?. I+9K Mg.4 . _

!2.0=1100. TR=9550.N
VA=79.45 P:= C.6P -, RU= 6SC. Tfl=2i20. M J A=i67 -l_ PE=o.60

___

.MOOEL
[: + +

short current I,yo+.The necessary bias voltage is V, in ~;. Similarly, (45)

TABLE III OP AMPPERFORMANCE CHtiR.kCT~RISTICS 8741 Device-Level Model LM741 Data Sheet 30 0,67 0.62 80 20 1 2.10
103

SD3

8741 Macromodel

LM118 Data Sheet 5 100 71 120 6 2

2,. ]05

v. = v.. + v.,- +
The Complete Model

v T

In I&~ ISD4

(46)

C, (pF)
SE+ (v/ps) SR- (v//.Ls)

A summary of the design equations for the parameters of the macromodel is given in Table I. An example of the use of these equations is given in the Appendix. The :starting point is op amp performance data. The particular IC used to illustrate the design procedure was the object of an earlier study [6]. The configuration of this IC was established to be that of Fig. 2 and the transistors were characterized by the GumnlelPeon (G-P) parameters of Table 11.1 Program SPICEhas been used to establish the perfornlance and characteristics of the op amp [7]. The results are summarized in Table III, column 1. These values are used in the Appendix to develop the element and parameter values of the macromodel. As brought out in the Appendix, several parameters of the macromodel could be chosen arbitrarily:
1 A slight modification of the GP parameters of the output transistorshas been made to produce a typical level of maximum short-circuit available current.

Ifl (nA) In.. (nA) V., (mV)

CtiRR

(dB)

R.., (Q) R.-.c (Q) Isc+ (mA) Z, SC-(mA) v+ (v) v- (vj

Pd (mW)

30 30 0.899 0.9 0.718 0.72 255 256 0.7 <1 0.298 0.29!? 4.16.10 4.17.10 1.219.103 1.217.10 16.3 16.8 106 106 566 566 76. S 76.8 26.2 25.9 26.2 25.9 14.2 14.2 12.7 12.7 59.4 59.4

20 90 75 25 25 14.0 13.5

16.10$ 40 100 75 25 25 13 13

T = 300 K(V, Is, =

Ism =

= 25.85 mV), 8.10- A,

R, = 0.1 MQ, where 1s1, 1s~3 are the saturation currents of the first transistor and the voltage-limiter cliodes, respectively. In addition, the major compensation capacitQr is fixed

360 TABLE IV PARAMIJTICRS MACROMODEL 8741

T

IEEE

JOURNALOF SOLID-STATE CIRCUITS, DECEMBER1974

LM 741

LM 118

Is,

300 300 300 8.10-16 8.10-16 ~ .10-16 8.10-16 8.10-16 8.10-16 I~D, R, 100 100 100 ~ 30 C, 30 2.042 2.41 C~ 7.5 2.033.103 111.67 52.6726 & 2.137.103 52.7962 143.57 P2 I~E (PA) 27.512 20.26 500 R~ (m~) 0.40 7.2696 9.872 1,$, (A) 8.309.10-1$ 8.619.10-8 8.0925 .10-6 4352 1989 R., (Q) 5305 R., (o) 2391.9 2712 1884 4.5288 2.098 6, (pF) 5.460 1,5.363 ~ (kQ) .502.765 U (pmho) 229.774 188.6 Gc~ (nmho) 5.028 1.1516 6.28 32.13 R,, (n) 76.8 32.13 Ro, (Q) 489.2 42.87 42.87 G* (mho) 37.0978 247.49 92.792 Ix (A) 100.138 8.10-16 ~ .10-16 1~~, (A) 3.8218.10-3 Rc (Q) 0.00279 ~10-3 0.1986 .10-3 0.02129 .10-3 Gc (mho) 5034.3 46964 358000 2.803 Vc (v) 1.6042 1.803 2.803 VE (v) 3.1042 2.303 (A) (A) (ka) (pF) (pF)

(K)

o .

device-level macro model

model

-5{l

10

20

30

40

t Ipsec )

Fig. 4. Simulated voltage follower slew rate performance using both device-level models and macromodels.

by the type of op amp under study or is chosen appropriately. For the case at hand, Cz = 30 pF. The remaining values of the parameters of the macromodel are presented in Table IV, column 1. IV. COMPARISON WITH DEVICE-I,EVEL iklODELS Basic Macro model Perf ormtance

To provide a further comparison, the large-signal, slew rate performance for a voltage follower is shown Fig. 4 for both the device-level model and the macrornodel. It
is seen that the responses are very similar. The presence of C@ produces a step in the initial response of the voltage follower. From simple theory [4], the jump should be approximately

The values for the macromodel of Table IV, column 1 were used to define an external model in program SPICE. The same set of computer runs was made as lead to the op amp performance results of Table III, column 1. The For this example, results for the macromodel are presented in column 2 of this table. It is seen that the comparison is excellent for AVin = 10V both small-signal and large-signal experiments.

and

AVOU,= ~

(10) = 2.5V.

BOYLEetal.: MACROMODELING oPERATIONAL OF AmplifierS 20k

15 [ loVou!

361

.:*W.
Fig. 5. A monostable time delay circuit.

),

(v)
5(h

o-

,,

-5-

From Fig. 4, the observed jump for the macromodel is 3.6 and 3.4 V for the device-level model. A measure of the complexity of the two op amp models can be obtained by comparing the node and branch counts of each circuit. For the device-level model, where each GP transistor model has 2 internal nodes and 7 branches, the totals are 81 nodes including the datum node, and 193 branches. For the macromodel, where each E-M transistor model has no internal nodes and 4 branches, the totals are 16 nodes and 28 branches. The ratios for the two models are 5.1 for the nodes and 6.9 for the branches. The number of p-n junctions in the device-level model is 52 and 8 in the macromodel, a ratio of 6.5. The total computer central processing unit (CPU) time on a CDC 6400 to simulate the voltage follower slew rate performance is 39.2 s for the device-level model and 4.0 s for the macromodel, a ratio of 9.8. An alternate comparison is obtained if only the simulation times for the initial state and the transient analyses are used. The improvement ratio is then 12.0. For the dc and ac simulations, the device-level model to macromodel CPU times, for the analyses only, have the ratios of 3.9 and 6.0, respectively. Note that the improvement ratio is less for the dc analyses. A R egenerative Timer The monostable time delay circuit of Fig. 5 provides a good test of the ability of the macromodel to perform as desired when demanding nonlinear performance is required. The voltage and timing levels of the circuit of Fig, 5 have been chosen to provide a maximum stress on
the op amps with respect to voltage limits, critical voltage switching levels and speed of response, slew-rate limitations, etc. The output waveforms of the circuit as predicted by program SPICE using both the device-level model and the macromodel are shown in Fig. 6. It is seen that the responses compare closely. The leading and trailing edges of the output pulse differ in timing by less than 1 time step of the computer output, i.e., better than 3 percent of the overall pulsewidth. The total CPU times for the simulations using the two models are in the ratio of 8.9. If the common output time is deleted, the improvement ratio is 9.6.

k -lo .
o
device-level

<1$
model h.

mocro model

-15+ o

I 20

I 40 t ( ,usec)

[ 60

Fig. 6. Simulated output pulse response of time delay circuit using both device-level models and macromodels.

100k 399k

100k

10k

10k

10k

v:

Fig, 7, Ring of Three bandpass filter.

TABLE V
l?.ESPONSE DATA
FOR THE

,[RING OF THREE BANDPASS FILTI;R

Design Actual Center Center Frequency Frequency f.a (kHz) f., (kHz) 1 2 10 0.998 (O.998) 1.996 (1.996) 9.934 (9.934)

Gain Magnitude ~R 11.01 (11 .00) 12.24 (12.23) 112.1 (107.1)

Gain Magnitude at
o.~f.d

Gain Magnitude at

l.lf,a
4.311 (4.311) 4.368 (4. 367) 4.398 (4,401)

4.806 (4.806) 4.898 (4. 896) 5,547 (5.542)

Numbers inparentheses refer o results t withdevice-level model.

An Active RC Filter To further check the second-order ac response of the macromodel, the simple Ring of Three op amp filter of Fig. 7 was designed for a center frequency of 1 kHz and a ~ of 10. The frequency response from program
SPICE for the two models is summarized in Table V. Again, it is seen that the comparison is very close.

362

IEEE JOURNALOF SOLID-ST.4TE CIRCUITS,DECEMBER1974

At higher frequencies, the phase response of the (1 lllHz) 741-type op amps comes into effect. A response comparison for the two models as shown in rows 2 and 3 indicates that the macromodel is providing the proper phase response.
The total
state

expressions of Table I. The final results arc presented in column 1, Table IV. From the slew rate performance of the 8741 as given in Table III

CPU

simulation

times to determine

the dc

s,+ =

0.90 V/ps

and

SIZ- = 0.72 V/ps. capacitor of Cz = 30 pF,

and the frequency response using the two models have the ratio of 5.8. If the common output time is omitted, the ratio becomes 6.8. In this application, the nonlinear performance of the op amp is not of major interest. In order to check on the improvement of computer run time for a reduced macromodel, the voltage and current limiting circuitry of Fig. 1 was omitted. The simulated response of the filter did not change, of course; however, the total CPU
by a factor of 1.4. IC OP AMPS

For the given compensation these values lead to

ICI = ;SE+C, = 13.50 PA C, = ~? .. C, = 7..5OPF.

The average base current is 256 nA and the desired base current offset is 0.7 nA.
I,, = 256.3 nA,

run time was reduced l.MACROMODICL

IB, = 255.7 nA
/32= 52.7962.

PARAMETERS

FOR OTHER

/3,= 52.6727,

The detailed, precise performance characteristics for an individual op amp as obtained from the use of the device-level models are usually n@ available. The precision used in the numerical example of this paper is employed in order to obtain an accurate estimate of the performance of a macromoclel in relation to a known reference. Experimental results with actual op amps could inclucle significant measurement inaccuracies, Typically, one has a data sheet or averagecl experimental data for a type of op amp which is to be included in a system. As an example of the choice of macromodel parameters in this situation, two further examples are given. In Table III, columns 3 and 4, measured typical op amp data are given for both the LM741 and the LMl 18. The macromodel parameters corresponding to these data are given in columns 2 and 3 of Table IV. It is possible to introduce programming into a simulator to determine automatically the macromodel parameters. This has been done at one location for program SPICE. In this situation, all that is necessary to define a specific op amp model is to list its characteristics on an op amp model card) in much the same way that one ~urrently defines a transistor model by specifying its characteristics on a transistor model card. When an op amp characteristic is not inputed, a default value is used.
APPENDIX THE 8741 MACROMODEL

A high level of precision is used in this example in order to obtain an accurate comparison of macromoclel performance in relation to that of the op amp modeled at the device level. The necessary emitter current source for the input stage is ~~fl = 27.512 PA. The value of the CM emitter resistor is R, = 200/IBB = 7.2696 Ma

where a value of VA = 200 V has been used. For ~1, the assumed value of saturation current is
810-6A which is a typicalvalue for a small n-p-n IC transistor.o proclucethe desiredinput offset T voltag,e of 0.299 mV

IS2 80-1(1=802510-16A = +0)

For a fully compensated op amp with a rolloff of 6 dB/octave, the O dB frequency can be calculated from the product of the gain and the value of the frequency at which it is measured providing that the frequency is well above the corner frequency of the gain characteristic. From the data of column 1, Table III, f,
dB =

(1.219 103)(103) Hz = 1.219.106 MHz.

The value of the collector resistors of the first stage is R., = 1- = 4352 Q.

2~f0

dBc2

The value of the reciprocalof g.,for the first stage is

In this Appendix, a numerical example is used to illustrate the development of the parameters of the op amp macrolnodel. For the example, the response characteristics of the 8741 op amp are used as determined by several simulator runs using device-level modeling. The circuit of Fig. 2 together with the transistor parameters of Table II has been analyzed to obtain the characteristics whicb are summarized in column 1, Table III. The development procedure follows the sequence of

1 = 1915 Q. 9m1 The required value of the emitter resistor is R., = 0.9814(4352 1915) = 2392 Q. The final element for the input stage is (71, which produces the nondominant pole of the gain function. For A+ = 16,80

BOYLEet

d.: MACRO MODELING OPERATIONAL OF AMPLIFIERS

the support given for the numerous C, = ~ tan 16,80 = 4.529 pF, sary for this project. REFERENCES computer

363 runs neces-

The value of the resistor RP to simulate power dissipation for *15 V supplies and a dissipation of 59.4 mW is R. = 15,363 kQ, For the interstage, Rz is taken to be 100 k~ and
~a = #-

= 229.774

/Jld10 .

For a CMRR
G

of 106 ~~ (199.5 10S)

G.

CM = CIV!RR

= 1.1516 nmho.

In the output stage, the desired dc and ac output resistances are 566 ~ and 76.8 0, respectively. Therefore, Ro, = 76.8 Q, ROZ= 489.2 Q. The value of Go to provide the correct DM voltage gain of 417. 10s is aV~R.l b = KR;; = 37 097 The maximum current through the diode DI or Dz is Ix = 21ClGbR, I.c = 100.14A

[11 J. R. Greenbaum, [Di~ital-IC models for comnuter-aided design, Electronics, vol~ 46, 25, pp. 121-125, Dec.6, 1973. [21 B. M. Cohn, D. O. Pederson, and J. E, Solomon, Macromodeling of operational amplifiers, in ISSCC Dig, Tech. Fapem, Feb. 1974,pp. 42-43. [31 D. 0. Pederson and J. E, Solomon, The need and use of macromodels in 1(3 subsystem design, in F%oc. 1974 IEEE Sqmp. Circuits and Systems, p, 488. [41 J. E. Solomon, The monolithic op amp: a tutorial study, IEEE J. Solid-state Circuits, this issue, pp. .314-332. [51 P. R. Gray and R, G. Meyer, Recent advances in monolithic operational amplifier design, IEEE Trans. Circuits anti S~st., vol. CAS-21, pp. 317-327, May 1974, [61 B. A. Woolcy, S.-Y. J. Wong, and D. O. Pederson, A computer-aided evaluation of the 741 amplifier, IEEE J. SolicZState Circuits, vol. SC-6, pp. 357-366, Dec. 1971. [71 I,YW. Nagel and D. O. Pedcrson, Simulation program with integrated circuit emphasis (SPICE) , 131cctron. Res. Lab.,
Univ. of California, Berkeley, Memo ERL-M382, and in

Proc. 16th Midwest &mp. Circuit Theory, 1973. [81 D. N. Pocock and M. G. Krebs, {Terminal modeling and photocornpensation of complex microcircuits, IEEE Trans. Nucl. Sci., vol. NS-19, pp. 86-93, Dec. 1972. and F. N. Trofimenkoff, Modeling o~era[91 D. H. Tleleaven tional amplifiers for computer-aided circuit analysis? IEEE Trans. Circuit Theor~ (Corrcsp.), vol. CT-18, pp. 205-207, Jan. 1971.

where the desired value of I~c is 25.9 mA. With these values, the saturation currents of DI and D2 are I SD = I

Ix

exp ~~z

= 3.822.10$2 A. volt-

The values for the approximate voltage-controlled age source are

Graeme R. Boyle was born in Echuca, Victoria, Australia, on October 26, 1949. He received the B.E, and M.Eng.Sc. degrees in electrical engineering from the University of Melbourne, Melbourne, Australia, in 1972 and 1974, respectively. He is currently at the University of California, Berkeley, working toward the Ph.D. degree in the field of modeling and computer simulation of integrated circuits.

lorthe voltage-clamp circuits, the saturation currents of diodes D3 and D4 are chosen to be 8.10-16 A. The voltage sources should be

Vc = 15 14.2 + 0.02585 in ~$~~% and V.

= 1.604 V

= 15 12.7 + 0.804 = 3.104 V. AGIciNOWT~E~~~~~~

The authors are pleased to acknowledge the aid and discussion on this topic with C. Battj es, R. Bohlman, S. Taylor, R. Dutton, and I. Getreu. The staffs at the Computer Centers at the University of Californiaj Berkeley, and at Tektronix, Inc., Beaverton, Oreg., have been extremely generous and helpful in

Barry M. Cohn (S68) was born in Seattle, Wash., on April 8, 1949. He received the B.S.E.E. degree, graduating Magna Cum Laude and with College Honors, from the University of Washington, Seattle, in 1971. He received the M.S. degree in electrical engineering from the California Institute of Technology, Pasadena, in 1972. He has done power engineering for Seattle City Light during the summers of 19681970.From 1972-1974, while at the University of California, Berkeley, he did research and published on the topic of macromodelirrg integrated circuits for computeraided design. During the summer of 1973, he was employed as an Engineer with National Semiconductor Corporation, where he did research on the topic of macromodeling operational amplifiers. From 1973-1974 he has been a Research Assistant at the Electronic Research Lab and a Teaching Assistant at the University of California, Berkeley, from which he is currently on
leave and presently employed by Intel Corporation, Santa Clara, Calif., where he directs CAD operations. Mr. Cohn is a member of Tau Beta Pi and Phi Eta Sigma. He is the recipient of a National Science Foundation Trainceship, a General Telephone Electronics Graduate Fellowship, and numerous undergraduate scholarships.

364
(S49-A51-M56-F64) was born in Hallock, Minn., on September 30, 1925. He received the B.S. degree from North Dakota Agricultural College (now North Dakota State University), Fargo, in 1948 and the M .S. and Ph.D. degrees from Stanford University, Stanford, Calif., in 1949 and 1951, respectively. From 1951 to 1953 he was a Research Associate in the Electronics Research Laboratory, Stanford University. From 1953 to 1955 he worked at Bell Telephone Laboratories, Inc., Murrzy Hill, NJ., and was also a Lecturer at Newark College of Engineering, Newark, N.J. In 1955he joined the Electrical Engineering Department, University of California, Berkeley, where is is now a Professor and engaged in research in integrated circuits and com-

IEEE

JOURNALOF SOLID-STATE CIRCUITS, SC-9, O.6,DECEMBER1974 ~OL. N

Donald O. Pederson

puter-aided circuit analysis and design. From 1960 to 1964 he was Director of the Electronics Research Laboratory. Dr. Pederson is a member of Sigma Xi and Eta Kappa Nu. He and three coauthors were awarded a Best Paper Award for a paper presented at the 1963 International Solid-State Circuits Conference. He was a Guggenheim Fellow in 1964 and was the recipient of the IEEE Education Medal in 1969. In 1974 he was elected to the National Academy of Engineering.

James

E. Solomon (S57M61), please see p. 332 of this issue.

for a. photograph and biography,

A High-Performance Monolithic Multiplier Using Active Feedback

BARRIE GILBERT, SENIORMEMBER, EEE I

Absfrac fSince its conception in 1967, the linearized transconductance multiplier (LTM) has rapidly gained acceptance as the preferred approachto the realization of monolithic analog multipliers, and its simplicity has commended it for use in low-cost modular designs. Accuracies of these units have been limited to about 0.5 to to 2 percent, and drift and noise performance have generally been worse than that possible using the dominant alternative technique of pulse-width-height modulation, This paper shows that when careful attention is given to all the sources of error it is possible to attain a five-fold improvement in accuracy and corresponding reductions in the drift and noise levels. Odd-order nonlinearities can be reduced to negligible magnitudes by the use of active feedback, by substituting the usual resistive-bridge feedback path by an amplifier identical to that used as the input stages.

&
11 12

1,

14

I,

l+%
1,
1,

14

(a)

J,J4 =+J3

(b)

J1~= J3J4

I. INTRODUCTION HE LINEARIZED transconductance multiplier (LTM) technique is now widely used in one or T another of its several forms, the commonest of which are shown in Fig. 1. Using ideal transistors these circuits are fundamentally exact and insensitive to isothermal variations of temperature. Compared to alternative multiplication techniques, the LTM core is extremely simple and has intrinsically wide bandwidth. It is the basis of many other (functional circuits, such

+X)W w-x
(c)

(d)

Fig. 1. Basic LTM configurations. (a) Normal form. (b) Tnverted form. (c) Specific version of the normal form having low betasensitivity. (d) Common inverted form, which is convenient but has high beta-sensitivity.

Manuscript received May 25, 1974; revised August 11, 1974. This paper was presented at the International Solid-State Circuits Conference, Philadelphia., Pa., February, 1974. The author is with Analog Devices Semiconductor, Wilmington, Mass. 01887. 1 B. Gilbert,, A new wide-band amplifier technique, IEEE So.M-Stute Circuits, vol. SC-3, pp. 353-365, Dec. 1968. J.

as precise two-quadrant dividers, rms converters, vector sum modules, etc. This paper describes a four-quadrant multiplier designed to make full use of the potential accuracy afforded by this technique using currently available monolithic processes. The basic error sources are reviewed, and methods presented to minimize their effects. A significant improvement has resulted from the use of an active feedback scheme which largely eliminates the nonlinearities introduced by the input amplifiers. Apart from this, the resulting design is similar to most transconductance