synchronous Counter

In synchronous counters we have the same clock signal to all the flip-flops. MOD-4 Synchronous counter: We discuss here a 2-bit synchronous counter. We have the circuit for this as:s

We have the initial outputs as Q0=0 & Q1=0. Whenever the first negative clock edge comes O/P of 1st FF becomes 1 as we have J & K for 1st FF as 1 and hence output of 1st FF toggles and changes from 0 to 1. But when 1st cock edge had come output of 1st FF was 0. Hence J & K for 2nd FF for 1st edge are 0. So output of this FF doesnt change and we get Q1=0. so the output is (Q1Q0)2= 012. On the next edge, output of 1st FF changes from 1 to 0 as J & K are always 1 for this FF. Inputs for 2nd edge for 2nd FF are J=1 & K=1. Hence output changes from 0 to 1. so we get the count as (Q1Q0)2= 102. Similarly on the next edge well get the output count as (Q1Q0)2= 112. And on the 4th clock edge both the outputs get reset and we get the output as (Q1Q0)2= 002 and again whole procedure is repeated.

Synchronous Counters
Synchronous digital counters have a common clock which results in all the flip-flops being triggered simultaneously. Consequently, there are no cumulative delays that result because the clock signal must ripple through the stages as in the asynchronous counters. Synchronous counters can be designed to count up and down in

numerical order. In addition, they may be used to produce count sequences of non-consecutive numbers. The count sequence produced by synchronous counters is not dependent on the trigger characteristics of the flip-flops that comprise the count stages. The count sequence is achieved by applying the required logic function into the flip-flops.

Synchronous Counter Analysis To define the counter operation of synchronous counters we may employ a procedure similar to that used in the analysis of asynchronous counters. In particular, the following steps are used to analyse synchronous counters.

1. Verify that the counter is indeed synchronous (i.e. identify the common clock feature). 2. Determine the number of stages by counting the number of flip-flops or outputs. 3. Determine the type of flip-flops and the input function for each stage. For reference, recall the characteristic table which indicates the present state (Qt), the present inputs and the next state (Qt+1) for each flip flop. 4. Construct a characteristic table for the complete counter circuit. 5. Analyse the counter using the characteristic table to determine the complete counter sequence. This analysis concludes when the count sequence begins to repeat. 6. Determine the modulus of the counter. 7. Construct a state transition diagram to describe the counter operation. 8. Graph the output waveforms produced by the counter.

Let us now analyse the counter circuit shown in Figure 3-18.

Figure 3-18 A two-bit synchronous counter

The circuit is synchronous as the flip-flops are all tied to a common clocks The counter has two stages T flip-flops are used in the design of the counter

J-K Flip-Flop Characteristic Table Present Inputs J 0 0 0 0 K 0 0 1 1 Present State Qt 0 1 0 1 Next State Qt+1 0 1 0 0

1 1 1 1

0 0 1 1

0 1 0 1

1 1 1 0

Using the flip-flip characteristic table we may now develop the counter characteristic table. Let Ji and Kirepresent the inputs to the (I+1) th stage flip-flop, where i=0, 1 in this case.

Counter Characteristic Table Present State Q1 Q0 0 0 1 1 0 1 0 1 0 1 0 1 Present Inputs J1 K1 J0 K0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 1 0 Next State Q1 Q0 1 0 1 0

J0=K0=1 J1=K1=Q0

From the analysis of the counter next state table we conclude that it is a MOD-4 binary up counter. The state diagram is as illustrated in Figure 3-19 and the corresponding waveform diagram is chow in Figure 3-20.

Figure 3-19 State transition diagram

Figure 3-20 Waveform Diagram for counter in Figure 3-18

Synchronous counter design

To successfully design synchronous counters we may employ the following six basic steps:

1. Create the state transition diagram. 2. Create a present state-next state table (often referred to as the next state table). 3. Expand the table to form the transition table for each flip-flop in the circuit. The transition table shows the flip-flop inputs required to make the counter go from present state to the desired next state. This is also referred to as the excitation table. 4. Determine the logic functions of the J and K inputs as a function of the present states. 5. Analyse the counter to verify the design. 6. Construct and test the counter.

Let us employ these techniques to design a MOD-8 counter to count in the following sequence: 0, 1, 2, 3, 4, 5, 6, 7. Step1: Creating state transition diagram.

Step 2: Creating present state-next state table

Present State Q2 0 0 0 0 1 1 1 Q1 0 0 1 1 0 0 1 Q0 0 1 0 1 0 1 0 Q2 0 0 0 1 1 1 1 Next State Q1 0 1 1 0 0 1 1 Q0 1 0 1 0 1 0 1

Step 3: Expand the present state-next state table to form the transition table.

Present State Q2 0 0 0 0 1 1 1 1 Q1 0 0 1 1 0 0 1 1 Q0 0 1 0 1 0 1 0 1

Next State Q2 0 0 0 1 1 1 1 0 Q1 0 1 1 0 0 1 1 0 Q0 1 0 1 0 1 0 1 0

Present inputs J2K2 0X 0X 0X 1X X0 X0 X0 X1 J1K1 0X 1X X0 X1 0X 1X X0 X1 J0K0 1X X1 1X X1 1X X1 1X X1

X indicates a "dont care" condition.

Step 4: Use Karnaugh maps to identify the present state logic functions for each of the inputs.

E.g. for J2 we get:

J2 = Q1Q0 Using similar techniques for the other inputs we get: K2= Q1Q0 J1= Q0 K1= Q0 J0=1 K0=1

Step 5: Trace through indicates circuit should work correctly. Step 6: Constructing Circuit

Figure 3-21 A three-bit synchronous counter Like asynchronous counters, synchronous counters may be designed to meet a variety of specifications. For example, decade counters that count the binary sequence 0-9. In addition, we may implement bidirectional counters (i.e. they have the ability to count in ascending [0,1,2,3,4,5,6,7,8] and descending [8,7,6,5,4,3,2,1,0] order). In general, most bidirectional counters can be reversed at any point in their sequences e.g. 0,1,2,3,4,3,2,1,0,1,2,3,4. In this case there is an additional input which determines whether you want to count UP or DOWN.

COMPARISON B/W SYNCHRONOUS & ASYNCHRONOUS COUNTERS

Asynchronous Circuit The logic circuit of this type of counters is simple to design and we feed output of one FF to clock of next FF Propagation time delay of this type of counter is : Propagation Time Tpd = N * (Delay of 1 FF) which is quiet high N is number of FFs Maximum operating frequency And hence operating frequency is Low

Synchronous The circuit diagram for type of counter becomes difficult as number of states increase in the counter Propagation time delay of this type of counter is: Tpd = (Delay of 1 FF) + delay of 1 gate Inclusion of delay of 1 gate would be illustrated when we design higher counters: And hence operating frequency is Higher

CLOCK SKEW

It is a phenomenon in which there is a difference between the times at which clock signal reaches different components in synchronous circuits. Or we can say that clock signal from clock circuitry reaches different components in the circuit at different times. e.g. If in the circuit given below, CLK signal reaches the two flip-flops at different times then it is said that CLOCK SKEW exists in the system.

CAUSES: There are basically 2 reasons due to which clock skew exists in the system:

1. Distance: If there is a difference in the distances between the clock circuitry and different components then clock signal has to travel through different length of wires, hence clock signal would reach earlier where there is shorter distance and clock would reach later where there is longer distance. 2. Change in the material of wires: Also if there is a change in the material of wires then clock signal can travel faster in one wire and slower in other and hence there would be change at the time at which clock signal reaches different components.
Effects of clock skew:

Disadvantage: If combinational logic delay is very short or clock skew is large enough then output of 1st FF would change (hence input of 2nd FF is changed overriding the previous input) before HOLD time condition for the input of 2nd FF is satisfied and hence circuit would not work properly due to this HOLD TIME violation. Or input of 2nd FF change to create SETUP time violations. Advantage: We can see in the example given below that due to clock skew, minimum clock period of the clock is decreased (and hence frequency is increased).