A 0.25 m CMOS Fully Integrated IF-Baseband-Strip for a Single Superheterodyne GSM Receiver.

Paolo Orsatti, Francesco Piazza and Qiuting Huang Integrated Systems Laboratory, ETH Zurich, Switzerland Abstract: An IF-strip for a one chip single superheterodyne GSM receiver
has been implemented in a 0.25 m CMOS technology. The strip contains a ,20::60dB 71MHz IF-ampli er, a quadrature demodulator and low-pass output lters. Measurements show an overall voltage gain of 89dB and a noise gure of 3.8dB. Phase and amplitude mismatches of the I,Q demodulator are well below 1 degree or 0.1dB respectively. The system consumes 5.5mA from a 2.5 V power supply.

1 Introduction
CMOS RF-ICs at 1-2 Ghz range have made signi cant progress in recent years. Most of the research has been concentrated on highly integrated architectures such as direct conversion and broadband IF, which have proven quite suitable for less demanding applications such as wireless LAN and DECT 1, 2 . For stringent applications such as GSM, some front-end solutions have been published, but before the baseband signal processing is put together with the front-end, issues such as o set, icker noise, linearity etc, still need to be addressed before de nitive conclusions can be drawn on variants of the above architectures. In our work, we have adopted the path of rst proving the competiveness of CMOS in a well known architecture, single superheterodyne receiver in this speci c case, before attempting the more di cult task of solving architectural and circuit performance level di culties simultaneously. Within the frame of the conventional architecture, however, we strive to minimize the number of external components. The result is a highly integrated receiver by today's commercial standard, as shown by the block diagram in Fig.1. Before reporting the IF strip IC, we brie y describe the front-end circuits to set the background in overall expected performance and the expectations on the IF strip. The overall tolerable NF is 9dB at the antenna input. The duplexer typically attenuates the signal by 3 - 3.5dB, so that the remaining NF budget at the LNA input is only 5.5dB. The LNA gain is set to be 15dB, which is su ciently high to reduce the in uence of noise of the circuits after the LNA, such as mixer and IF ampli er, while not placing too high a demand on the LNA's 50 output stage in terms of compression point. The double balanced mixer's NF must be below 15dB and it must provide a further 10dB gain to scale down the noise of the IF strip. The main ampli cation of up to 60dB takes place at the 71MHz after the channel lter, and the quadrature demodulator, with internal phase shifter, converts the input into I and Q baseband signals, which are further processed by lowpass lters to remove the residual LO 1

feedthrough and sum-of-frequencies components, before leaving the RF receiver and entering the channel codec. Recently we reported the receiver front-end, which includes the critical RF blocks such as the LNA, mixer, VCO and transmitter preampli er 3, 4 . Thanks to the 0.25 m CMOS technology and optimal design, excellent performance characteristics have been achieved with current consumption competitive to existing commercial BJT solutions. The LNA's noise gure is less than 2dB, whereas that of the mixer is 12.6dB. The VCO 0.4 m CMOS has a phase noise of -113dBc at 100kHz o set. An earlier version of the IF AGC, reported in 5 , has common-source input structures with matching resistors and is measured to have 7-8dB NF. The total current consumption is less than 20mA. While the deep-submicron feature size has been essential in achieving competitive specs for a CMOS GSM front-end, its implications are mixed for the IF strip, where speed is not always the primary concern. The lower power supply of 2.5V10 is a major limitation to the number of stacked transistors that can be used and their bias overdrive. High output swing and high linearity are both more di cult to achieve. Matching considerations require non-minimum sized transistors to be used, whose higher parasitics prevent substantial saving in power consumption. This paper reports the design, implementation and characterization of the IF strip, which forms an integral part of the RF receiver in Fig.1.

2 The IF-baseband-strip

IF-AGC - Since the mixer only has a limited gain of 10dB and IF lters tend to have a sub-

stantial insertion loss e.g. 7dB, the noise contribution of the IF AGC can still be signi cant. To improve noise gure, a new input stage as shown in Fig.2 has been developed. Common-gate structure is used to provide the 330  impedance matching to the IF lter. The 3dB NF loss due to the matching resistor is therefore removed. This constant input impedance constraint imposed by lter matching forces us to abandon the previous method of programming ampli er gain by switching pairs of input transistors in and out. Instead, gain control is now achieved by switching only the needed drain current into the ampli cation path using Msw . Cascode devices M4 help keep the dominant pole frequency at a constant 150MHz. The complete 3-stage IF AGC now draws 2.5mA. Quadrature Demodulator - The output of the IF-AGC is fed to both the I and the Q path of the demodulator, one of which is shown in Fig.3. The rst stage is a double-balanced mixer to convert the desired signal to baseband while rejecting the unwanted LO feedthrough. Since signal levels can be quite high now, resistive source degeneration is used to achieve the desired linearity while allowing the gate-overdrive of the input transistors to be su ciently low for the 2.5V power supply. The desired voltage gain is achieved by a trans-impedance stage, followed by bu ers to drive the subsequent lter stage. The capacitors C1 and C2 in the trans-impedance stage create a pole at 500kHz, to further remove residual LO feedthrough. Each path of the demodulator provides 16 dB gain and consumes 290 A. Phase-shifter - To generate the needed quadrature LO signals, ESCL logic is used to divide a 142MHz into 71MHz with I and Q outputs. This approach makes the phase error from 90 degrees less dependent on process parameter variations. Although with minimum-length transistors very little current is required to toggle a 0.25 m ESCL ip- op, longer devices have been used to improve matching accuracy. The current consumption of the nal design is 80 A and the output amplitude is 200mVp. Lowpass Filter - A 4th-order Bessel lter is required here to provide additional channel ltering, remove unwanted mixer feedthrough components and provide additional gain. Switched capacitor lter is unsuitable in such an application because of aliasing and noise, whereas gm-C 2

lters are unlikely to be capable of delivering 1Vpp output from a 2.5V supply while achieving the required -45dB THD performance. An active-RC lter, shown in Fig.4, is the more natural choice for low noise and high linearity. Since the lter is low Q, Sallen-Key biquads are used to save opamps, thereby current consumption. The impedance level of the lter is a compromise between noise performance, cuto frequency accuracy and the driving capability of the class-AB bu er that is limited by current consumption and voltage supply. Due to low supply voltage the opamp reported in 6 has been adopted. The designed lter cuts o at 150kHz and consumes 640 A. Layout - The photomicrograph of the 0.25 m CMOS IF-strip is shown in Fig.5. Di erential structures, interdigitation and guard rings have been extensively used to prevent parasitic feedback through the substrate and maintain good matching of the I and Q paths.

3 Measured Performance
Measurements have been performed at 2.5V supply on unpackaged chips bonded on a small PCB, which contains all the needed external components. The maximum overall IF-strip gain is measured to be 89dB, which is very close to the nominal 92dB. The overall noise gure is 3.8 dB, which is virtually the same as that of the IF AGC alone. The IF AGC gain displays a well de ned monotonic characteristic, the measured minimum being -20.9dB and maximum being 58dB. The measured di erential errors in the 2dB gain steps are below 0.4dB except at the 0dB point, where the error is measured to be -0.7dB. Figure 6 shows the measured frequency response of the lowpass lter. The cuto frequency is 160kHz. The overall IF-strip consumes 5.5mA. The remaining critical factors determining the performance of the IF-strip, the gain matching of the I and Q paths and the accuracy of the 90 degrees phase di erence between the two, can be shown by the measurements in Fig.7. The top-half shows the demodulated sum and di erence channels. The average suppression of image channel is -43.5dB, which corresponds to less than 1 degree quadrature phase error or less than 0.1dB gain mismatch. The bottom half shows the polar plot of the I and Q signals over many cycles, which form a perfect circle as expected. Table 1 summarizes the measured IF strip characteristic.

4 Conclusions
The present IF-strip is an integral part of a 0.25 m CMOS transceiver for GSM applications. While the realization of 900 MHz RF front-end proves the feasibility and competiveness of a CMOS solution in terms performance and power consumption, the IF strip focuses on low voltage design and accuracy, as well as low power. With the power consumption of individual parts added together, the complete receiver will consume less than 25mA. This is better than most existing commercial BJT solutions. The AGC in the IF-strip is the most accurate of its kind, while an excellent image channel rejection of 43.5dB is measured on the demodulator.

References
1 2 3 4 A.Abidi et al, The Future of CMOS Wireless Tranceivers, ISSCC Digest of Technical Papers, pp. 118-119, Feb. 1997, San Francisco, USA; J.Rudell et al, A 1.9GHz Wide-band IF Double Conversion CMOS Integrated Receiver for Cordless Telephone Applications, ISSCC Digest of Tech. Papers, pp.304-305, Feb. 1997, San Francisco, USA; F. Piazza et al, A 0.25 m CMOS Transceiver Front-End for GSM, CICC Proceedings, May 1998, Santa Clara, USA; Q. Huang, On the Exact Design of RF-Oscillators, CICC Proceedings, May 1998, Santa Clara, USA;

5 F. Piazza et al, A 2mA 3V 71MHz IF Ampli er in 0.4 m CMOS Programmable over 80dB Range, ISSCC Digest of Technical Papers, pp. 78-79, Feb. 1997, San Francisco, USA; 6 K. J. De Langen, J. H. Huijsing, Compact 1.8V Low-Power Operational Ampli er Cells for VLSI, ISSCC Digest of Technical Papers, pp. 346-347, Feb. 1997, San Francisco, USA;
vdd CMFB

Image Filter LNA DBM

DUP

Channel Filter IF (71MHz) receiver.ps 97  32 mm 3-stage IF-amp Phase Shifter 90

o

I
Out Sw-g

M5 M4 Vb2 Vb2

M5

1/2

LO (142 MHz) Q

Msw Vb1 M1

1ststage.ps 58  35 mm
M2 M3 M2

M4

Out

Msw M1 Vb1

RF (950MHz)

VCO (1021MHz)

In
100A 290A 90A

M3

In
90A 290A 100A

Mixer LPF

Figure 1: Block diagram of the receiver.

vdd vdd

Figure 2: 1st stage of the IF-amp.

100.8k 100.8k

C1

C2

lo
M3 M4 M5 M6

in-1 in-2

M1

M2

M7

M8

out-2

in

27.3p

37.5p

36A

36A

72A

72A

72A

Figure 3: Schematic of the demodulator.

Figure 4: Block diagram of the output lter. Process Overall Max. Gain Overall Noise Figure Typical IF-amp step error I,Q Image Suppression Power consumtion 0.25 m CMOS 89 dB 3.8 dB 0.4 dB 43 dB 5.5 mA@2.5 V

die.ps 40  45 mm

Figure 5: Die photo of the IF-strip.

7 . : 2 0 F E B d 5 G g o l M R / A 1 H C

Table 1: Measured characteristics.

TRACE A: Ch1+jCh2 Spectrum A Offset -24 000.0 Hz -43.592 dB 20 dBm LogMag

1 2
1

10 dB /div

meas3.ps 64  54 mm

-80 dBm TRACE B: 1.2 I-Q 20 mV /div V Center: 0 Hz Ch1+jCh2 Main Time B Mkr 992.1875 us

meas2.ps 68  51 mm
1.4616 V

Span: 100 kHz 52.404 deg

START 5kHz I N STIMULUS 1 10 kHz 2 159.944 kHz

DATA 15.752 dB 12.768 dB

STOP 500kHz MEMORY -7.6368 -127.16

1 V 643.703713417 mV 1.23629628658 V

Figure 6: Filter characteristic. 4

Figure 7: I and Q demodulatoro outputs.

lo

rx-demod.ps 60  30 mm

M10

40k
M9

28.6k

out-1

lter-schem.ps 40k 80  29 mm

7.1p

4.1p 28.6k

out