A Fault Tolerant Three-Leg Shunt Active Filter Using FPGA for Fast Switch Failure Detection

Shahram Karimi*, Philippe Poure** and Shahrokh Saadate*

* **

GREEN Nancy University Facult des Sciences et Techniques BP 239 54506 Vandoeuvre les Nancy France LIEN Nancy University Facult des Sciences et Techniques BP 239 54506 Vandoeuvre les Nancy France

Abstract The reliability of the VSI (Voltage Source Inverter) components such as semi-conductor switches is critical for the shunt active power filters. A failure in one of the switches decreases system performances and usually leads to disconnect the filter. So, to prevent such undesirable events, real-time fault detection, isolation and compensation must be implemented. This paper proposes new robust fast power switch fault detection and compensation for a three phase shunt active filter without redundant leg. The approach introduced in this paper minimizes the time interval between the fault occurrence in the semi-conductor switches, used in VSI, and its diagnosis. This paper demonstrates that a faulty switch can be detected in less than 10 s without false fault detection due to power semiconductors switching by using simultaneously a time criterion and a voltage criterion. To attain this short detection time, a FPGA (Field Programmable Gate Array) implementation is mandatory. After fault detection, the classical three-leg shunt active filter is reconfigured in a two-leg topology. In this case the faulty phase is connected to the middle point of the DC bus. The experimental results based on FPGA in the loop hardware prototyping validate the performances of the proposed fault detection method for the reconfigurable three-leg active filter topology.

detected in one fourth of the fundamental cycle. These techniques are a kind of knowledge based procedure. This paper discusses theoretically and experimentally the performances of new fast switch fault detection for reconfigurable fault tolerant three-leg three-phase shunt active power filter topology without redundant leg. The approach introduced here minimizes the time interval between the fault occurrence in the semi-conductor switches, used in VSI, and its diagnosis. This paper demonstrates that a faulty switch can be detected in less than 10 s without false fault detection due to power semi-conductors switching by using simultaneously a time criterion and a voltage criterion. To attain this short detection time, a FPGA (Field Programmable Gate Array) implementation is mandatory. The experimental results based on FPGA in the loop hardware prototyping validate the effectiveness and performances of the proposed method. II. FAULT TOLERANT TOPOLOGY The fault tolerant active filter system is shown in Fig. 1. It is composed of a three-phase shunt active power filter, a grid and a non-linear load. The shunt active power filter consists of a three-phase VSI using six IGBTs, three equal series inductances Lf with resistances Rf and a DC capacitor. The non-linear load is a three-phase diode rectifier feeding (R, L) load. The grid is balanced with equal series resistance Rs and inductance Ls. The specifications of the power system are given in Appendix. The output currents of the shunt active filter are controlled to provide harmonic currents generated by the non-linear load to ensure filtering. When a fault has occurred in one of the power switches or the drivers, the fault detection scheme detects the fault occurrence and isolates the faulty leg. If the fault occurred is an opencircuit, the isolation is implemented by removing the gate signals from the switches of the faulty leg. In the case of short- circuit, the faulty leg is isolated by very fast acting fuses. Then, in both cases, the reconfiguration scheme triggers the suited bidirectional switch in order to connect the faulty phase to the midpoint of the DC bus. Therefore, after fault detection, the three-leg VSI topology is reconfigured into a two-leg inverter topology. Haddad and Joos studied the three-leg SAPF topology (before fault occurrence) and the two-leg SAPF topology (after fault detection and reconfiguration) [8]. They demonstrated that the two-leg topology requires switches with blocking capability twice greater than in the classical three-leg configuration [8]:

I. INTRODUCTION Safety, reliability and performances are some of the major concerns for power electronic systems. These systems are protected against the fault conditions such as overload/short circuit fault. The primary function of the protection system is to detect the fault, limit the damage rate and preferably find the location of the fault. Typical protection systems have two major disadvantages; their operation in most of cases leads to disconnect the system and they can not detect some of the fault such as the opencircuit fault in the semi-conductor switches. So, the fault occurrence decreases system performances even with an active protection. Recently, the fault mode behaviour, the protection and the fault tolerant control of three-phase voltage source inverters (VSI) have been covered in a large number of papers [1, 2]. The reliability of the VSI components such as semi-conductor switches is critical for the VSI-based power electronic systems. Reducing the time interval between the fault occurrence in the semi-conductor switches and its diagnosis is one of the major challenging points. The methods suggested in [3-5] take at least one fundamental period to detect the switch or driver failure. With the techniques proposed in [6, 7], the fault is

978-1-4244-1668-4/08/$25.00 2008 IEEE

3342

(vdc)threeleg (vdc)twoleg

=2

Vs1

(1)
n

Rs Rs Rs

Ls Ls Ls

is1 is2 is3

e1 e2 e3 if1 if2

ic1 ic2 ic3 if3

Lc Lc Lc

Rc Rc Rc R L

Vs2 Vs3

Therefore to attain satisfactory performances in both the three-leg and the two-leg topology, the DC bus voltage, vdc, must be regulated twice greater than in the classical three-leg configuration. III. FAULT DETECTION SCHEME The power switch fault detection is based on the comparison between the measured and estimated pole voltages, vko (k = 1, 2, 3), respectively noted vkom and vkoes. The estimated pole voltages can be expressed by:
v vkoes = (2 k 1) dc 2 (2)

Lf Lf Lf Rf Rf Rf f1 S1 1 S4 f2 f3 S2 2 S5 f4 f5 S3 t1 t2 t3

2 Cdc

Vdc/2 o

3 S6 f6

2 Cdc

Vdc/2

Figure 1. Fault tolerant SAPF topology without redundant leg.

Where k = {0, 1} is the switching pattern of the top switch of the leg number k and vdc is the DC bus voltage. The fault occurrence can be detected by analysing the difference between the measured and estimated pole voltages. This voltage error is given by:

ko = vkom vkoes

(3)

With ideal switches consideration, the measured and estimated pole voltages are equal in normal operation and thus the voltage error is zero. In short-circuit case, the faulty leg is either isolated by the switch driver or by the fuses (see Fig. 1). Then, the fault becomes an open-circuit fault. Consequently, only open-circuit fault is studied. In the following, an open-circuit fault for one of the top power switches, Sk (k = 1, 2, 3), is considered. The voltage error, ko, and the measured pole voltage, vkom, are studied analytically. An open-circuit fault reduces the pole inverter topology to the equivalent circuit presented in Fig. 2. In this circuit, the measured pole voltage and consequently the voltage error for the phase k depends on the phase current ifk and on the switching patterns for the leg number k. The analysis of the post-fault behaviour can be divided in two cases. In the first one, ifk is assumed to be different from zero and in the second one the zero crossing condition is considered. A. Post-fault Behaviour when i fk 0 Even though the estimated voltage vkoes only depends on the switching pattern of the Sk, the measured pole voltage, vkom, can be changed with the sign of the phase current ifk: if ifk >0

Figure 2. Equivalent circuit for open-circuit fault in the switch Sk.

Table I presents the voltage error, ko, for this case. We note that when ifk 0, the fault is correctly detected only if ifk> 0 and k = 1 (or k + 3 = 0), otherwise the leg number k operates correctly and the voltage error is zero. A similar analysis could be made for an open-circuit fault in one of the bottom power switches, Sk (k = 4, 5, 6).
TABLE I VOLTAGE ERROR FOR OPEN-CIRCUIT FAULT IN THE SWITCH Sk WHEN ifk 0
ifk

k
1

Dk Off

Dk+3 On

v kom

v koes
v dc 2

ko
vdc 0 0 0

>0

v dc 2 v dc 2 2

>0 <0 <0

0 1 0

Off On Off

On Off Off

v dc 2 2

v dc

v dc

v vkom = dc 2

(4a)

v dc 2

v dc 2

if ifk <0 and k = 0 (or k + 3 = 1)

v vkom = dc 2

(4b)

if ifk<0 and k = 1 (or k + 3 = 0)

v vkom = dc 2

(4c)

B. Post-fault Behaviour when i fk Crosses Zero When k is one and ifk crosses zero, the values of vkom and ko depend on the states of the bypass diodes Dk and Dk+3. In this case, these states depend on the switching patterns of the switches Si and Sj (i j k {1, 2, 3}) and on the phase voltage ekn.

3343

By using the Kirchhoff laws, we established the following equations for (k = 1, 2, 3): Lf
d ifk + Rf ifk + ekn vkn = 0 dt

v if ekn < dc then Dk is off, else Dk is on 3

1 3 v (vdc + ekn) ekn = ekn dc 2 2 2

(5)

vD(k+3) =

Assuming the grid voltages balanced and because of the sum of the active filter currents is null, we deduce: v1n + v2n + v3n = 0 (6)

v if ekn > dc then Dk+3 is off, else Dk+3 is on 3

(6) Case 3: i = j = 1

The output voltages of the inverter can be expressed as: vkn = vko + von From expressions (6) and (7), we obtain: von =
1 (v1o + v2o + v3o) 3

(7)

vDk = ekn [ dc (vdc + ekn)] = ekn (7) 2 2 2 if ekn < 0 then Dk is off, else Dk is on

(8)

vD(k+3) = [

3 vdc 1 (vdc + ekn)] ekn = vdc ekn < 0 2 2 2

When ifk is equal to zero, the voltage vkn is equal to the phase voltage ekn. Thus vko is expressed by: vko = vkn von = ekn von From expressions (8) and (9), we obtain: von =
1 (vio + vjo + ekn) (i j k {1, 2, 3) (10) 2

Dk+3 is off With considerations of the above study, Table II presents the voltage error between the measured and estimated pole voltages for open-circuit fault in the switch Sk when ifk crosses zero during post-fault operation. In this case, when Dk is on, ifk becomes negative and the leg number k operates correctly, thus the voltage error is zero. When Dk+3 is on, ifk becomes positive and thus the voltage error is -vdc and the fault can be detected. When Dk and Dk+3 are off, ifk remains zero and the voltage error depends on the phase voltage ekn and the fault can be detected. A similar analysis can be made for the open-circuit fault in one of the bottom power switches, Sk (k = 4, 5, 6).
TABLE II VOLTAGE ERROR FOR OPEN-CIRCUIT FAULT IN THE SWITCH Sk WHEN k IS ONE AND ifk CROSSES ZERO. case

(9)

The voltages across the bypass diodes Dk and Dk+3 are expressed by: vDk = vkn (
vdc + von) 2

(11) (12)

v vD(k+3) = ( dc + von) vkn 2

Dk+3:

We now study the states of the bypass diodes Dk and

ekn
>0

Dk
Off

Dk+3
Off

v kom

ko
ekn

v dc 2

3 2

3 2

ekn vdc
vdc 0

Case 1: i = j = 0 vDk = ekn [ Dk is off vD(k+3) = [

3 vdc 1 + (vdc ekn)] ekn = ekn 2 2 2 3 vdc 1 + (vdc ekn)] = vdc+ ekn < 0 2 2 2

0 0 Off On

v dc 2 v dc 2

v dc 3
1 0 1 >

On

Off

v dc 3 v dc 3 v dc 3
0 On Off Off Off Off On Off Off

2
0 <

3 2

ekn

v dc 2

3 2

ekn

v dc 2 v dc 2

if ekn > 0 then Dk+3 is off, else Dk+3 is on Case 2: ( i =1 and j = 0) or ( i =0 and j = 1) vDk = ekn
v 1 3 (vdc ekn) = dc + ekn 2 2 2
3
1 1

vdc

<0

v dc 2

3 2

ekn

3 2

ekn

3344

As a result of the post-fault behaviour analysis, with ideal switches consideration, the fault occurrence in each leg can be determined by using a comparison between the measured and estimated pole voltages. However, in real case, because of the turn-off and turn-on propagation time and the dead time generated by the switches drivers, this voltage error is not null and constituted of pick during the switching time. To avoid false fault detections due to power semi-conductors switching, we think of using simultaneously a time criterion and a voltage criterion. C. Time Fault Detection Criterion The time error signal is computed for each phase by first taking the absolute value of the voltage error signal (see Fig. 3). Then, the output is applied to a comparator with a threshold value h. The output of the first comparator, ck, is equal to zero if | ko| h and equal to one if | ko| > h. Thus, the output of this comparator is a repetitive square waveform due to power semi-conductors switching. The up-counter is enabled and starts to count when the output of the first comparator becomes equal to one. The output of the up-counter, nk, is equal to the number of clock pulses while the output of the first comparator is one, if counting is initialised to zero after each square waveform. By considering the up-counter clock frequency, the output of this counter is directly linked to the time during which vkom and vkoes are different. Consequently, the fault occurrence is detected using simultaneously a time criterion and a voltage criterion. To do this, the up-counter output is applied to a second comparator with a threshold value Nt. This threshold value should be chosen several times larger than the switching time. By this way, we avoid false fault detection due to semiconductor switching and the fault condition can be detected in less than 10 s. The resulting signal fk from the fault detection scheme is used to isolate the faulty leg and trigger the suited bidirectional switch tk. IV. ACTIVE FILTER CONTROL STRATEGY The control system used to provide harmonic currents generated by the non-linear load consists of an harmonic isolator and a current controller. The same control strategy is available for both three-leg and two-leg topologies. Consequently, when a fault occurs, no controller reconfiguration is necessary. The control system and the fault detection and compensation scheme are both programmed in only one FPGA. The harmonic isolator computes the current references which must be generated by the active filter. Fig. 5 shows the block diagram of the harmonic isolator. The reference currents are identified using a modified version of the instantaneous active and reactive power method proposed by Akagi [9] associated with two digital voltage and current selective band pass filters [10]. Thanks to the voltage selective band pass filter, the active filter control is completely immunized against the voltage harmonics. The current selective band pass filter is employed as a high pass filter without generation of any phase delay. The DC voltage regulator consists of a proportional controller and a first order low-pass filter used to eliminate the DC voltage ripples. A current controller is used to control the switches (S1-S6) of the voltage source inverter. This controller is a modulated hysteresis current controller detailed in paper [11].
ic1 ic2 abc

Figure 3. Fault detection principle.

vdc DC voltage controller ih ih
v v p&q
calculation

i Selective Band i Pass Filter

p q

pc i i
-ref & -ref

if1-ref abc if2-ref if3-ref

vs1 vs2

abc

Selective Band Pass Filter

calculation

Figure 4. Block diagram of the reference currents generator.

V. FPGA IN THE LOOP RESULTS To validate the effectiveness and performances of the proposed method, the control system and the fault tolerant detection and compensation method have been designed using fixed-point Altera DSP Builder in Simulink environment and implemented into only one Stratix EP1S80B956C6 FPGA chip embedded in a Stratix DSP S80 development board which comprises a 80-MHz oscillator. The fault tolerant three-phase SAPF topology (the plant) shown in the Fig. 1 has been modelled in discretetime mode using Power System Blockset (PSB) in Simulink environment. In our experimental validation so called FPGA in the Loop, the FPGA prototyping board is connected to a PC via a Joint Test Action Group (JTAG). This interface performs communication between the FPGA prototype (which implements in hardware the controller and the fault detection and compensation scheme) and the plant (emulated by the PSB) [12]. At each time step, the Simulink output signals (ic1, ic2, if1, if2, vs1, vs2, vdc, v1om, v2om and v1om) are exported to the FPGA target. When the FPGA receives the signals, it executes the implemented program for one sample interval. The FPGA returns its control signals (S1-S6 and t1t3) computed during this step to Simulink. At this point one sample cycle of the FPGA in the loop prototyping is performed. Fig. 5 shows the FPGA in the Loop prototyping used in the following to implement and evaluate performances of the proposed fault detection and compensation strategy. A Moore Finite State Machine (FSM) is used to implement the fault detection scheme. Fig. 6 presents the state diagram of the fault detection scheme. The control unit of the fault detection scheme is shown in Fig. 7. The up-counter is clocked by a signal with a period of 200 ns, generated from an internal PLL and the threshold value Nt is chosen equal to 25 step (corresponding to 5 s). The waveforms of Fig. 8 present mains phase currents without fault detection and compensation when an opencircuit fault is introduced in the switch S3 at t = 135.5 ms. In this case, the current if3 is positive (case of the analytical study of the section III. A.). Fig. 9 and Fig. 10 show FPGA in the Loop results with fault detection and compensation under the same conditions. Without fault

3345

detection and after fault occurrence, the source current THD values are equal to 10.9%, 8.2% and 15.8% for phase 1, 2 and 3 respectively. Consequently, if the fault is not detected and compensated, active filter performances are decreased and THD values are much greater than the standard value (5%). The results presented in Fig. 9 and the Fig. 10 show that the studied fault tolerant SAPF without redundant leg satisfies the main performance features after fault compensation, i. e. a THD value equal to 1.8%. Fig. 10 shows zoomed FPGA in the Loop results for duration of 100 s. In this case, before fault occurrence if3 is positive and 3 is one. Therefore the fault detection is achieved 5 s after the fault occurrence. In the following, an open-circuit fault is introduced in the switch S3 at t = 122 ms. In this case, the current if3 crosses zero (case of the analytical study of the section III. B.). Fig. 11 and Fig. 12 show FPGA in the Loop results with fault detection and compensation. The studied fault tolerant SAPF satisfies the main performance features after fault compensation. Fig. 12 shows zoomed results for a duration of 100 s. In this case, before fault occurrence, if3 is negative therefore after fault occurrence the leg number 3 operates correctly and the voltage error is zero. At t = 123.629 ms (see Fig. 12), if3 crosses zero. At this time the phase voltage e3n is equal to 30 V and 1 = 3 = 1 and 2 = 0 (case 2 in table II), therefore D3 and D6 become off and if3 remains zero and the voltage error becomes equal to (vdc/2+3/2e3n) thus the fault can be detected. However, the fault is not detected because before a duration of 5 s (at t = 123.632 ms) 3 becomes zero and therefore S3 becomes on and if3 becomes negative, so the leg number 3 operates correctly. When if3 becomes zero for the second time (at t = 123.677 ms) the phase voltage e3n is equal to 35 V and 1 = 3 = 1 and 2 = 0 (case 2 in the table II), therefore D3 and D6 become off and if3 remains zero and the voltage error becomes equal to (vdc/2+3/2e3n) thus the fault can be detected. At t = 123.678 ms 2 becomes one therefore the voltage error becomes 3/2e3n (case 3 in the table II) and if3 remains zero. At t = 123.68 ms 2 other once becomes zero and if3 remains zero (case 2 in table II). Therefore the fault detection is achieved 5 s after the second time that if3 crosses zero.

Figure 6. State diagram of the fault detection scheme.

Reset

fk
Control Unit

ko|

ck

ena

nk

Up res Counter

Figure 7. Control unit of the fault detection scheme.

20

is1 (A) is2 (A) is3 (A)

-20 20

-20 20

-20 0.11

0.115

0.12

0.125

0.13

0.135

0.14

0.145

0.15

0.155

0.16

t (s)

Figure 8. Mains phase currents without fault detection and compensation (S3 is faulty and opened at t = 135.5 ms).
10

is3 (A)

0 -10 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15

(a)
10

t(s)

if3 (A)

0 -10

Figure 5. FPGA in the Loop prototyping.

0.08

0.09

0.1

0.11

0.12

0.13

0.14

0.15

(b)

t(s)

Figure 9. FPGA in the Loop results with fault detection and compensation; (a) Mains phase current is3; (b) Filter phase current if3; (S3 is faulty and opened at t = 135.5 ms).

3346

6 4
i (A)
f3

2 0

135.45

135.50

135.55

conductors switching do not influence over the proposed fault detection scheme. In order to attain such a fast detection time, a FPGA hardware implementation is used. Experimental performances are validated by hardware FPGA in the loop implementation of both controller and detection algorithm in only one FPGA target. REFERENCES
[1] Mendes, A.M.S.; Lopez-Fernandez, X.M.; Cardoso, A.J.M., Thermal Behavior of a Three-Phase Induction Motor Fed by a Fault-Tolerant Voltage Source Inverter, IEEE Transactions on Industry Applications, Volume 43, May-june 2007, pp.724 - 730. D. Kastha and B. KJ. Bose, Investigation of fault modes of voltage-fed inverter system for induction motor drive, IEEE Tran. on Industrial Application, vol. 30, 1994, pp. 1028-1038. R. Peuget, S. Courtine, J. Rognon, Fault detection and isolation on a PWM inverter by knowledge-based model, IEEE Tran. on Industrial Application, vol. 34, 1998, pp. 1318-1325. C. Karl, K. Kafka, Power electronics monitoring for a controlled voltage source inverter drive with induction machines IEEE PESC 2000, pp. 213-217. A.M.S. Mendes, A.J.M. Cardoso, Fault diagnosis in a rectifier inverter system used in variable speed AC drive, by the average current Parks vector approach, EPE 1999, pp. 1-9, Lausanne. R.L.A. Ribeiro, C.B. Jacobina, E.R.C. da Silva, A.M.N. Lima Fault detection in voltage-fed PWM motor drive systems, IEEE IAS Annual Meet., 2000, vol. 1, pp.242-247. R.L.A. Ribeiro, F. Profumo, C.B. Jacobina, G. Griva, E.R.C. da Silva, Two fault tolerant control strategies for shunt active power filter systems, IEEE ISIE 2002, pp.792 797.
K. Haddad, G. Joos, Three phase active filter topology based on a reduced switch count voltage source inverter IEEE Power

1
f3

[2]
135.45 135.50 t(ms) 135.55

Figure 10. Zoomed results (S3 is faulty and opened at t = 135.5 ms).
10

[3] [4] [5]

is3 (A)

0 -10 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15

(a)
10

t(s)

[6] [7] [8]

if3 (A)

0 -10 0.08 0.09 0.1 0.11 0.12 0.13 0.14 0.15

(b)

t(s)

Figure 11. FPGA in the Loop results with fault detection and compensation; (a) Mains phase current is3; (b) Filter phase current if3; (S3 is faulty and opened at t = 122 ms).
1
1

1,2

0.5 0

f3

0 -2 i
f3

e3n (V)

-20 -30 -40 123.6 123.65 123.7

Electronics Specialists Conference, vol. 1, 1999, pp. 236-241. H. Akagi, Y. Kanazawa, A. Nabae, Generalized theory of the instantaneous reactive power filter, International power electronics conference, Japan, 1983, pp. 1375-1386. [10] M.Benhabib, E. Jacquot, S. Saadate,An Advanced control approach for a shunt active power filter International Conference on Renewable Energy and Power Quality, 2003, Spain. [11] M. A. Shamsi-Nejad, S. Pierfederici, J.P. Martin, F. MeibodyTabar, Modelling and design of an hybrid modulated hysteresis current controller Application to a single phase voltage source inverter, 37th IEEE Power Electronics Specialists Conference, Jeju, Korea, 2006. [12] S. Karimi, P. Poure, Y. Berviller and S. Saadate, Design and FPGA in the Loop Prototyping Methodology for Power Electronics System Control, IEEE, 14th International Conference on Electronics, Circuits and Systems, Morocco, 2007, p.p. 701704.

[9]

if3 (A)

APPENDIX SPECIFICATIONS OF THE POWER SYSTEM

t(ms)

Figure 12. Zoomed results (S3 is faulty and opened at t = 122 ms).

VI. CONCLUSION This paper proposes new robust fast power switch fault detection for fault tolerant three-phase SAPFs without redundant leg. The effectiveness of this detection method is theoretically studied in any case of the switching pattern for the switches and of the states of the reverse diodes. The proposed method minimizes the time interval between the fault occurrence and its diagnosis. The FPGA in the Loop experimental results demonstrate the possibility to detect a faulty switch in less than 10 s by using simultaneously a time criterion and a voltage criterion. Depending on system parameters and detection constraints, this time detection can be easily modified by choosing the suited threshold value. Also, power semi-

Mains voltage Mains frequency Mains inductance (Ls) Mains resistance (Rs) Load ac inductor (Lc) Load ac resistance (Rc) Load inductor (L) Load resistance (R) Filter inductor (Lf) Filter resistance (Rf) DC capacitor (Cdc) DC voltage (Vdc)

400 V 50 Hz 0.1 mH 0.2 m 0.8 mH 0.27 m 40 mH 48.6 3 mH 5m 1100 F 1400 V

3347