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A 470-W 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme
Joonhee Lee, Student Member, IEEE, Sunghyun Park, Student Member, IEEE, and SeongHwan Cho, Member, IEEE
AbstractThis paper presents a digitally controlled injectionlocked multimodulus frequency divider (ILMFD) based on a ringoscillator using inverter chains for a small area and low power consumption. In the proposed ILMFD, division ratios of 2, 3, 4, 5 and 6 are achieved by using a programmable delay line that changes the self-oscillation frequency of the ring-oscillator. The locking range of the proposed ILMFD is improved by employing a dual-input injection scheme, which unlike previous multiinput injection schemes, does not require distinct phase inputs. A prototype chip implemented in a 0.13- m CMOS process has an area of 35 33 m2 and operates at 5 GHz while consuming 470 W from 1.2 V supply, where 350 W is dissipated in the core of the ILMFD. The proposed divider is the rst reported multimodulus ILFD with digitally controlled division ratios and an in-phase dual-input injection scheme. Index TermsDual-input injection, injection-locked multimodulus frequency divider (ILMFD), injection locking, in-phase input injection, multimodulus frequency divider, variable division ratios.

I. INTRODUCTION

UE TO THE explosive growth of low-cost wireless hand-held devices, power consumption has become one of the most important design criteria in wireless transceivers. For short-range communication such as Zigbee or Bluetooth, a frequency synthesizer occupies a signicant portion of total power consumption. Since frequency divider is one of the dominant power-consuming components in the frequency synthesizer, it is important to reduce the power consumption of the frequency divider for a low-power frequency synthesizer. A frequency divider based on a current-mode logic (CML) has been widely used in phase locked loops (PLLs) due to its wide locking range and robust operation [1]. However, because its power consumption increases signicantly with the operation frequency, it is not suitable for low power frequency synthesizers. In order to reduce the power consumption of frequency dividers, injection-locked frequency dividers (ILFDs) have been reported in recent years [1][3]. Although they consume less power than the CML dividers, a major drawback is that their locking range is limited and the division ratio

Manuscript received February 04, 2009; revised July 09, 2009. First published October 09, 2009; current version published December 27, 2010. This work was supported in part by the Korea Research Foundation under Grant KRF-2008D00227. The authors are with the Department of Electrical Engineering and Computer Science, KAIST, Daejeon 305-701, Korea (e-mail: ljh0616@gmail.com; xoghkrhfvm@gmail.com; chosta@ee.kaist.ac.kr). Digital Object Identier 10.1109/TVLSI.2009.2030575

cannot be changed. Recently, in order to increase the locking range of ILFDs, a multiple-input injection technique has been proposed. Although this technique increases the locking range, it requires multiphase inputs with accurate phase differences, which is difcult to achieve [4], [5]. For example, in [4], an external phase shifter is used to achieve the desired phase difference. In [5], a static CML frequency divider is used before the ILFD to generate I/Q signals for the multiple-phase input injection. These ILFDs with multiple-input require extra power consumption and silicon area due to the additional circuits that generate multiphase signals. Another disadvantage of the conventional ILFDs is that their division ratio cannot be changed. Although there have been ILFDs that claim variable division ratios [4], [6], [7], their variable division ratios are achieved only when the input frequency is changed. That is, their division ratio cannot be changed for a xed input frequency range. While variable division ratios at 10 GHz have been reported in [8], an analog control scheme is used, that requires an accurate external DC voltage. Hence, additional analog circuits such as a digital-to-analog converter are necessary to provide the desired DC voltage. Therefore, a true digitally controlled multimodulus ILFD has not yet been reported. A digitally controlled injection-locked multimodulus frequency divider (ILMFD) with an in-phase dual-injection scheme was briey presented in [9]. Variable division ratios are achieved in a xed frequency range by using a digitally controlled delay cells that change the self-oscillation frequency of the divider. In addition, a dual-input injection scheme, which does not require multiphase input signals, is employed to increase the locking range. However, the operation principle of the ILMFD has not been analyzed. The specic operation principle of the ILMFD with the dual-input injection scheme was not explained and the theoretical locking range of the ILMFD was not considered in [9] at all. In this paper, we fully analyze the operation principle of the proposed ILMFD, including the locking range in a mathematical form and the verication of the in-phase dual-input injection scheme using additional prototype chip. This paper is organized as follows. Section II shows how the dual-input injection scheme improves the locking range of the ILMFD and how an optimum phase difference for the maximum locking range can be realized. The theoretical locking range of the proposed ILMFD is also derived in the frequency domain. In Section III, the digital control scheme for variable division ratios is proposed and its schematics are explained. Section IV

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Fig. 1. Schematic of the ILFD with programmable delay cells. Fig. 3. Schematic of the ILFD with the dual-input injection scheme.

When the input signal is injected to the ILFD through , the of A input signal begins to synchronize the cross points and B with its peak points by turning on . When the division ratio is 2, as shown in Fig. 2(a), the input signal synchronizes the cross points with its input peak points at every cycle of the input signal. When the division ratio is 5, the output period of due to the the ring-oscillator is approximately increased to is turned on every cycle of additional delay cells. Although the input signal, the synchronization happens only once within as shown in Fig. 2(b). This a given interval is because is weaker than the inverter delay cell, , and can make the node voltages of A and B equal (i.e., hence ) only when and are close together. When and are far apart and driven by , (e.g., , ), cannot force and to be equal. Hence, for the remaining 4 cycles, there is no synchronization by as shown in Fig. 2(b). Therefore, when the division ratio is increased, the locking range of the ILFD becomes narrower due to fewer synchronizations within a given interval. B. Dual-Input Injection Scheme to Improve Locking Range
Fig. 2. Input voltage and node voltages of A and B. (a) When the division ratio is 2. (b) When the division ratio is 5.

analyzes the experimental results and Section V concludes this paper. II. OPERATION PRINCIPLE OF THE PROPOSED ILFD WITH THE IN-PHASE DUAL-INPUT INJECTION A. Qualitative Analysis of the ILFD With Programmable Delay Cells The schematic of an ILFD with programmable delay cells is shown in Fig. 1 which is a modication of the divide-by-2 is inserted in one of circuit in [2]. The nMOS switch the inverters to inject the input signal into the ILFD. The programmable delay cells, details of which will be described in Section III, are added to change the self-oscillation frequency of the ring-oscillator, which enables variable division ratios. Unfortunately, when the division ratio is increased, the locking range of the ILFD is decreased. This phenomenon can be intuitively explained in time-domain as shown in Fig. 2, where the input voltage and node voltages of A and B are shown, when the division ratio is 2 and 5, respectively.

In order to increase the locking range, a multiple-input injection scheme can be employed [4], [5]. In the proposed circuit, a dual-input injection scheme is used as shown in Fig. 3, where is applied to an -stage ring osadditional input injection cillator. In order to maximize the locking range, it is important to optimize the phase difference between the two injected inputs. In previous works, the phase difference was created using phase shifters [4], [5] that resulted in large power consumption and area. In this work, our goal is to integrate the phase shifter together with the ILFD. In order to do so, we rst calculate the phase difference that maximizes the locking range and then design a circuit that provides the desired phase difference. To calculate the optimum phase difference, the ILFD is modwith and are currents eled as shown in Fig. 4, where and , respectively. Note that each injected to the ILFD by injected current has phase shift of and , and their phase dif. and are the current owing ference is in the -th inverter and the load stage, respectively. Note that when . Each inverter is modeled using an ideal inverter with a phase shift of and a load stage which and capacmodels the delay of the inverter using resistor itor . The phase shift at each load stage can be expressed as (1)

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Fig. 4. Equivalent circuit of the ILFD with the dual-input injection scheme when f

= f + 1f

the injection. By using (2), (3), and (5), the single-sided locking in terms of can be expressed as range

(6) It can be seen that the single-sided locking range is determined by the phase shift caused by the injected currents. To nd the relationship between the phase shift and the injected signals, a phasor diagram of the current is used , as shown in Fig. 6, where the current relation among , , and can be expressed as

Fig. 5. Phase shift at each stage of the proposed ILFD when f

= f + 1f

where . Note that when the ILFD operates at self-oscillation frequency, , and there is no injection of curto meet rents, the phase shift at each load stage must be the Barkhausen criteria. That is (2) In order to investigate the locking range mathematically, a phase shift diagram is used as shown in Fig. 5 [2], [4], [10]. The phase shift of each inverter stage is represented by the sum , the load stage of the phase shift due to the ideal inverter and the injected current . When the input current is injected to the ILFD and the ILFD locks at , where is the single-sided locking range, additional phase shift arises at each load stage. Hence, the phase shift at the load in (2) can be modied as (3)

. . . (7) When sine law is used in Fig. 6(a) to calculate , we obtain (8) and hence is described as (9) is dened as . Note that indicates where compared to that of the the strength of the injected signal by inverter in the ring-oscillator. To calculate , sine law is used in Fig. 6(b), which can be described as (10) where is the phase difference between can be described as and , that

To satisfy the Barkhausen criteria for oscillation, the total and hence the following phase shift of the loop must be condition must be met (4) Therefore, the relation between and can be expressed as (5) This equation implies that the oscillation frequency must change so that the phase shift of the load cancels the phase shift due to

(11)

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Fig. 6. Phase diagram of the current when f

= f + 1f

Since the node voltages of the A and B are almost the same when is much the input signal is high, the current that ows in smaller than the current that ows in the ring-oscillator. Hence, must be small and we can assume that the phase shift due to and for and . Hence, in (10) can be described as

Fig. 7. Calculated locking range according to phase difference tween two injected inputs and .

( 0  ) be-

(12) and (11) can be described as (13) By plugging (12) and (13) to (10), is described as (14) is dened as . Since both where are caused by , and are the same. Therefore, is described as and that it is desirable to increase to improve the locking range. Moreover, it can be seen that the maximum locking range occurs when the phase difference is around which can easily be is implemented as one generated by one inverter. Therefore, inverter as shown in Fig. 8 and hence the proposed dual-input injection scheme require only the single-phase input signal. Alfor the wide locking range though it is desirable to increase as shown in Fig. 7, there exists a practical limitation of . If is excessively increased, the ILFD operates at the the size of unwanted frequency, which leads to an unlock state. Hence, it is and extracted from necessary to nd a proper the size of circuit simulation is 0.4 in the proposed ILFD. Fig. 9 shows the calculated locking range according to phase difference between the two injected inputs and . It can be seen 11. that the locking range is maximized around for Hence, the proposed dual-input injection scheme can improve the locking range for each division ratio in the proposed ILMFD which will be explained in Section III and the division ratios are changed by . C. Locking Range of the ILFD With the In-Phase Dual-Input Injection Scheme It can be seen that when the phase difference is , the locking range of the proposed ILFD is almost similar to the maximum value as shown in Fig. 9. Hence, the locking range of the ILFD can be approximately expressed as the maximum locking range. The maximum locking range of the ILFD can be calculated by
Fig. 8. Schematic of the ILFD with the dual-input injection scheme.

(15) There are two terms which determine the phase shift in (15). and the other is term due to . One is the term due to Hence, it can be seen that the locking range is increased due to the added injection current compared to single-input injec. While the locking range depends on the tion with only and , we focus on the implementation of the values of phase shifter that generates the optimum phase difference for and maximum locking range. Hence, we focus on which is a function of . In order to nd the optimum value , the single-sided normalized locking range of the of is calculated using (6) and (15). The calcuILFD lated locking range according to phase difference between two and exinjected inputs and is shown in Fig. 7 where tracted from circuit simulation is 0.1. Note that is the number of the inverters and determines the division ratio of the proposed ILFD, which will be explained in Section III. It can be seen

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Fig. 9. Calculated locking range according to phase difference ( tween two injected inputs and N .

0  ) beFig. 10. Chip microphotograph of two ILFDs.

plugging the maximum values of ating (9), the maximum value of

, , and . By differentican be achieved as follows:

(16) Similar to follows: , the maximum value of can be calculated as

(17) By substituting (16) and (17) to (6), the maximum can single-sided normalized locking range be expressed as

Fig. 11. Measured input locking range of two ILFDs.

TABLE I NORMALIZED LOCKING RANGE OF TWO ILFDS

(18) where

(19) a ring-oscillator with seven identical inverters instead of programmable delay cells for division ratio of 2. The die photo of the prototype chip is shown in Fig. 10 and the active area is m , excluding pads. Fig. 11 shows the input locking range of two ILFDs. It can be seen that the locking range of the ILFD with dual-input injection is two times larger than that of the ILFD with the single-input injection. The measured normalized locking range and the calculated normalized locking range using and are 0.4 and 0.1, re(18) are shown in Table I where spectively. It can be seen that the measured results correspond very well to the calculated results in the two ILFDs.

where

D. Demonstration of the ILFD With the In-Phase Dual-Input Injection Scheme To verify the increase in locking range of the proposed ILFD, two ILFDs have been fabricated in a 0.25- m CMOS process, one which is the conventional ILFD shown in Fig. 1 and the other is the proposed ILFD shown in Fig. 8. Two ILFDs have

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Fig. 12. (a) Schematic of the proposed ILMFD. (b) Schematic of the inverter,

D  D . (c) Schematic of the inverter, D  D

III. IMPLEMENTATION OF THE INJECTION-LOCKED MULTIMODULUS FREQUENCY DIVIDER A. Digital Control Scheme and Implementation of the ILMFD To overcome the disadvantages of an analog control scheme such as large power consumption and large silicon area, a digital control scheme is proposed as shown in Fig. 12. There are ve internal loops which correspond to the division ratios of 2, 3, 4, 5, and 6 in the ILMFD. The division ratio can be changed by selecting one of the ve internal loops which consist of one switch implemented as a transmission gate and several inverters. If additional loop is inserted in the ILMFD, the range of division ratios can be easily extended. As explained in Section II, and , of which the input signal is injected through provides the required phase shift. This digital control scheme also has the advantage in the aspect of the low pass ltering effect [11]. When the division ratio is increased, there are many sub-harmonics due to the low selfoscillation frequency of the ILMFD. In the proposed ILMFD, as numbers of the inverters are increased with the division ratio, the sub-harmonics are reduced. B. Adaptive Bias Current Control In PLLs, since a frequency divider follows a VCO, the operation frequency range of the frequency divider must cover the tuning range of the VCO. Although the proposed ILMFD has wide locking range, it may not be enough for some applications. In order to further increase the locking range, the proposed ILMFD is designed so that its self-oscillation frequency can be adaptively changed according to the VCOs output frequency.

That is, the self-oscillation frequency is changed by controlling the bias current of the current starved inverters used in the ILMFD shown in Fig. 12(a). to and to are The detailed schematics of to shown in Fig. 12(b) and (c), respectively. Sizes of are designed to meet the desired self-oscillation frequency for the division ratios of 2, 3, 4, 5, and 6. When the division ratio is of to can be expressed as 2, each delay

(20) where is the output period of the ring-oscillator, and is the delay of one transmission gate, which is negligible compared to . When the division ratio is 3, the following condition must be met:

(21) and are delays of and , respectively. Acwhere cording to (21), sizes of and must be larger than to decrease the delay. Similarly, sizes of to are determined using the calculation procedure described in (21) for the other division ratios of 4, 5, and 6. In this paper, a single-ended ILFD is implemented as a proof-of-concept. Due to the singleended nature, the proposed ILFD may suffer from commonmode noise and supply variations. A fully-differential scheme that is more robust is also possible.

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Fig. 16. Measured spectrum of the proposed ILMFD (a) when division ratio is 3 (b) when division ratio is 5. Fig. 13. Adaptive bias current control scheme.

Fig. 14. Chip microphotograph of the proposed ILMFD.

Fig. 17. Measured input locking range of the proposed ILMFD.

Fig. 15. Measurement setup.

This bias current control scheme also reduces the effect on the ILMFDs performance caused by process, voltage and temperature (PVT) variations. When the desired self-oscillation frequency is increased or decreased due to PVT variations, this scheme increases or decreases the bias current to reduce the variation of the self-oscillation frequency, thereby reducing the effect of PVT variations. IV. MEASUREMENT RESULTS The proposed ILMFD is implemented in a 0.13- m CMOS process where the die photo is shown in Fig. 14. The active area m , where of the ILMFD including the control logic is m and the control the divider core occupies 52% logic occupies 48% of the active area. The measurement setup is shown in Fig. 15. A signal generator (HP 83712) is used to generate an input signal and a DC voltage is provided through an external bias tee. A spectrum analyzer (HP 8563) is used to measure the spectrum of an output signal and a signal source analyzer (Agilent 5052) is used to measure the phase noise of the output signal. The output spectrum of the ILMFD is shown in Fig. 16 when the input frequency is 5 GHz. The output frequency is 1.668 GHz and 1 GHz when the division ratio is 3 and 5, respectively. The measured input locking range of the proposed divider is shown in Fig. 17 for division ratios of 2, 3, 4, 5, and 6 when the

For , a switch is inserted to reduce power consumption of the ILMFD. For example, when the division are turned off as they are ratio is 4, four inverters not necessary. The adaptive bias current control scheme is shown in Fig. 13, where the ILMFD is used in a PLL. A digitally controlled bias circuit generates a bias voltage for the current starved inverters according to the control signals for the division ratio. Since the output frequency of the VCO is proportional to the division ratio increases then the divider must lock at of the divider, if a higher frequency. By increasing the bias current that is controlled according to the division ratio, the ILMFDs self-oscillation frequency is increased and hence can lock at a higher frequency. While the above PLL has not been implemented, measurement results in Fig. 17 show that the locking range can indeed be changed according to the bias current, indicating that the proposed ILMFD can be used for the adaptive bias current control scheme.

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Fig. 18. Measured normalized locking range and calculated normalized locking range of the proposed ILMFD.

Fig. 20. Simulated input sensitivity of the ILMFD for the division ratios of 2, 3, 4, 5, and 6.

Fig. 21. Measured phase noise of the proposed ILMFD. Fig. 19. Input signal and output signal for the division ratios of 2, 3, and 4.

input frequency is from 3.5 GHz to 5 GHz. The input locking range is as large as 3 GHz (2.56 GHz to 5.56 GHz) when the division ratio is 2 and it is reduced to 1 GHz (4 GHz to 5 GHz) as the division ratio is increased. The measured normalized locking , where is the locking range and is the selfrange oscillation frequency of the ring-oscillator, and the calculated normalized locking range of the ILMFD using (18) are shown in Fig. 18. The simulated locking range is also shown in Fig. 18. It can be seen that there is close correspondence between the simulated results, the theoretical results, and the measurement results. Strictly speaking, (6), (13) and (15) should be modied when the delay cells are sized differently. In order to investigate the modied locking range mathematically, the phase shift diagram shown in Fig. 5 must be modied and the additional phase shift due to the differently sized delay cells must be introduced. When the locking range is calculated considering the modied phase shift diagram, the resulting equation has the additional variables and it is difcult to nd any meaning or intuition out of it. As the purpose of this analysis is to provide a basis of how the phase shifter should be implemented, such complicated equation without much intuition is not meaningful. Note that even

if we use the original equations which assume identical delay cells, the error between the calculation and the measurement is less than 10%. One interesting observation that can be found in Fig. 18 is that the measured locking range is larger than the calculated is 2 and 4. A more imporlocking range particularly when tant observation that must be made is that the measured locking . This range is not a monotonically decreasing function of result is contrary to what the phasor-domain analysis suggests is increased. that the locking range should decrease when For easier explanation, Fig. 18 is shown in a tabular form in Table III, where it can be seen that the nonmonoticity occurs is changed from an odd number to an even number. when ). Such discrepancy between theory (i.e., and measurement is a shortcoming of the phasor-domain approach and we believe that it can be intuitively explained in time domain as shown in Fig. 19, where the input signal and the output signals of the ILMFD are shown for the division ratios of 2, 3, and 4. When the division ratio is 2 or 4, the rising edge and the falling edge of the output signal is synchronized with the peak points of the input signal, and hence the ILMFD can easily enter the injection locked mode. However, when the division ratio is 3, the falling edge of the output signal is not aligned with the peak points of the input signal. Note that in

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TABLE II COMPARISON OF ILFDS

TABLE III CALCULATED LOCKING RANGE AND THE MEASUREMENT LOCKING RANGE

TABLE IV NUMBER OF SYNCS AND INPUT CYCLES WITHIN AN OUTPUT PERIOD

the phase-domain analysis, the effect of the synchronization between the rising or the falling edge and the peak points of the input signal is not modeled. is even (i.e., , In general, when ), the ILFD has the additional synchronization at , the the falling edge of the output. Hence, when locking range may be larger than the case when due to the additional sync, despite the fact that the increase in decreases the locking range. It should also be noted that the added syncs at the falling edge will be more effective in is small. That is, when increasing the locking range when , sync occurs once every three input periods since only the rising edge is synchronized. However, when , sync occurs twice every four input periods, which is more than as shown in Fig. 19. When , the case when , sync occurs once every ve input periods, but when sync occurs twice every six input periods, which is still more , but not as effective as the case than the case when due to higher . This is summarized in when Table IV, where number of synchronizations and input cycles within an output period is shown. The input sensitivity of the proposed ILMFD for division ratios of 2, 3, 4, 5, and 6 is shown in Fig. 20. It can be seen that the input sensitivity improves with smaller division ratio. Note that this input sensitivity is based on circuit simulation. Since the input buffer shown in Fig. 15 is used and on-wafer probing of the ILMFD was not possible, an experiment could not be performed. While the input sensitivity is based on simulation,

we believe it is close to the real result, as we have found close correspondence between the simulation and the measurement. For example, the maximum difference between the simulation and the measurement for the self-oscillation frequency of the ILMFD was less than 100 MHz (7%). The maximum difference between the simulation and the measurement for the normalized locking range was also less than 10%. Moreover, the difference between the simulation and the measurement for the output power was less than 1 dBm. Therefore, we believe that the simulation well reects the actual input sensitivity. The measured phase noise of the ILMFD is shown in Fig. 21 when the division ratio is 2. The solid line is the phase noise of HP 83712 at 5 GHz and the dashed line is the phase noise of the ILMFD at 2.5 GHz. The top line is the phase noise of the ring-oscillator when it is free-running. At low offset frequency, the phase noise of the ILMFD is about 6 dB lower than that of the input signal due to the divided-by-2 operation and it can be seen that the phase noise is determined by the input signal source rather than the divider itself. At higher offset frequencies, the phase noise of the ILMFD becomes larger due to the poor phase noise of the ring-oscillator [13]. The power consumption of the ILMFD is 420 W and 470 W when input frequency is 3.5 GHz and 5 GHz, respectively. Note that this power consumption includes the output buffer shown in Fig. 12. The simulation result which corresponds very well to the measurement result indicates that the power consumption of the core and the output buffer is 350 W and 120 W when the input frequency is 5 GHz.

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The measured performance of the ILMFD is summarized in Table II together with other ILFDs. It can be seen that this work presents the only divider that has digitally controlled division ratios. In addition, unlike other multiple-input injection techniques [4], [5] that require multiphase inputs, our divider requires only single-phase input. Moreover, it can be seen that the proposed ILMFD has the largest power efciency and the smallest area. V. CONCLUSION In this paper, an ILMFD with a digital control scheme for variable division ratios is presented for the rst time. The proposed ILMFD is based on a ring-oscillator for a small area and low power consumption. The locking range of the proposed ILMFD is improved by employing a dual-input injection scheme with an integrated phase shifter implemented as one inverter, which unlike previous multiinput injection schemes, does not require distinct phase inputs. Moreover, the ILMFD performs division ratios of 2, 3, 4, 5 and 6 by selecting a specic loop which consists of one transmission gate and several inverters. REFERENCES
[1] S. Cheng, H. Tong, J. S. Martinez, and A. I. Karsilayan, A fully differential low-power divide-by-8 injection-locked frequency divider up to 18 GHz, IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 583591, Mar. 2007. [2] K. Yamamoto and M. Fujishima, A 44- W 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 11701174, Mar. 2005. [3] M. Motoyoshi and M. Fujishima, 43 W 6 GHz CMOS divide-by-3 frequency divider based on three-phase harmonic injection locking, in Proc. IEEE Asian Solid-State Circuits Conf., 2006, pp. 183186. [4] J.-C. C. Chien and L.-H. Lu, Analysis and design of wideband injection-locked ring oscillators with multiple-input injection, IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 19061915, Nov. 2007. [5] A. Mirzaei, M. E. Heidari, R. Bagheri, S. Chehrazi, and A. A. Abidi, Multi-phase injection widens lock range of ring-oscillator-based frequency dividers, IEEE J. Solid-State Circuits, vol. 43, no. 3, pp. 656671, Mar. 2008. [6] R. J. Betancourt-Zamora, S. Verma, and T. H. Lee, 1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers, in Proc. Symp. VLSI Circuits, 2001, pp. 4751. [7] M. Acar, D. Leenaerts, and B. Nauta, A wideband CMOS injectionlocked frequency divider, in Proc. Radio Freq. Integr. Circuits Symp., 2004, pp. 211214. [8] F. H. Huang, D. M. Lin, H. P. Wang, W. Y. Chiu, and Y. J. Chan, 20 GHz CMOS injection-locked frequency divider with variable division ratio, in Proc. Radio Freq. Integr. Circuits Symp., 2005, pp. 469472. [9] J. Lee and S. Cho, A 470- W multimodulus injection-locked frequency divider with division ratio of 2, 3, 4, 5 and 6 in 0.13- m CMOS, in Proc. IEEE Asian Solid-State Circuits Conf., 2007, pp. 332335.

[10] B. Razavi, A study of injection locking and pulling in oscillator, IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 14151424, Sep. 2004. [11] W. Z. Chen and C. L. Kuo, 18 GHz and 7 GHz superharmonic injection-locked dividers in 0.25 m CMOS Technology, in Proc. Eur. Solid-State Circuits Conf. Symp., 2002, pp. 8992. [12] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee, and M.-H. Juang, A wide locking range and low voltage CMOS direct injectionlocked frequency divider, IEEE Microw. Wireless Compon. Lett., vol. 16, pp. 299301, May 2006. [13] S. Verma, H. R. Rategh, and T. H. Lee, A unied model for injectionlocked frequency dividers, IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 10151027, Jun. 2003. Joonhee Lee (S05) received the B.S. degree in electronic engineering from Yonsei University, Seoul, Korea, in 2003, and the M.S. degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2005, where he is currently working toward the Ph.D. degree. His research interests include analog and mixedsignal circuits for low-power high performance communication systems.

Sunghyun Park (S05) received the B.S. degree in electrical engineering and computer science from KAIST, Daejeon, Korea, in 2008. Since 2009, he has been with Massachusetts Institute of Technology, Cambridge, MA, where he is currently working toward the M.S. degree. His research interests include low-power design of analog and mixed-signal circuits. Mr. Park is a recipient of the Samsung Scholarship.

SeongHwan Cho (S94-M03) received the B.S. degree in electrical engineering from KAIST, Daejeon, Korea, in 1995 and the M.S. and Ph.D. degrees in electrical engineering and computer science from the Massachusetts Institute of Technology, Cambridge, in 1997 and 2002, respectively. During the summer of 1999, he was with the IBM T.J. Watson Research Center, Yorktown Heights, NY. In 2002, he was with Engim, Inc., where he was involved in data converters, phased-locked loops, and voltage-controlled oscillator design for IEEE 802.11(a)(b)(g) WLANs. In 20032004, he served the military of Korea as a Public Service Agent. Since November 2004, he has been with the Department of Electrical Engineering and Computer Science, KAIST, where he is now an Associate Professor. His research interests include analog and mixed-signal circuits for low-power high performance communication systems. Prof. Cho was the co-recipient of the 2009 IEEE Circuits and System Society GuilleminCauer Best Paper Award. He is serving and has served as a member of the TPC in several IEEE conferences, including ISSCC, A-SSCC, ASP-DAC, and ISLPED. He was the Technical Program Committee Vice-Chair of A-SSCC 2008.