Dalal Patel H.No:70, First Floor, Jubilee Hills, Hyderabad, Email: dalalpatel@gmail.com Andhra Pradesh, India.

Mobile: +91-9959244237 _______________________________________________________________________ Professional Experience 1 year experience in EDA Verification industry. Summary of Qualifications Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog. Very good knowledge in verification methodologies OVM, UVM. Experience in using industry standard EDA tools for the front-end design and verification VLSI Domain Skills HDLs: HVL: Verification Methodologies: EDA Tool: Knowledge: Verilog and VHDL SystemVerilog and PSL UVM, OVM. Modelsim 10.0b ASIC/FPGA Design Flow, Digital Design methodologies RTL Coding, Code Coverage, Functional Coverage, ABV.

Professional Qualification Certified in Advanced VLSI Design and Verification course From Sandeepani VLSI Institute, Bangalore Year: July 2010. Bachelor of Engineering, Vageeshwari Engineering College, Karimnagar, India Discipline: Electronics & Communication Engineering Percentage: 65% First Class Year: May 2011 Achievements Gold medalist in engineering Received the best performer award from Maven Silicon during the VLSI Design course

VLSI Projects SPI Controller Core - Verification HVL: SystemVerilog EDA Tools: Modelsim, Questa -- Verification Platform Description : The SPI Controller Core is an interface between wishbone compatible Master Device and SPI interface Slave device. It supports variable length of transfer word and the core can be configured for 1 to 32 bit, 64 & 128 bit. It supports data latching and data transfer at both edges of clock.This core can be configured to connect with 32 slaves. The SPI Clock frequency can be adjusted by configuring desirable value in 32 bit clock divider register.The SPI Core RTL is technology independent and fully synthesizable. Architected the class based verification environment using system Verilog Verified the RTL module using System Verilog Generated functional and code coverage for the RTL verification sign-off

UART- IP Core Verification HVL : System Verilog EDA Tools: Modelsim. The UART IP core consists of a transmitter, a receiver, a modem interface, a baud generator, an interrupt controller, and various control and status registers. This core can operate in 8-bit data bus mode or in 32-bit bus mode, which is now the default mode. It is an interface between wishbone compatible UART transceiver, which allow communication with modem or other external devices, like another computer using a serial cable and RS232 protocol. The UART core RTL is technology independent and fully synthesizable. Architected the class based verification environment using system Verilog Verified the RTL module using System Verilog Generated functional and code coverage for the RTL verification sign-off