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Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Prof. Randy Katz (Unified Microelectronics Corporation Distinguished Professor in Electrical Engineering and Computer Science at the University of California, Berkeley) and Prof. Gaetano Borriello (University of Washington Department of Computer Science & Engineering) from Chapter 2 of R. Katz, G. Borriello. Contemporary Logic Design. 2nd ed. Prentice-Hall/Pearson Education, 2005. J. Rabaey, A. Chandrakasan, B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice Hall/Pearson, 2003.
in0 in1
in0
Combinational Circuit
in1
inN-1
inM-1
Combinational logic circuits are memoryless No feedback in combinational logic circuits Output assumes the function implemented by the logic network, assuming that the switching transients have settled Outputs can have multiple logical transitions before settling to the correct value
L4: 6.111 Spring 2006 Introductory Digital Systems Laboratory 2
A Sequential System
Inputs COMBINATIONAL LOGIC Current State Registers Q D Next state Outputs
Memory element
CLK
Sequential circuits have memory (i.e., remember the past) The current state is held in memory and the next state is computed based the current state and the current inputs In a synchronous systems, the clock signal orchestrates the sequence of events
L4: 6.111 Spring 2006 Introductory Digital Systems Laboratory 3
A Simple Example
Adding N inputs (N-1 Adders)
in0 in1 in2 inN-1
in
DQ
clk
Current_Sum
Vo2 = Vi1
Point C is Metastable
C
V o1
Vi2
V i2 = V o
1
Vi1 = V o2
V i1 A V i 2 = V o1 C
V o2
B V i 1 = V o2
L4: 6.111 Spring 2006
B
V i1 = V o2
5
S R
Q Q S 0 R 0 0 1 1 Q Q 1 0 0 Q Q 0 1 0
SR = 1 1 QQ 01
QQ 10 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 1 QQ 00
1 0 1
Q
Reset
Forbidden State
Hold Set Reset Set
SR = 0 0
SR = 0 0
R S Q Q
??
Flip-flop refers to a bi-stable element (edge-triggered registers are also called flip-flops) this circuit is not clocked and outputs change asynchronously with the inputs
L4: 6.111 Spring 2006 Introductory Digital Systems Laboratory 6
hold
sample
hold
sample
hold
D G
R and S
clock
clk
A Positive D-Latch: Passes input D to output Q when CLK is high and holds state when clock is low (i.e., ignores input D) A Latch is level-sensitive: invert clock for a negative latch
L4: 6.111 Spring 2006 Introductory Digital Systems Laboratory 7
Positive Latch
Negative Latch
CLK
CLK
clk clk
"data" "load" "remember" "stored value"
2 13
1D
LE1-2
D CP
1Q
16
Q L1
1Q
2D
D CP
2Q
15
Q L2
2Q
14
Operating Modes
H H Data Latched L
Inputs
LEn-n
Outputs nD
L H X
nQ
L H q
nQ
H L q
6 4
3D
LE3-4
D CP
3Q
10
Data Enabled
Q L3 7 4D
3Q
11
D CP
4Q
Q L4
4Q
D Q G
D Q G
D Q
CLK
CLK
Slave Master
0 1 D 0 QM 1 Q CLK D QM Q
CLK
CLK
Master-Slave Register
Use negative clock phase to latch inputs into first latch Use positive clock to change outputs with second latch
Transparent latches sample inputs as long as the clock is asserted Timing Diagram:
D Clk Q 7474
7475
D C Clk Level-sensitive latch Q
Q 7475
Behavior the same unless input changes while the clock is high
Introductory Digital Systems Laboratory 11
Clock
memory element can be updated on the: rising edge, falling edge, high level, low level Setup Time (Tsu) Minimum time before the clocking event by which the input must be stable Hold Time (Th) Minimum time after the clocking event during which the input must remain stable Propagation Delay (Tcq for an edge-triggered register and Tdq for a latch) Delay overhead of the memory element
There is a timing There is a timing "window" around the "window" around the clocking event clocking event during which the during which the input must remain input must remain stable and stable and unchanged in order unchanged in order to be recognized to be recognized
12
J K
Q J K 0 1 0 1 Q+ Q 0 1 Q Q+ Q 1 0 Q
0 0
100 J K Q \Q
1 1
Eliminate the forbidden state of the SR Flip-flop Use output feedback to guarantee that R and S are never both one
L4: 6.111 Spring 2006 Introductory Digital Systems Laboratory 13
J K
S R
Q Q
P P
S R
Q Q
CLK
J K Clk
Set
Reset
1's Catch
Toggle
100
J K
Q Q
P \P Q \Q
Input
X
Input
Output
Schematic
Output X
tpLH
J K S R Q Q
J K
Q Q
Pulse-Triggered Registers
Ways to design an edge-triggered sequential cell:
Master-Slave Latches Pulse-Based Register
L1
Data D Q Clk Clk
L2
D Q Clk Data Clk
Latch
D Q Clk
Short pulse around clock edge Pulse registers are widely used in high-performance microprocessor chips (Sun Microsystems, AMD, Intel, etc.) The can have a negative setup time!
L4: 6.111 Spring 2006 Introductory Digital Systems Laboratory 17
1 0 1
Clk D 0 1 QN 0 1
0 1
T (Toggle) Flip-Flop
T Q
Clk T 0 1
L4: 6.111 Spring 2006
0
QN Q N-1 QN-1
1
Introductory Digital Systems Laboratory 16
J Q C K Q
K D Q J C Q
Design Procedure
Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?
Q Q+ 0 0 0 1 1 0 1 1
J K 0 X 1 X X 1 X 0
T 0 1 1 0
D 0 1 0 1
D Q 0 1 0 0 0 1 1 1
Implementing D FF with a J-K FF: 1) Start with K-map of Q+ = (D, Q) 2) Create K-maps for J and K with same inputs (D, Q)
3) Fill in K-maps with appropriate values for J and K to cause the same state changes as in the original K-map
D Q 0 0 X 1 1 X D Q 0 1 0 X 1 1 X 0
Q+ = D
E.g., D = Q= 0, Q+ = 0 then J = 0, K = X
0 1
J= D
L4: 6.111 Spring 2006
K =D
18
JK Q 0 1 00 0 1 01 0 0 11 1 0
J 10 1 1
K Q+ = D = JQ + KQ
Resulting equation is the combinational logic input to D to cause same behavior as J-K FF. Of course it is identical to the characteristic equation for a J-K FF.
19
In
D Q
Combinational Logic
D Q
Clk
Clk
Register Timing Parameters Tcq : worst case rising edge clock to q delay Tcq, cd: contamination or minimum delay from clock to q Tsu: setup time Th: hold time
L4: 6.111 Spring 2006
Logic Timing Parameters Tlogic : worst case delay through the combinational logic network Tlogic,cd: contamination or minimum delay through logic network
20
Combinational Logic
D Q
Clk CLK
Th Th Tsu
Clk
IN
Tsu Tcq Tcq,cd Tlogic Tcq Tcq,cd Tsu2
FF1 CLout
Tl,cd
Combinational Logic
D Q
Clk CLK
Th Th
Clk
IN
Tsu
FF1
Tcq,cd
CLout
Tl,cd
Shift-Register
Typical parameters for Positive edge-triggered D Register
D Tsu Th 20ns 5ns Tw 25ns Tplh 25ns 13ns Tphl 40ns 25ns Tsu 20ns Th 5ns all measurements are made from the clocking event that is, the rising edge of the clock
CLK
Shift-register
IN DQ Q0 DQ Q1
100
OUT
IN Q0 Q1
CLK
CLK
23