2

Architecture of 8086
A microprocessor chip is composed of two worlds - the inner world and the outer world. The outside world consists of metallic pins for being connected with memory, port and the decoding devices. The MPU uses its metallic pins for conveying the address, data and control signals to the external devices. Therefore, it is imperative that we have good understanding on the Electrical Characteristics and the Functional Properties of these pins. The detailed study of these two parameters is covered under the title of External Architecture. The inner world consists of complex electronic circuitry (Fig 2.43), which generates bus signals and processes data that the MPU receives from the external memory and port devices. The detailed study of the inner world electronics is covered under the caption of Internal Architecture.

2.1 (a) Physical Pin Diagram

The physical pin diagram of the minimum mode 8086 microprocessor is repeated in Fig-2.1. It has 40-pins and is accommodated in a CERDIP (CERamic Dual In Package) or plastic DIP package. The inline pins are separated from each other by 0.1-inch and offline pins are by 0.3 inch. The physical dimension of the 8086 is just 2-inch x 0.3-inch. The CPU design has been implemented using HMOS technology to achieve high performance. The 8086 operate at 5MHz, the 8086-2 at 8MHz and the 8086-1 at 10 MHz with maximum power dissipation of 2.5W. There are corresponding CMOS versions (80C86, 80C86-2, 80C86-1), which operate at the same frequencies as for the HMOS 8086s but with maximum power dissipation of 1W. The 8086 supports another mode of operation called maximum mode, in which it allows parallel connection and operation of co-processors like 8087, 8089 and similar.

Figure 2.1: Physical Pin Diagram

56 2.1(b)
i. iv. vii. ix.

Chapter - 2

Pin Classification
Address Bus (ABUS) ii. Data Bus (DBUS) Utility Lines v. CPU Control Lines Bus Request Line (DMA Line) viii. ALE Line Inter-processor Communication Line iii. vi. Control Bus (CBUS) Interrupt Request Lines

Depending on the similarities of functions, the 40-pins of the minimum mode 8086 (MIN8086) are classified into the following eight groups:

2.1 (c)

Bus Structured Pin Diagram

The physical pin diagram of Fig-2.1 of the 8086 does not reveal much technical information about the functional properties of the pins. There is an alternative representation known as Bus Structured Diagram, which carries the functional meaning of these pins at a glance. In a busstructured diagram (Fig-2.2 , 2.3), the pins with similar functions are grouped together
1200ab : GM : 12-2007

MIN8086

CPU Control Lines (7)

MN-MX/ READY RESET CLK Vcc GND GND NMI INTR INTA/

DEN/ DT R/ S7 S3 BHE/ M-IO/ WR/ RD/ ALE D15 D8 D7 D0 A 19 - A00 8 8 20 5

Utility Lines ( 2)

Status Lines (5)

CBUS (4)

Interrupt Request Lines(3)

(1)

Direct Memory Access Line (2)

HOLD HLDA

DBUS (16)

Inter processor Communication Line (1) -

TEST/

ABUS (20)

Figure-2.2: Simplified Bus-structured Diagram for the Minimum Mode 8086

Figure 2.3: Bus Structured Diagram of Minimum Mode 8086 showing Multiplexed Pin Functions

Pin Electrical Characteristics

57

In Fig-2.2, we find that the 8086 microprocessor is equipped with varieties of signals to accomplish data read/write operations with memory and port devices. There are about 61 different signals, which are activated using only 40 pins instead of 61 pins. In fact, the functions of all these 61 signals can be carried out using only 40-pins and we see it in Fig-2.3. The reduction of pin counts from 61 to 40 has been made possible by allowing one pin to share two signals on time multiplex. It is possible to do time multiplex those two signals, which do not occur at the same time. Why are there so many signals for the 8086? They are needed and the justification in favor of this answer would be gradually revealed to us as we move through the pages of this book. We will see in Section-2.2 (a) and (b), the mechanism of transforming Fig-2.2 into Fig-2.3 by applying time multiplexing concept to those signals, which do not occur at the same time.

2.1 (d) Pin Electrical Characteristics

To build a system, the pins of the 8086 are connected with the pins of the external CLK chip, RAM, ROM, Buffer, latch and decoders [Fig-2.63, 2.65]. While making such connections, it is necessary to take into account the permissible number of fanout/fanin of the pins. The fanout/fanin consideration prevents the pins from delivering and sinking overloads. Every pin of the 8086 is characterized with the following features, which are very important factors to study from the viewpoint of system design. i. A pin has a serial number with respect to the notch mark. For example: The pin-29. ii. There is a signal associated with a pin. For example: The signal name of pin-29 is WR/. iii. The signal, which is associated with a pin, has a meaning. For example: The signal WR/ associated with pin-29 has the meaning of Write Enable. iv. The signal that is associated with a pin has a definition. For example: The WR/ signal of pin-29 has the following definition: The 8086 assert a Logic-L signal at this pin to tell the selected storage location to accept data from the data bus. v. A pin has some electrical characteristics with regards to voltage and current ratings: For example: The pin-29 of the 8086 has the following characteristics: a. VOH (2.4V) : Minimum output voltage that the pin will hold when it assumes LH state and delivers 400A. b. VOL (0.45V) : Maximum output voltage that the pin will hold when it assumes LL state and sinks 2.5mA. c. IOH (400A) : Maximum current that the pin will deliver while maintaining LH state at 2.4V. d. IOL (2.5mA) : Maximum current that the pin will sink while maintaining LL state at 0.45V. e. VIL (0.8V) : Maximum input voltage, which the pin will reliably recognize as LL. f. VIH (2V) : Minimum input voltage, which the pin will reliably recognize as LH.

58 2.1 (e) Brief Functions of the 8086 Pin Signals

Chapter - 2

In a microprocessor-based system, the MPU is the master and the memory/port devices are the slaves. All data transfer operations are seen with respect to the master, the MPU. An outgoing flow/arrow line indicates that the CPU is sending a signal over this line to the destination. An incoming flow/arrow line indicates that the CPU is receiving signal from external devices.
Signals Category Address Bus (20) Data Bus (16) Signal Names A19 A0 D7 D0 D15 D8 Direction Output In/Out Functions - To select one memory location out of 220 locations - To select one port location out of 216 locations - To convey 8-bit data between CPU and the Even Banks of Memory and Port - To convey 8-bit data between CPU and the Odd Banks of Memory and Ports - The CPU sends data read command signal to the selected memory or port device. - The CPU sends data write command signal to the selected memory or port device. - The CPU sends selection bit to select either a memory or a port device. - The CPU sends selection bit to select ODD bank (upper bank) of storage device. - LH configures 8086 to operate in Minimum Mode. LL configures 8086 to operate in Maximum Mode. - LH tells the CPU to come out of cycle stretching. - LH keeps the CPU in the reset state. Transition from LH to LL initiates the start of the CPU. - Pulse train for the operating frequency of the CPU. - +5V Power supply for the CPU. - To sink the source current by two ground pins. - To receive nonmaskable external interrupt signal. - To receive maskable (deniable) external interrupt. - To send acknowledgment signal to the external interrupting device. - A request by an external device to use the CPU BUS for Direct Memory Access (direct data transfer bypassing the CPU). - To send acknowledgment signal to the BUS requesting device. - To establish communication with coprocessor (8087, 8089) during maximum mode operation. - Emits various status signals of the CPU during program execution. - To enable external data buffer for D15 D0 lines. - To change the direction of the data buffer either as data transmitter or data receiver. - A pulse signal appears only once during a machine cycle to latch the Address and BHE/ signals from the multiplexed A19/S6 A16/S3, AD15 AD0 and BHE/S7 signals.

Control Bus (4)

RD/ WR/ M-IO/ BHE/

Out Out Out Out Input Input Input Input Input Input Input Input Output Input

CPU Control Lines (7)

MN-MX/ READY RESET CLK Vcc GND (2) NMI INTR INTA/ HOLD

Interrupt Request Lines (3)

DMA Lines (2)

HLDA Inter Processor Comm Line (1) Status Lines (5) Utility Lines (2) TEST/ S7 S0 DEN/ DT-R/ ALE

Output Input Output Output Output Output

Address Latch Enable Line (1)

Bus Timing Diagram of the 8086 Microprocessor

59

2.1.F1 Introduction We, the human beings establish communication with our surroundings using different types of signals. To communicate with another human being, we use verbal language. To communicate with a pet animal, we use sign language. To communicate with a PC, we use a keyboard. And to communicate with a television, we use a remote controller. We send signals to the surroundings and also receive responses from them. To ensure that the exchange of information between these two agents (the transmitter and the receiver) takes place properly, a Timing Relationship is necessary as to: i. When sending the signal, ii. How long to wait to allow the receiver digesting the received signal, iii. When to get ready to listen to the response. Likewise, around a microprocessor chip, there are memory and IO controllers. In order to exchange data with these devices, the CPU establishes communication by asserting electrical signals (called Bus Signals) on its address, data and control busses. The bus signals [Fig-2.4] are automatically generated when the CPU executes a data transfer instruction. To ensure correct and reliable data transfer between the CPU, the memory and the peripheral controllers, the relative timing offsets among the various components of the bus signals should be strictly maintained. A Bus Timing Diagram is a graphical presentation of the various timing functions that appear on the CPU pins during data exchange with memory and IO controllers. The basic bus-timing diagram of the minimum mode 8086 microprocessors is presented in Fig-2.4.
600:GM:03-04 T1 CK M-IO/ ADDR STS ALE DATA ADDR RD/ INTA/ READY DT-R/ DEN/ WR/ Mem ory Access Tim e WAIT READY WAIT READY FLOAT A15-A0 DATA IN (D15-D0) BHE/ A19-A16 S7 - S3 BHE/ A19-A16 S7 - S3 T2 (4+Nwait) = Tcy T3 Twait T4 T1 T2 (4+Nwait) = Tcy T3 Twait T4

2.1 (f)

Bus Timing Diagram of the 8086 Microprocessor

A15-A0

DATA OUT (D15-D0)

Figure-2.4: Bus Timing Diagram of the Minimum Mode 8086 Microprocessor

60

Chapter - 2

2.1.F2 Use of a Bus Timing Diagram Every microprocessor has its own Bus Timing Diagram, which is prepared by the chip designers. The timing diagram describes the terminal properties of the microprocessor chip. It provides information as to the time instant at which a particular timing function occurs or should occur. The timing diagram allows a system designer to build a reliable system by careful discrimination of the memory/port devices, which might have mismatch timing functions with CPU. For example: The 8086 systems (MicroTalk-8086) running at 2.048MHz [Fig-2.6(a), 2.63] expects that the selected memory chip should put data on the data bus within 500nS after the occurrence of the falling edge of the RD/ signal. Therefore, a memory device with an access time larger than 500nS will not work in this system. The bus-timing diagram plays an important role in the design/development house to trouble shoot prototyped or newly built systems. The maintenance people take the help of the timing diagram to repair/adjust malfunctioning systems. 2.1.F3 Few Definitions relating to Bus Timing Diagram To have clear understanding on the timing relationships of the various bus signals of the diagram of Fig-2.4, it is necessary to remain familiar with the definitions of the following terms: T-State or Clock Cycle: In the study of digital electronics including the microprocessor, the term Cycle is always a measure of Time. A T-state (T) or a Clock Cycle is the duration of one clock of the operating frequency. In Fig-2.4, which is for the 8086, we see that the Clock Cycle is a measure of time between two falling edges of the operating frequency. Let us designate the clock cycle period by the symbol T. Machine Cycle: A Machine Cycle refers to the amount of time in terms of T-states, which is required to complete one data read or write operation. The Fig-2.4 indicates that the duration of a machine cycle is about four T-states without the wait states. The machine cycle may be represented by the symbol: Tcy (T Cycle). Bus Cycle or Instruction Cycle: A Bus Cycle refers to the amount of time that is required to complete the execution of an instruction. 2.1.F4 Study of the Timing Relationships of the Bus Timing Diagram The bus-timing diagram of Fig-2.4 describes the relative timing positions of the address, data, control and other signals that appear on the pins of the CPU. In this subsection, we study the timing instants of the various pin signals in accordance with the data sheets of the 8086. To read a data byte from an external memory location, the following events occur in the order indicated: i. The falling edge of T1 is the time reference ii. The M-IO/ signal assumes Logic-H state at time: 10nS. The cross over point on the M-IO/ signal is an indication that the signal is assuming a different value from the previous one. iii. The ALE signal assumes Logic-H state at time: 80nS iv. The BHE/ signal assumes Logic-H state at time: 110nS. At the same time, the upper 4-bit address line (A19-A16) and the lower 16-bit address line (A15-A00) of the address bus assume the relevant logic values.

Bus Timing Diagram of the 8086 Microprocessor

61

v. vi.

vii.

viii. ix. x. xi. xii. xiii.

If the 20-bit address of the desired memory location is C1002h, then the CPU will assert a bit pattern of 1100 on the A19-A16 pins and a bit pattern of 0001 0000 0000 0010 on the A15-A00 pins. There is a passage of time that allows the bus signals to arrive at their stable states. The ALE signal works as a triggering signal and it transfers the BHE/, A19-A16 and A15-A00 signals at the output of the auxiliary latches [Fig-2.63, U6-U8] within a period of (T+250) nS. The ALE signal is also deactivated at the same time. At time (T+40) nS, the following events occur on the bus: a. The BHE/-pin transmits status signal S7. b. The A19-A16 pins transmit status signals S6, S5, S4 and S3. c. The A15-A00 pins enter into float state (3-state). Preparation is initiated to read data from the selected memory chip. The RD/ signal assumes Logic-L state at time (T+165) nS. The DEN/ Signal assumes Logic-L state at time (3T+40) nS. The A15-A00 pins change from float into input data bus at time (4T-205) nS. The data enters into the CPU within the time of 40nS. At the same time, the DEN/ signal is deactivated at (5T/2 + 110) nS The RD/ signal deactivates at time (5T/2 + 150) nS.

Example-2.1 Refer to Fig-2.6 (a) and find that the base frequency for the crystal, Y1 is: 6.144 MHz. The
diagram also indicates that the operating frequency of the 8086 microprocessors is 1/3rd of 6.144. Therefore the duration of clock cycle (T-State) = 1/(2.048MHz) 488nS. Now, fill up the following table showing the numeric values for the timings of the bus signals of Fig-2.4. Sno 1 2 3 4 5 6 Table 2.1 Timing Function Time Reference Start of M-IO/ Signal Start of ALE Signal Common Start of the Following Signals: BHE/, A19-A16, A15-A00 Time allocation for the BHE/, A19-A16, A15-A00 signals to reach to the output of the auxiliary latch Common Start of the following Signals: BHE/-pin Emits S7 Signal A19-A16 Emit S4-S3 Signals A15-A00 Signals enters into Float Start of the RD/ Signal Start of DEN/ Signal at Turning of the A15-A00 Signals into Data Bus at Time allocation for the data to enter into the CPU register The DEN/ signal deactivates at The RD/ Signal deactivates at Symbolic Value (T/2+50) T+40 Numeric Value 0 nS 10 Ns 80 nS 110 nS 294 nS 528 nS

7 8 9 10 11

110 2T 4T-35

440 nS 976 nS 40 nS 610 nS 1917 nS

62 2.1 (g) Detailed Functions of the 8086 Pin Signals

Memory /Port and these are: i. ii. iii. iv.

Chapter - 2

Read/Write Control Bus (4 Lines): There are four outgoing lines in this category Read Control Line: RD/ (/ indicates active Low) Write Control Line: WR/ Memory/Port Differentiating Line: M-IO/ Memory Bank Selection Line: BHE/

Read Control Line (RD/): This is an outgoing line and is terminated with the memory and port devices. It carries active low signal to inform the selected memory/port location to put data on the data bus. The RD/ signal is automatically generated when the CPU executes a data read instruction [Fig-2.4]. The timing relationship of the RD/ signal is depicted in Fig-2.4. Write Control Line (WR/ ): This is an outgoing signal and it carries active low signal to command the selected memory/port location to absorb data from the data bus. The WR/ signal is automatically generated when the CPU executes a data write instruction [Fig-2.4]. Fig-2.4 contains the timing relationship of the WR/ signal. Memory/Port Differentiating Signal (M-IO/): The CPU has separate RD/ and WR/ signals to differentiate a read operation from that of a write operation. Similarly, it has a M-IO/ control signal to distinguish the selection of a memory chip from that of the IO chip. The M-IO/ pin automatically asserts LH signal when the CPU executes a memory-referenced instruction. It emits LL signal during the execution of an IO-referenced instruction. Memory Bank Selection Line (BHE/ :Byte High Enable): This is an outgoing signal and is multiplexed with the status signal, S7. The BHE/ signal selects the ODD bank of the memory/port devices. The BHE/ signal goes to the memory/port decoder, where it is conditioned to generate the enable signals for the ODD memory/port banks. Thus, we see that the BHE/ pin of the CPU carries Logic-L signal during the execution of read/write instructions, which involve: i. Word (two byte) data operation starting from Even-numbered address. ii. Byte data operation from ODD-numbered memory address. Processor Control Lines: The following six lines are accommodated under this category. These control lines, directly or indirectly regulate the operation of the 8086 microprocessor.
i. ii. iii. iv. v. vi. RESET (CPU Reset) MN-MX/ (Minimum Mode or Maximum Mode) READY CLK (CPU Clock) Vcc Supply (+5V Supply) GND Supply (0V Sink)

RESET Line: It is an input line and carries a positive pulse to the CPU. The minimum requirement for the width of this pulse is at least four clock periods. The reset pulse is generated by a R-C circuit and is conditioned by an auxiliary clock chip [Fig-2.6 (a)] before it arrives at the

Detailed Functions of the 8086 Pin Signals

63

RESET pin of the CPU. The conditioning involves synchronizing [Fig-2.6 (b)] the RESET pulse with the processor clock, which is necessary for the proper reset and initialization of the internal circuitry of the microprocessor. At the rising edge of the reset pulse, the CPU terminates all operations. It will remain Idle for the duration of the pulse. During the falling edge of the reset pulse, the CPU begins an internal reset sequence, which lasts for about 10 clock periods. During the reset sequence, the following registers assume the values as indicated. The contents of other registers remain unknown.
Data Segment Register is initialized to 0000h Stack Segment Register is initialized to 0000h Extra Segment Register is initialized to 0000h Code Segment Register is initialized to FFFFh Instruction Pointer Register is initialized to 00000h Flag Register is initialized to 0000h DSR = 0000Hh SSR = 0000h ESR = 0000h CSR = FFFFH IPR = 0000H FR = 0000H

MN-MIX/ (MiNimum Mode or MaXimum Mode): In minimum mode operation, the 8086 do not allow the parallel connection and operation of co-processor chips like 8087 and 8089 but in maximum mode it does allow. The meanings of the pin signals of the 8086 CPU are sufficiently different when it operates in maximum mode. The pin diagram of the maximum mode 8086 is depicted in Fig-2.5 below. The 8086, using its 40 pins, cannot furnish all the functions required by maximum mode operation. To keep the number of pins at minimum while achieving the multiprocessing performance, a jumper pin (pin-33) has been added to the CPU to select the mode of operation. When MN-MX/ pin is strapped to +5V, the 8086 assert signals at its various pins as required by the minimum mode operation [Fig-2.2]. When the jumper pin is connected to ground potential, the 8086 assert maximum mode signals as per definitions of the pins of Fig-2.5.
8086
280 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

GND AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 NMI INTR CLK GND

Vcc AD15 A16-S3 A17-S4 A18-S5 A19-S6 BHE/-S7 MN-MX/ RD/ RQ/-GT0/ RQ/-GT1/ LOCK/ S2/ S1/ S0/ QS0 QS1 TEST/ RDY RST

Figure-2.5: Physical Pin Diagram for Maximum Mode 8086

64

Chapter - 2

READY Signal: This is an input signal to the processor. The CPU functions normally as long as the logic level at this pin remains high. When the logic level of this pin goes low, the CPU starts inserting WAIT States in its operating clock [Fig-2.4]. It means that the clock period begins stretching and all bus activities become frozen. The bus activities resume when the pin logic is restored to Logic-H state. The inclusion of the RDY pin in the architecture of 8086 has allowed the utilization of the slow memory devices in the system design. The slow memories are characterized with low cost and higher access time (greater than 200nS). There are commercial systems requiring huge on-board memories with moderate demand in speed. The RDY line is connected with the controller of the slow memory module. After the reception of the address-data-read signals from the buses, slow memory controller pulls down the RDY line. When the data becomes available from the slow memory, the controller asserts Logic-H on the RDY pin. The RDY signal requires synchronization with the processor clock and is done with the help of the clock generator chip [Fig-2.6(b)]. CLK:The CLK signal is the Heart for the 8086 microprocessor. It is the source for all kinds of complex timing functions that are generated with the processor. There is a dedicated clock chip (the 8284) that produces a 33% duty-cycle clock signal for the 8086. The choice of 33% duty-cycle is a compromise for the optimum operation of the 8086. The schematic diagram for the clock circuit is depicted in Fig-2.6 (a). The conceptual block diagram for the 8284 chips is depicted in Fig-2.6 (b).
653b +5 Rx 5k R1 5k 4 11 R ST / + 13 3 7 1 6 9 18 Y1=6.144MHz 16 X2 CLK 08 =1/3Y1 RST 10 READY 5 OSC 12 =Y1 PCLK 02= 1/6Y1 17
RES/ CLK RESET 653b

Vcc X1

RDY RST/ F-C/ AEN1/ AEN2/ CSYNC RDY2 GND

X1 X2 RDY1 Oscillator CLK

OSC RDY

Cx 100 uF

8284

/3

CLK

Figure-2.6 (a): Schematic of 8284 Clock Circuit

Figure-2.6 (b): Conceptual Block Diagram of 8284

+5V Supply: +5V supply is the source for the electrical power of the 8086 microprocessor. The tolerance of the +5V supply is: 5V10% for the 8086 and 55% for the 8086-1/8086-2. At room temperature, the 8086 chips can draw as much as 340mA current from the +5V supply. 0V Supply: There are two pins (1, 20) in the architecture of the 8086 to sink the source current in two parallel paths and thus minimizes the noise.

Detailed Functions of the 8086 Pin Signals

65

Utility Lines: The author proposes the class name Utility Lines to include the following signals: i. ii. iii. DEN/ DT-R/ S3 S7 (Data Buffer Enable Signal) (Data Buffer Direction: Transmit or Receive) (CPU Status Signals)

DEN/ (Data Buffer Enable) Line, DT-R/ Line: Due to the limited current driving capability of the data bus of the 8086 microprocessor, it is highly recommended that we use bi-directional data buffers similar to 74LS245 with the data lines of the CPU [Fig-2.63, U4-U5]. In Fig-2.7, we have presented the detailed structure of the 74LS245 data buffer. While the CPU does not execute any read/write instructions, the data buffer should remain OFF (3-state condition). The 8086 generate the DEN/ signal to accomplish this purpose. The DEN/ is an outgoing line and carries Logic-L signal to disable the 74LS245. DT-R/ (Data Transmit and Receive): The direction of data transfer is always with respect to the CPU. Thus, during the execution of a data write instruction, the direction of the data buffer of Fig-2.7 should be such that it forwards data toward the memory/port devices. During data read operation, the direction should be reversed. To ensure that the direction of the data buffer of Fig-2.7 changes dynamically during the execution of read/write instructions, the 8086 automatically assert appropriate signals on the DTR/ line. The DT-R/ is an outgoing line, which is terminated with the DIR-pin of the data buffer. It carries Logic-H signal during the execution of write instructions and Logic-L signal during read operation.
8086 CPU
A DEN/ DT-R / 26 27 19 1 EN/ DIR A

74LS245

Memory

Rx D7 D6 D5 D4 D3 D2 D1 D0 9 8 7 6 5 4 3 2 D7 D6 D5 D4 D3 D2 D1 D0

B Read Path: (DT-R/ = LL) Write Path : (DT-R/ = LH) Tx D7 D6 D5 D4 D3 D2 D1 D0 11 12 13 14 15 16 17 18 D7 D6 D5 D4 D3 D2 D1 D0

GM : 601: 03-04

Figure-2.7: Connection of 74lS245 data Buffer in the 8086 System

66

Chapter - 2

Operation: During data read operation, the Rx gate of the 74LS245 must be ON and the Tx gate must be OFF. It is ensured this way. While the CPU executes a read instruction, it expects to receive data from the bus. So, the CPU activates the DT-R/ and DEN/ signals to LL states. The LL value of DT-R/ signal disables Tx gate while the ANDing of DEN. (Data Buffer Enable) and DT-R/ enables Rx. The CPU easily receives the data from the data bus. Similarly, during data write cycle, the CPU asserts LH at DT-R/-pin and LL at DEN/-pin. These signals are ANDed within the 74LS245 to generate gating signals, which accurately enables the Tx gate and disables the Rx gate.
Table 2.2 Truth Table of 74LS 245 Data Buffer Bus Activities Status of 74LS245 RD/ WR/ DEN/ DT-R/ ANDA ANDB 0 1 0 0 ON OFF 1 0 0 1 OFF ON 1 1 1 1 OFF OFF

Instruction mov al, BYTE PTR [bx] mov BYTE PTR [bx], al mov al, ah

Operation Rx On OFF OFF Tx OFF ON OFF Data Read Data Write Buffer is OFF

Processor Status Lines: S3, S4, S5, S6 and S7 Lines: The timing diagram of Fig-2.4 indicates that after the occurrence of the address event, the 8086 uses the upper 4-bit address lines (A19-A16) to emit the status signals: S3, S4, S5, S6. The CPU uses the BHE/ line to emit the signal: S7. To catch the values of these status signals, suitable electronic circuitry are to be employed. The bit pattern and the meaning of these signals are given below in Table-2.3 [1].
Table-2.3 Status Signals S4 S3 1 1 1 0 Meaning The memory reference instructions are using Data Segment for read/write operations during the execution of the current instruction The memory reference instructions are using Code Segment for read/ write operations during the execution of the current instruction. Or The CPU is accessing the Interrupt Vector Table for jumping to Interrupt Sub Routine in response to an Interrupt. The memory reference instructions are using Stack Segment for data accessing. The memory reference instructions are using Extra (alternate) Segment for read/write operations during the execution of the current instruction. The IF-bit of the flag register is set. Always Spare

0 0 S5 = 1 S6 = 0 S7 = ?

1 0

Interrupt Control Lines: The following three lines have been accommodated in this group: i. NMI (Non-Maskable Interrupt Request) Line ii. INTR (Maskable Interrupt Request) Line iii. INTA/ (Interrupt Acknowledge) Line

Detailed Functions of the 8086 Pin Signals

67

NMI (Non-Maskable Interrupt) Line: This is an input line, which is always ready to receive an interrupt request signal (IRQ) from an external device. When a Logic-H signal arrives at this pin, the 8086 is immediately interrupted. The CPU suspends the current program and jumps to Interrupt Sub Routine (ISR). Having finished the ISR, the CPU resumes the suspended program. Here we observe that the CPU could not deny the Interrupt Request Signal that it has received over its NMI-pin. The bureaucratic word nonmaskable stands for the meaning of: Cannot be denied. The word maskable stands for the meaning of: Can be denied. In Chapter-5, we will carry out detailed study on the configuration, operation and management of the Interrupt Structure of the 8086 microprocessor. INTR (Maskable Interrupt Request) Line: This is also an interrupt request line. An external device can interrupt the CPU by asserting a Logic-H signal on this pin. The CPU has the choice to honor or deny the IRQ signal that arrives at its INTR-pin. The INTR is a maskable interrupt and can be enabled/disabled using software instructions. INTA/ (Interrupt Acknowledge) Line: This is an outgoing line and carries a negative going pulse (called INTA pulse) to the external interrupting device, which has placed an IRQ signal on the INTR pin of the CPU. The purpose of the INTA signal is to tell the interrupting device to put a pre-defined 8-bit code (called Interrupt Type Code, ITC) on the D7-D0 bus. The CPU receives the ITC code and uses it to compute the beginning address of the ISR. The INTA/-pin requires pullup a termination to +5V supply by a 5K resistor [Fig-2.63, P139]. DMA Control Lines: HOLD Line: This is an input line to the CPU, which has originated from an external device called DMA (Direct Memory Access) device. The Logic-H value of this signal informs the CPU that the DMA device wishes to use the system bus for direct data transfer. HLDA (Hold Acknowledge): The HLDA pin of the 8086 is an outgoing line and is terminated with a DMA device. It carries a Logic-H signal in response to the HOLD signal and informs the DMA device that the system bus is released and now it can be used for direct data transfer. Interprocessor Communication Line: TEST/ Line: This is an input line to the CPU, which originates from a FPU (Floating Point Unit) chip like 8087 [Fig-2.62]. The FPU asserts this pin low to inform the 8086 that it has finished its own computational tasks and now the CPU can continue executing its own instructions.

2.2 (a) Time Multiplexing of 8086 Pin Signals

Multiplex of A15 A0 Signals with D15 D0 Signals: In Chapter-1, we learnt that the process of reading a data byte from a memory location involves: Firstly, putting the address signals on the ABUS; Secondly, sending the RD/ signal over the CBUS and Thirdly, absorption of the data from the DBUS. Here, we clearly see that the address and data signals do not occur at the same time. So, we can comfortably use 16-pins to share A15 A0 and D15 D0 signals. This sharing has been indicated in Fig-2.3 as AD15, AD14, , AD0. The AD15 signal actually stands for A15D15. The association of AD15 signal with pin-39 indicates that the said pin first carries the A15 signal and then it turns into a data line to convey the data signal D15. Now, there is a reduction of 16 pins and the pin counts has come down to 45.

68

Chapter - 2

Multiplex of A19 A16 Signals with S6 S3 Signals: S6 S0 are the status signals, which the 8086 emits as per Table-2.4 after the execution of an instruction to exhibit the internal states of the CPU. Thus, it is clear that the status signals occur much later than the address signals. So, the A19 A16 signals and the S6 S3 signals can easily share 4 pins. These are shown as A19/S6, , A16/S3 in the diagram of Fig-2.3. Now, we have another reduction of 4 pins and the pin counts has come down to 41. Multiplex of BHE/ Signals with S7 Signal: The CPU activates the BHE/ (Byte High Enable) signal to enable the ODD bank of the memory or the port devices and it occurs along with the occurrence of the address signals. Thus, we see that the S7 signal occurs much later than the BHE/ signal. So, it is possible that we share a single pin for both the BHE/ and S7 signals and is indicated as BHE/-S7 in Fig-2.3. Now, we have a 3rd reduction in the pins and the net pin counts has arrived at 40.

2.2 (b) Multiplexed Address/Data Bus Operation

Introduction: We have seen in the previous studies that the A15 A00 and D15 D00 signals share common pins on time multiplexing. At the beginning of the bus cycle, the A15 A00 signals appear first on the shared pins.
8086 Microprocessor
R D /, W R / Generato r A19 - A16 A15 - A0 SW 1
delay

Memory
R D /, W R / A19 - A16 D Flip-flop AD 15-AD 0 TL ALE In O ut CK Aux. Latch D 15-D 0 D 15-D 0 598 A15 - A0

1 A15-A0 D 15-D 0

D 15-D 0 al R egister ALE G EN ER ATO R

Figure-2.8: Multiplexed Address/Data Bus Operation of the 8086 Microprocessor

We know that these are the address signals, which must remain stable at the input terminals of the selected memory/port device for the whole duration of the machine cycle until the data transfer is complete. But, we also know from the timing diagram of Fig-2.4 that the shared pins should turn into the data bus somewhere in the middle of bus cycle. Under this circumstance, we have to find a way similar to the circuit of Fig-2.8 to grasp the address bits from the shared pins and hold them at the output of an auxiliary latch. Now is the appropriate moment to understand the role of the ALE signal. The ALE pin carries a positive pulse at the beginning of every machine cycle [Fig-2.4] to trigger the auxiliary latch of Fig-2.8 for accepting/holding the address bits emitted by the CPU.

Multiplexed Address/Data Bus Operation

69

Working Principles of Circuit of Fig-2.8: We know that the CPU, at first uses the address lines to select a memory location. And then, it issues the RD/ or WR/ signal to accomplish data transfer. Thus, the two events Address Assertion and Data Flow do not occur at the same time. So, it is possible to use only 16 pins of the 8086 CPU to carry both the 16-bit address (A15 A00) and the 16-bit data (D15 D00) on time multiplex basis. The working principles: (i) At the beginning of address assertion, the wiper of SW1 is at position-1 within the CPU. The upper 4-bit address (A19 A16) directly goes to the memory chip. The lower 16-bit address (A15 A00) is available to the input of the D-flip flop over the common TL (Transmission Line). (ii) As we know that the address information must remain stable to the input of the memory until the read or write pulse goes to it. Therefore, it is required that the A15 A00 must be transferred to the output of the D-flip flop. To accomplish this task, the CPU generates the ALE (Address Latch Enable) pulse [Fig-2.4]. When the ALE goes to Logic-L, the output of the D-flip flop gets isolated from its input. The lower 16-bit address remains stable to the input of the memory chip. (iii) After some time delay, the ALE pulse transfers the wiper of SWI to position-2. Now, the TL line is ready to carry 16-bit data. (iv) The CPU sends (if it is read operation) the RD/ signal to the memory chip. The 16-bit data of the memory location travels to the CPU over the TL line. (v) Thus we see that the common TL line can carry both the address and data signals without any conflict. So, it may also be represented by the symbol AD15-AD00 meaning that the TL line is carrying the time-multiplexed signals, A15 A00 and D15-D00. (vi) In practice, there would be required 16 nos D-flip flop to implement the auxiliary latch. The IC, 7LS373 are an octal latch, two units of which could be used to latch the 16-bit address and keep them at the input of the memory devices [Fig-2.63, U7-U8]. In Fig-2.9, we have presented the detailed of 1-bit structure of the 74LS373.
OE/

In

Out

ALE

CK

muxAD7

Figure-2.9: 1-Bit Structure of the 74LS373 Latch

2.2 (c) Functional Relationship among RD/, WR/, M-IO/, BHE/, and A0 Signals
The 8086 have the capability of reading (writing) 8-bit data from a single location of the even bank of memory or even bank of port. It can also read (write) 8-bit data from a single location of the odd bank of memory or odd bank of port. The 8086 can also read (write) 16-bit (2 Bytes) data from two consecutive memory locations or from two consecutive port locations starting from even bank. The CPU can also read (write) 16-bit (2 Bytes) data from two consecutive memory locations or from two consecutive port locations starting from odd bank. However, while reading (writing) 16-bit data starting from odd bank, the CPU takes double time compare to reading (writing) 16-bit data starting from even bank. All these read (write) operations are controlled by the timely occurrence of the A0, BHE/, M-IO/, RD/ and WR/ signals. The functional relationship of these signals is documented below in Fig-2.10.

70
Sn. 1 2 3 RD/ 0 0 0 WR/ 1 1 1 Signals M-IO/ BHE/ 1 1 1 1 0 0 Table 2.4 Function A0 0 1 0 Read 8-bit data from EVN bank of memory via D7 D0 Read 8-bit data from ODD bank of memory via D15 D8 Read 16-bit data from both bank of memory starting even bank via D15 D0 Write 8-bit data into EVN bank of memory via D7 D0 Write 8-bit data into ODD bank of memory via D15 D8 Write 16-bit data into both bank of memory starting even bank via D15 D0 Read 8-bit data from EVN bank of port via D7 D0 Read 8-bit data from ODD bank of port via D15 D8 Read 16-bit data from both bank of port starting from bank via D15 D0 Write 8-bit data into EVN bank of port via D7 D0 Write 8-bit data into ODD Bank of port via D15 D8 Write 16-bit data to both bank of port starting from bank via D15 D0 mov mov mov mov from

Chapter - 2

Assembly Codes bx, 3010h al, BYTE PTR ds:[bx] bx, 3011h al, BYTE PTR ds:[bx]

4 5 6

1 1 1

0 0 0

1 1 1

1 0 0

0 1 0

mov bx, 3010h mov ax, WORD PTR ds:[bx] mov bx, 3010h mov BYTE PTR ds:[bx], al mov bx, 3011h mov BYTE PTR ds:[bx], al mov bx, 3010h mov WORD PTR ds:[bx], ax mov dx, 3010h in al, dx mov dx, 3011h in al, dx mov in mov out mov out mov out dx, 3010h ax, dx dx, 3010h dx, al dx, 3011h al, dx dx, 3010h ax, dx

from

7 8 9

0 0 0

1 1 1

0 0 0

1 0 0

0 1 0

even

10 11 12

1 1 1

0 0 1

0 0 0

1 0 0

0 1 0

even

Figure-2.10: Functional Relationship of RD/, WR/, M-IO/, BHE/ and A0, Signals

2.2 (d) Bus Activities

The CPU, while performing data read/write operations with the memory and port devices, it mainly uses the following buses: i. Address Bus containing 20 Lines (A19 A00) ii. Data Bus containing 16 Lines (D15 D00), which are time Multiplexed with A15-A0 iii. Control Bus containing 4 Lines (RD/, WR/, M-IO/, BHE/) A bus becomes active when it assumes a set of new logic values for the signals that are present in the bus and it happens during the execution of memory/port reference instruction. In other words, a bus becomes active when there is a continuous change in the logic values of its signals. There are 20 lines in the address bus of the 8086 microprocessor, which are designated as A19-A00. The Logic-H or the Logic-L states of the bus signals are their Logic Values. Let us see what new logic value that the buse would assume during the execution of the following instruction:
08000 mov bx, 0002h : BB 02 00

08003 During the 1st machine cycle, the CPU would read the opcode (BB) from the memory location 08000h. Therefore, it must assert:

Memory Organization of the 8086 System i. ii. iii. The bit pattern of 0000 1000 0000 0000 0000 (08000) on the address bus. The bit pattern of 0111 on the control bus for RD/, WR/, M-IO and BHE/. The bit pattern of 10111011 (BB) on the D7 D0 lines of the data bus.

71

During the 2nd machine cycle, the CPU would read the 2nd instruction byte (02) from the memory location 08001h and accordingly it has to assert: i. The bit pattern of 0000 1000 0000 0000 0001 (08001) on the address bus. ii. The bit pattern of 0110 on the control bus (code byte read from ODD bank). iii. The bit pattern of 00000010 (02) on the data bus. Thus, we see that there appears a new value in the states of the signals of the address, data and control buses of the CPU. Such change in the logic values occurs only during the execution of an instruction. The bus activities are not observed under the following situations: i. If the CPU has executed the HLT instruction ii. If the peripheral device has deactivated the READY signal (cycle stretching) iii. If the peripheral device (DMA Controller) has taken over the bus control.

2.3 (a) Memory Organization of the 8086 System

2.3.A1 Introduction With the help of 20 address lines (A19 A00), the 2 8086 can access 220 (1048576) of contiguous external memory locations that include ROM and RAM and memory-mapped ports. Because each location contains 8-bit (1 Byte) data, we say that the 8086 can access 1048576 bytes memory space. Considering 1024 bytes as 1K and 1024 K as 1M, we state that the 8086 have the capability of addressing 1024 Kbytes (1048576/1024) or 1 Mbytes external memory space. The 20-bit address of the beginning location is 00000h and that of the end location is FFFFFh. The total memory space of the 8086 system is depicted in Fig2.11 with many partitions, which the author recommends to adapt while designing an 8086 learning system similar to MicroTalk-8086 or building an 8086-based instruments or control circuits. In fact, the memory space of Fig-2.11 is the memory map of the MicroTalk-8086 Learning/Dev. System. In MicroTalk-8086, there are 64 Kbytes RAM space occupying the address range, 0000h 0FFFFh. The system has the ROM space occupying the address range, F0000h FFFFFh. The startup (Bootup or Powerup) location for the 8086 is: FFFF0h (FFFF:0000).

Figure-2.11: Memory Space of 8086 System

72

Chapter - 2

2.3.A2 EVEN Bank and ODD Bank Memory Arrangement of 8086 In an 8086 system, the memory locations (also the port locations) with even numbered addresses are stacked together and the resulting block is known as EVEN Bank. Similarly, the memory locations with odd numbered addresses are stacked together and the block is known as ODD Bank. In Fig-2.12, we see that the MEM (Memory Even Bank) contains all the even locations with addresses 00000h, 00002h, ., FFFFCh, FFFFEh. The MOB contains the locations with addresses 00001h, 00003h,.,FFFFDh, FFFFFh.

Figure-2.12: 8086 Memory Space organized as Even and Odd Banks

To simplify the study, we have assumed that the system of Fig-2.12 contains only two memory chips, U3 and U4. The U3 belongs to the even memory bank and contains half of the total addressable locations, which are 220/2 = 219 locations. The U4 belongs to odd memory bank and contains the other half (219) of the memory space, which is 220/2. Now, we find that only 19 address (A19 A1) lines are required to access the storage locations of the memory chips. The address line A0 is a good choice to connect it with the input of the memory decoder for selecting either the even or the odd memory bank. The data pins of U3 and U4 are physically connected with the D7 D0 and D15 D8 lines of the 8086 respectively. The SE/-pin and the SO/-pin refer to the chip select pins of the MEB and MOD respectively. The following truth table describes that the even and odd memory banks are correctly selected for data transfer in response to the logic values of M-IO/, BHE/ and A0 signals.
Signals M-IO/ BHE/ 1 1 1 0 1 0 0 X Table-2.5 Memory Decoder Selection U1 Output U2 Output Logic-H Logic-L EVN Bank Logic-L Logic-H ODD bank Logic-L Logic-L Both Bank Logic-H Logic-H None Operation 8-Bit data via D7-D0 bus 8-Bit data via D15-D08 bus 16-bit data via D15-D00 bus No data transfer with memory

A0 0 1 0 X

Memory Organization of the 8086 System 2.3.A3 Working Principles of the Memory Decoder (MDEC) of Fig-2.12

73

Selecting EVN Bank for Byte Data Operation: To handle an 8-bit data with the EVN-bank, the CPU must assert an even address on the address bus. For any even address, the A0-bit is always at LL. The BHE/-bit and the M-O/ signal automatically assume Logic-H states when the CPU executes a memory reference instruction like:
mov al, (00002h) ; meaning: the content of even location 00002h is copied to al-register.

The input bit pattern of the memory decoder of Fig-2.12 appears as: 110. As a result, all the output pins of the MDEC assume Logic-H states except the S6/. The Logic-L value of S6/ passes through the enabled gate U2 and then reaches to the chip select pin (SE/) of the EVN bank. Thus, we see that the MDEC has successfully selected the EVN memory bank for byte data operation. Selecting ODD Bank for Byte Operation: To handle an 8-bit data of the ODD bank, the CPU asserts an odd numbered address on the address bus with A0-bit at LH. The BHE/-bit and the M-O/ signal automatically assume LL and LH states respectively when the CPU executes a memory reference instruction like:
mov ah, (00003h) ; meaning: the content of odd location 00003h is copied to ah-register.

The input bit pattern of the MDEC of Fig-2.12 appears as: 101. As a result, all the output pins of the MDEC assume Logic-H states except the S5/. The Logic-L value of the S5/ signal passes through the enabled U1 and then reaches to the chip select pin (SO/) of the ODD bank. Thus, we find that the MDEC has successfully selected the ODD memory bank for byte data operation. Selecting Both Banks (EVN Bank and ODD Bank) for Word Data Operation: Assume that we wish to read two bytes data at a time from the memory locations, 00002h and 00003h of the memory system of Fig-2.12. This is a word operation in which the beginning address is aligned with an even numbered address. When the beginning address is aligned with an even address, the CPU takes only one machine cycle to complete the word data operation. The CPU asserts the beginning address on the address bus with A0-bit setting at Logic-L state. The BHE/-bit and the M-IO/ signal automatically assume Logic-L and Logic-H states respectively when the 8086 execute a memory instruction like:
mov ax, (00003h, 00002h) ; meaning: ; the content of even location 00002h is copied to al-register. ; the content of odd location 00003h is copied to ah-register

Now, the input bit pattern of the memory decoder of Fig-2.12 appears as: 100. As a result, all the output pins of the decoder assume Logic-H states except the pin-S4/, which assumes Logic-L state. The S4/ signal drives the inputs of the AND gates U1 and U2 and forces their outputs to assume Logic-L states. The outputs of the AND gates are connected with the chip select pins (SE/ and SO/) of both the memory banks. Thus, we see that the MDEC has simultaneously selected the EVN bank and the ODD bank for word data operation. Limitations of the Memory Decoder Circuit of Fig-2.12: The memory decoder circuit of Fig-2.12 is purposely made simple in order to understand the underlying principles of Decoding. A simple idea always works as a staircase to conceive the idea of a complex concept, which is necessary to solve a particular problem. AE has said that a wise man always begins with the simple one and then she gradually moves to the complex one.

74

Chapter - 2

The decoder of Fig-2.12 works on the assumption of the following hypothetical concepts:
i. ii. iii. iv. Full decoding scheme is employed. The EVN bank (ODD Bank) of memory is composed of a single chip and accommodates 512 Kbytes locations. The single memory chip U3 or U4 contains both RAM and ROM. The lower 256Kbyte occupies the RAM and the upper 256Kbyte occupies the ROM.

In practical systems such as MicroTalk-8086, we have used lower capacity memory chips likes as 27256 (32Kbyte ROM) and 62256 (32Kbyte RAM). Under this circumstance, the memory organization of the next version (Fig-2.13) of the diagram of Fig-2.12 would be based on:
i. ii. Two RAM chips will constitute the EVN bank and ODD bank for the total 64K RAM space of the system. They will occupy the space: 00000h 0FFFFhh Two ROM chips will constitute the EVN bank and ODD bank for the total 64K ROM space of the system. They will occupy the space: F0000h FFFFFh

The simple decoder of Fig-2.12 cannot accomplish the above-mentioned complex decoding task, which requires the selection of a particular memory chip (out of four) within its specified address range. There is a need of new decoder with some degree of sophistication. Let us study the design of this new but complex decoder in the next section.

2.3 (b)

2.3.B1 Introduction The four memory chip version of the diagram of Fig-2.12 is depicted below in Fig-2.13. This diagram is, in fact, the memory system of the MicroTalk-8086 trainer. The new decoder circuit is built based on partial decoding scheme. It is a Black Box, which performs the complex decoding task to select a particular memory location (port location) of a particular memory chip (port chip) within its specified address range. To understand how this decoder selects a particular storage location, let us draw its Truth Table.

Memory Decoding Scheme of a 4-Chip Based 8086 System

Figure-2.13: Memory Decoding Scheme of a 4-Chip based practical System

Memory Decoding Scheme of a 4-Chip Based 8086 System

75

2.3.B2 Truth Table for the Decoder of Fig-2.13 The decoder U1 of Fig-2.13 is designed using a 27256 ROM to provide the following decoded outputs:
i. Its D0-pin must assume LL state so that the EVN RAM bank is selected for the following even memory addresses asserted by the CPU. 00000, 00002, , 0FFFC, 0FFFE Its D1-pin must assume LL state so that the ODD RAM bank is selected for the following odd memory addresses asserted by the CPU. 00001, 00003, , 0FFFD, 0FFFF Its D2-pin must assume LL state so that the EVN ROM bank is selected for the following even memory addresses asserted by the CPU. F0000, F0002, , FFFFC, FFFFE Its D3-pin must assume LL state so that the ODD ROM bank is selected for the following odd memory addresses asserted by the CPU. F0001, F0003, , FFFFD, FFFFF Its D4-pin must assume LL state so that the EVN PORT bank (here the Display/Keyboard Controller chip, 8279 of the MicroTalk-8086 trainer, Fig-2.66) is selected for the following even variable port addresses asserted by the CPU. 0000, 00002, , 0FFC, 0FFE Table 2.6
U1s parameters 27C256 (U1) A6 A19 0 0 0 1 1 1 0 A5 A18 0 0 0 1 1 1 0 A3 A2 8086 Signals A17 A16 MIO/ 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 A4 A1 BHE/ 1 0 0 1 0 0 1 A0 A0 0 1 0 0 1 0 0 00000 0FFFE 00001 0FFFF 00000 0FFFF F0000 FFFFE F0001-FFFFF F0000-FFFFF 0000 0FFE EVNRAM ODDRAM BOTHRAM EVNROM ODDROM BOTHROM EVNPORT Memory/Port Range Bank Selected Loca t i o n 0006 0005 0004 007E 007D 007C 0002 Con t e n t FE FD FC FB F7 F3 EF LL Chip Selected Data Operation

ii.

iii.

iv.

v.

D0 D1 D1,D0 D2 D3 D3,D2 D4

M0 M1 M1,M0 M2 M3 M3,M2 Port

Byte Byte Word Byte Byte Word Byte

How to explain the meaning of the above Truth table! Please take your time, get paper and pencil and work out in your own way to discover the spirit of making such kind of truth table. Place your decoder in the MicroTalk-8086 trainer and see that it works!. When the CPU intends to perform a read operation on location 00000h of the even RAM, it executes the instruction mov al, (00000h). As a result the following bit pattern appears on the address lines of the 27256-based decoder:
A19 A18 A17 A16 (0000) M-IO/= LH (1) BHE/=LH (1) (0) A0 = LL signals of the 8086 signal of the 8086 signal of the 8086 signal of the 8086 on the on the on the on the a6 a5 a4 a3 a2 a1 a0 bits of the decoder bit of the decoder bit of the decoder bit of the decoder

What we see now is that the decoder has received the pattern 0000110 as an input address. This pattern has selected its internal ROM location of address 0006h. As a result, the 8-bit content of this location will appear at its output pins D7 D0. If we have wanted that the D0-pin only should assume LL-state to select the even RAM location then certainly we had to store at earlier time the data FEh(1111 1110) at location 0006h of the decoder using a ROM programmer.

76 2.3 (c) Memory Segmentation of the 8086 System

Chapter - 2

2.3.C1 Introduction One of the reasons for the development of the 8086 architecture over the 8085 is to support the Multiuser environment. In a multiuser system [see Fig-2.14 below], there is only one computer with one microprocessor chip but many users. The individual users are provided with a monitor, a keyboard but no processor box. Every user has the full freedom to choose her task and continue it. All the users share the common resources (RAM, ROM, IO and etc.) of the system but each of them has the virtual feeling of having her own computer.
8086 Register Set
AX BX CX DX

Available Memory
(Ptv. Memory Space)

668: multiuser

SS3 ES3 DS3 CS3 SS2 ES2 DS2 CS2 SS1 ES1 DS1 CS1

FR

IP
(Pvt. Memory Space)

SS ES DS CS multiuser L 668

User-1

(Pvt. Memory Space)

BP SI DI SP

Stack Segm ent-3 Extra Data Segm ent-3 Data Segm ent-3 C ode Segm ent-3 Stack Segm ent-2 Extra Data Segm ent-2 Data Segm ent-2 C ode Segm ent-2 Stack Segm ent-1 Extra Data Segm ent-1 Data Segm ent-1 C ode Segm ent-1

User-3

Multi-user/ Multitasking 8086 Computer-1

User-2

User-1

User-2

User-3

Figure-2.14: Memory Segmentation in the Mutiuser System of the 8086 Architecture

2.3.C2 Working Principles of Multiuser/Multitasking Environment The CPU starts with the User-1 and spends only 50mS (for example) time for the user. The User-1 performs as much work as much she can do within the 50mS Time Slot. Anyway, the User-1 will always get 50mS time-slot in every 150mS time period. Thus the User-1 has the feeling that she has her Own CPU and she has been working in the Single User/ Single Tasking environment. But, the fact is not that. The illusion of having a dedicated computer is due to the very fast switching (called task switching) of the CPU among the competing users. Before the CPU starts with the User-1, the 4 memory segments of the User-1 are loaded with the data that belongs to her program. The Base Addresses of the 4 memory segments (CS1, DS1, ES1 and SS1) of the User-1 are also loaded into the Segment Registers of CPU. The other registers are dynamically loaded/updated by the CPU as the instruction codes get executed. The contents of the whole Registers Set describe the Current State of the program of the User-1. At the expiry of the 50mS time-slot, the CPU saves the Current State (the values of the Register Set) of User-1 into the Stack Segment-1 of User-1. The CPU then loads the segment registers of the CPU with the values of the Base Addresses of the 4 memory segments of User-2. The CPU now allocates 50mS time-slot to the User-2. Similar processes are invoked for the User-3.and Usser-4 if any. At the expiry of the last time-slot for User-4, the CPU allocates time-slot for User-1 again. The cycle repeats!

Memory Segmentation of the 8086 System

77

2.3.C3 Code/Data Protection Problems and Solutions in Multiuser System The mutiuser system has reduced the cost of the computer hardware but at the same time it has introduced a new problem, which is: When many users work together, there is a chance that a user makes an unauthorized access to the code/data of another user and corrupts it. This is to say that the codes/data are not protected! The mutiuser environment is implemented by allocating separate memory space to each of the competing users. This scenario is depicted in Fig-2.14 for three users. Now, a user has a Private Memory Space, which will hold all possible class of data that her program will deal with. A program deals with the following four classes of data:
i. ii. iii. v. The binary codes for the instructions of the program itself (known as Code or Cdata). The actual data on which the program will work (known as Data or Ddata). The presence of additional large data such as text (known as Extra Data/ Edata). The return address of the calling/interrupted program (known as stack Data/Sdata).

The above-mentioned four classes of data are stored into four memory slots of the private memory space of a user. This is to say that the private memory space of a user is Segmented into four slices to store program codes and data. The segmentation scheme keeps the program code and data in separate memory spaces and thus reduces the chance of being overlapped. Thus we see that the segmentation method provides some kind protection for code from being mixed up with data. The high degree of protection is achieved in the PVAM (Protected Virtual Address Mode) operation of the 80286/80386 architectures. 2.3.C4 Memory Segments for a Program In segmented architecture, total memory space that belongs to a particular user is divided into the following four segments (Fig-2.11):
i. Code Segment Memory (CSM). It holds the Program Codes (Cdata). The upper 16-bit of the beginning address (called Base Address) of the CSM is stored in the CS register (CSR) of the 8086. The lower 4-bits of the base address are always 0000B (0h) and is considered as having been understood. The size of the CSM can be as high as 64Kbye. An individual location of the CSM is accessed with the help of the IP (Instruction Pointer) register. Data Segment Memory (DSM). It holds data (Ddata) on which the program works. The upper 16-bit of the beginning address of the DSM is stored in the DS register (DSR) of the CPU. The lower 4-bits of the base address are always 0000B (0h) and is considered as having been understood. The maximum size of the DSM is 64Kbyte. The CPU uses the bx (Base Pointer) register to access a memory location of the DSM. Extra Segment Memory (ESM). It holds large (Edata) program data. The upper 16-bit of the beginning address of the ESM is stored in the ES register (ESR) of the 8086. The lower 4-bits are always 0000B (0h) and is considered as having been understood. The maximum size of the ESM could be 64Kbyte. The si/di (Source/destination Index) registers are used to access a particular memory location of the ESM. Stack Segment Memory (SSM). It holds special data (Sdata) like return address. The upper 16bit of the beginning address of the SSM is stored in the SS register (SSR) of the CPU. The lower 4bits are always 0000B (0h) and is considered as having been understood. The size of the SSM can be as high as 64Kbyte. The CPU takes the help of the SS (Stack Pointer), SS (Stack Segment) and the bp (Base Pointer) registers to address a particular memory location in the SSM.

ii.

iii.

iv.

78
2.4 (a) Register Layout of 8086

Chapter - 2

Within the inner part of the microprocessor, there is a fascinating world of Electronics. A substantial amount of this electronics is dedicated to form a vital organ of the microprocessor what is known as Register Set. A register is just like an ordinary RAM location but with an access time in the order of few nanoseconds (1 to 8 nS). It is a costly process to manufacture high speed RAM and this is one of the reasons for not accommodating so many (100) registers within a microprocessor like the 8086. It is the register set that allows a programmer to define the functional behavior of the microprocessor. The register set renders various services to the programmer such as:
i. ii. iii. iv. v. vi. Temporary storage area for variables. As counters. As a pointer to locate program code in an external program area. As a pointer to locate data source (data destination) in an external memory space. Allows a program to take decision as to which path to follow out of many alternatives. Allows the implementation of multiuser and multitasking environment.

In Fig-2.15, the general layout of the register set of the 8086 microprocessor is presented. The sizes of all the registers are 16-bit. The AX, BX, CX and DX registers are divided as lower 8-bit and upper 8-bit. The Table-2.7 summarizes the attributes of the registers of the 8086.
Category 1 2 3 4 5 6 7 8 Symbolic Name AX (AH and AL) BX (BH and BL) CX (CH and CL DX (DH and DL) SP, BP, SI and DI IP FR CS, DS, ES and SS Table 2.7 Register name Accumulator Register Base Register Count register Data Register Pointer/Index Registers Instruction Pointer Register Flag Register Segment Registers Size 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit Access Mode Direct Direct Direct Direct Direct Indirect Indirect Indirect

Figure-2.15: Register Layout of the 8086 Microprocessor

Functions of the 8086 Registers

79

2.4 (b)

2.4.B1 AX ( ah and al) Register i. During data read/write and ALU operations, the CPU uses it as a GPR to hold either 16-bit or 8-bit data. Examples: i. mov al, 12h ii. mov ax, 1234h iii. add al, 12h iv. or al, 23h v. mov al, BYTE PTR [bx] vi. mov ax, WORD PTR [bx+23h] ii. During 8-bit multiplication, one of the data must be in the al-register. The 16-bit result enters into ax-register..

Functions of the 8086 Registers

Example:

mov mul

al, 23h bl

iii. During 16-bit multiplication, one of the 16-bit data must be in the ax-register. The lower part of the result enters into ax-register and the upper 16-bit of the result enters into dx-register.

Example: iv.

mov mul

ax, 3456h WORD PTR [bx]

During 16-bit division, the 16-bit dividend be in the ax-register. The 8-bit quotient enters into the al-register and the 8-bit remainder part enters into the ah-register.
ah-Register ax = dividend 1234h al-Register

=
8-bit divisor

Quotien( 36h)

Remainder (10h) 682

Example:

mov div

ax, 1234h bl

80
v.

Chapter - 2 During 32-bit division, the lower 16-bit of the dividend must be in the ax-register and the upper part is in the dx-register. The 16-bit quotient enters into ax-register and the 16-bit remainder enters into dx-register.

Example:

mov mov mov div

ax, 5678h dx, 1234h cx, 9ABCh cx

; performing 12345678 / 9ABC

vi.

During IO operation with port, the 8-bit (16-bit) data exchange must occur with respect to alregister (ax-register). Example: in al, 30h ; data comes form a fixed port with address 30h in ax, 30h ; 16-bit data from two consecutive port locations

vii. To get correct BCD result from an incorrect BCD result during BCD addition, the incorrect BCD result must be in the al-register. daa instruction is used for this purpose. Example: mov al, BCD1 (27) mov ah, BCD2 (14) add al, ah ; al = 3B, which is incorrect. Expected BCD is:41 daa ; al = 41 2.4.B2 BX (bh and bl) Register i. During data read/write and ALU operations, the CPU uses it as a GPR to hold either 16-bit or 8-bit data. Examples: i. mov bl, 12h ii. mov bx, 1234h iii. add bl, 12h iv. or bl, 23h v. mov bl, BYTE PTR [di] vi. mov bx, WORD PTR [si+23h] ii. Works as 16-bit unsigned offset pointer to locate a memory location in the Data Segment.
FFFFF 3FFFF 32000 bx 30000 00000 Target Loc.

DSM

SBA

728

Figure-2.16: Explaining the use of BX-register as Unsigned Offset Pointer

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81

In the 8086 system, the maximum size of the data segment memory is 64 Kbyte. The system address of the DSM may be anywhere within the 1 Mbyte space except the ROM area. Let us consider the DSM of Fig-2.16 to explain the use of bx-register as an offset pointer to access a data byte from the target location of 32000h In Fig-2.16, the beginning address of the DSM is 30000h (3000:0000). The memory location with which we wish to perform read/write operation is known as Target Location. The target location is located at the address 32000h (3000:2000). Thus we observe that the target location is situated at an offset of 2000h from the beginning address of the DSM. The 8086 programming rule prescribes that the offset of the target location must be passed via one of the valid pointer registers. The bx-register is one of them. The other offset pointer registers are: si, di, sp, ip and bp. The example codes are: mov ax, 3000h mov ds, ax mov bx, 2000h ; offset of target location is placed in bx-register mov al, BYTE PTR ds:[bx] ; data comes from the target location 32000h The bx-register, by default, is an integral part of the DSR and DSM. The content of the bx-register is always added with the content of the DSR to compute the 20-bit address of the target location, even though the DSR-register is not indicated in the instruction. This is to say that the following two instructions do the same job: mov al, BYTE PTR ds:[bx] mov al, BYTE PTR [bx] The bx-register may be attached with other segment registers to work as offset pointer. But, in these cases, the name of the segment registers must be explicitly specified in the instruction. This is known as segment override prefix. mov al, BYTE PTR cs:[bx] ; data comes from CSM (probably ROM area) mov al, BYTE PTR ss:[bx] ; data comes from the stack segment memory 2.4.B3 CX (ch and cl) Register i. During data read/write and ALU operations, the CPU uses it as a GPR to hold either 16-bit or 8-bit data. Examples: i. mov cl, 12h ii. mov cx, 1234h iii. add cl, 12h iv. or cl, 23h v. mov cl, BYTE PTR [di] vi. mov cx, WORD PTR [si+23h] ii. The cx-register has no use as offset pointer iii. cl-register as un 8-bit unsigned Loop Counter. When we desire to repeat an instruction (s) for n (00h FFh) time, the number n could be kept in the cl-register. Example: mov cl, 04h sal al, cl ; content of al-register is shifted left by 4-bits.

82
7 al-register 0 7 al-register 0 6 0 6 0 5 0 5 0 4 0 4 1 3 0 3 0 2 0 2 0 1 0 1 0 0 1 0 After 4-Bit Shift 0 Before Shift 728

Chapter - 2

Figure-2.17: Explaining the use of cl-register as a Loop Counter

When the above two instructions are executed, the contents of the al-register will be shifted to the left by four bit positions. This has been depicted in Fig-2.17. If the cl-register is not used as loop counter, then we have to execute the following series of instructions to shift the contents of the alregister to the left by four bit positions. sal al, 01h sal al, 01h sal al, 01h sal al, 01h iv. cx-register as 16-bit unsigned Loop Counter To repeat an instruction (s) for n times, where the value of n has the unsigned range 0000h FFFFh. The value of n must be put in the cx-register Example: mov cx, 0FFFFh AGN: nop loop AGN

The nop instruction will be executed for FFFFh times. The nop instruction is executed for once and then the loop instruction decrements the content of the cx-register by 01h. The nop instruction is repeatedly executed until the content of the cx-register becomes 0000h. 2.4.B4 DX (dh and dl) Register i. As an 8-bit or 16-bit general purpose register (GPR) for data movement and ALU operations. ii. During multiplication and division process in conjunction with ax-register. iii. During IO operation, it holds the 16-bit address of a variable port (Vport). Example: mov dx, vport ; 16-bit address of variable port is in dx-register in ax, dx ; 16-bit data comes from two consecutive vports..

Figure-2.18: Explaining the use of dx-register to hold the address of a Variable Port

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83

2.4.B5 SI (Source Index) and DI(Destination Index) Registers The SI- and DI-registers are general-purpose 16-bit registers. Like the bx-register, these registers cannot be divided into two halves. The SI- and DI-registers have the identical operational features. We discuss below, the features of the SI-register only, which are also applicable for the DI-register. i. As an offset pointer to locate a target location in a memory segment. By default, the SIregister is attached with the Data Segment Memory. However, by specifying the name of the segment register (this method is known as Segment Override Prefix), the SIregister can be attached with other memory segments. For example:
mov mov al, BYTE PTR [si] al, BYTE PTR es:[si] ; data comes from DSM ; data comes from ESM

ii. As a general-purpose register for data movement. For example:

mov si, WORD PTR [bx]

iii. As a general-purpose register for arithmetic and logical operations. For example:
add rol ax, si si, 01h ; an arithmetic operation ; a logical operation

iv. As a special-purpose register, it works in conjunction with the DI- and the CX-registers. These registers, as a set, can move a block of data from one place to another. In this application, the SI-register points to the beginning address of the data source and the DI-register points to the beginning address of the data destination. The CX-register works as a loop counter to indicate the number of data bytes to transfer. For example:

Figure-2.19: Explaining the use of SI- and DI-Registers

Assume that we wish to move 2048 (0800h) bytes of data from DSM to ESM of Fig-2.19. The following instructions codes could be employed to complete the data transfer operation.
mov mov mov mov mov Cld mov rep ax, ds, es, si, di, 0000h ax ax 3000h 5000h ; ; ; ; ; ; Si points the starting address of data source DI points the starting address of data dest. clear the direction flag number of bytes to transfer continue transfer until cx=0000

cx, 0800h movsb

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2.4.B6 SP ( Stack Pointer )Register i. During data read/write and ALU operations, the user may use the sp-register as a 16-bit general-purpose register..
Examples: a. b. c. d. mov add sal mov sp, sp, sp, sp, 7000h ax cl WORD PTR [si+23h]

ii.

It has no use during programming as an offset pointer to perform data read/write operations in the SSM. Thus, the following instructions are invalid:
a. b. mov mov al, BYTE PTR ss:[sp] ax, WORD PTR ss:[sp]

ii.

The CPU uses it in the background as a 16-bit offset pointer to perform data read/write operations on the SSM during subroutine and interrupt calls. During a subroutine call, the CPU saves the return address (CSH, CSL: IPH, IPL) into SSM. The storage locations are pointed by the sp-register. Let us clarify it with an example and the diagram of Fig-2.20.
FFFFF 08FFF 08FFE

SSM
sp 07000 00000

728x

Figure-2.20: Explaining the use of SP-register as an Unsigned Offset Pointer in SSM Example: 01000 01002 01007 mov call al, 23h : B0 23 SUR1 : 9A 20 00 00 00 ; 01007 = 0000:1007 is return address

; SUR1 Starting Location is 02000 = 00000 + 2000 = 0000:2000 02000 nop ; subroutine begins

Let us assume that the ss- and the sp-registers are loaded with 0000h and 7FFEh during initialization. In the above example, the CPU calls the subroutine (SUR1) at label 01002h. Therefore, the return address is 01007h (0000:1007 = CSH, CSL: IPH, IPL). Now, the CPU executes the following instructions in the background (beyond the knowledge of the user) to save the return address on the SSM (called stack).
sub mov sub mov sp, 02h WORD PTR ss:[sp], 0000h ; CSH, CSL sp, 02h WORD PTR ss:[sp], 2000h ; IPH, IPL

The above instructions indicate that the CPU decrements the content of SP-register by 02h and now, the SP-register points at location 0000:8FFC [Fig-2.21]. The CPU executes the instruction mov WORD PTR ss:[sp-02h], 0000h to save the CSH part of the return address at location 0000: 8FFD and the CSL part of the return address at location 0000:8FFC. Next, the CPU executes the instruction mov WORD PTR ss:[sp-04h], 1007h to save the IPH part of the return address at location 0000: 8FFB and the IPL part of the return address at location 0000:8FFA.

Functions of the 8086 Registers

85

iii. The CPU also uses the sp-register as an offset pointer to save/retrieve user requested data onto stack. For example: if the CPU encounters an instruction like push ax, it executes the following instructions in the background to save the content of ax-register onto the stack of Fig-2.21.
mov WORD PTR ss:[sp-06h], ax

After the execution of the above six SP-SSM related instructions, the structure of the stack space of Fig-2.21 appears as below:

sp-02h

Figure-2.21: Structure of SSM Space after Execution of SP-SSM Related Instructions

2.4.B7 BP ( Base Pointer ) Register We have seen in the previous studies that the programmer cannot use the SP-register as an offset pointer to locate a target memory location in the SSM. The CPU uses the SP-register in the background to access a SSM location to store/retrieve data. But sometimes, in practical applications, programmers desire to manipulate (read-modify-write) data of a particular location of the SSM. In such cases, the programmer can use the BP-register as an offset pointer to access a target location in the SSM. The BP-register, by default is associated with the SSR-register [Fig-2.32]. The 8086 architecture demands that the BP-register must be used with some displacement. If there is no displacement then 00h should be used.
mov mov Example: al, BYTE PTR ss:[bp+00h] al, BYTE PTR ss:[bp} ; this is not a valid instruction`

Refer to Fig-2.21 and write 8086 ASM codes to know the value of the return address. L1: L2: L3: mov mov mov bp, sp ax, WORD PTR ss:[bp+02h] bx, WORD PTR ss:[bp+04h] ; bp = 8FFAh ; ax = IPH, IPL ; bx = CSH, CSL

In the above example, we obtained information from the SSM without disturbing the states of the SSM and SP and it has been possible due to the inclusion of the BP-register in the 8086 architectures. To bring the stack of Fig-2.21 into its original position of Fig-2.20, the following instructions have to be executed by the programmer in the subroutine.
pop ret ax

sp-04h

sp

sp-06h

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Chapter - 2

2.4.B8 FR ( Flag Register ) Register A wise person checks her wallet before she decides to go for dinner in an expensive restaurant. The person is said to be a wise because she has the ability to take decision depending on the monetary condition of her wallet whether to go or not into an expensive restaurant for dinner. To live and sustain life in society, we are always taking decisions to some extent. In fact, the society exists and moves forward through evolutionary process due to the presence of antithesis situations, which forces a person to take a decision to accept one out of many alternatives. In our society, we have a group of people whom we call normal because they can take decisions at need. There are another group of people, who appeared to be at a loss in taking decisions at need and we call them fool! To allow a microprocessor doing jobs for human beings, it must be a normal machine. This means that the MPU must be able to take decisions whether to Ignite the Fire Alarm or Not depending on the input values that it has been continuously acquiring from the environment. The 8086 microprocessors indeed have the ability to take decisions under antithesis situations. The correctness of the decision depends on the Programmer (another Person), who has programmed the 8086 to take decision! There is a register known as Flag Register (FR) or Processor Status Word Register (PSW) within the 8086, which continuously records the antithesis situations in bit form as the CPU keeps on executing the instructions of a program. The CPU automatically keeps looking into these bits of the FR and uses them to take decision whenever necessity arises. The FR of the 8086 is a 16-bit register but there is only nine active bits. The bits from fr1, fr12 fr15 are permanently locked to LH and fr3, fr5 are permanently locked to LL. A bit value can be either a 0 or 1. So, depending on the values of the available nine bits, the CPU can take nine different decisions at different times. The bit structure of the FR is given below in Fig-2.22.

Figure-2.22: Bit Pattern of the Flag Register of 8086

There is no direct instruction to read the whole content of the FR. The read-modify-write operation on the FR by executing the following instructions:
pushf mov and popf ; all bits of FR is stored onto Stack memory bp, sp ss:[bp+00h], 00h ; all bits are made 00h except, fr1, fr12-fr15 ; FR is retrieved from the stack

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87

The following table presents a summary that shows the affects of the 8086 instructions on the Flag Bits of the Processor Status Register.
= Flag Bit is updated x = Flag Bit remains undefined (it may be 0 or 1) = Flag bit remains same as before (not affected)) Table 2.8 Instructions Category Example Data Transfer in, out, lahf, lds, lea, les, mov, pop, pusf, stos, xchg, xlat popf sahf and, cmp neg not or Shift/Rotate/Logical test xor rcl, rcr, rol, ror, sal, sar, shl, shr, String cmps, lods movs scas Arithmetic Instructions aaa aad, aam aas add, sbb, sub, adc cbw, cwd daa, das dec, inc idiv imul, mul Program Transfer call, ja, jae, jb, jbe, jcxz, je, jg, jge, jl, Jle, jmp, jna, jnae, jnb, jnbe, jnc, jne, jng, jnge, jnl, jnle, jno, jnp, jns, jnz, jo, jp, jpe, jpo, js, jz, loop, loope, loopne, loopnz, loopz, ret Processor Control clc cld cli cmc lock, nop, stc, wait std sti

O 0 0 0 x x x x x

D x x

I x x

Flag Bits T S Z x x x x x x x x x x

A x x x x x x x

P x x x x

C 0 0 0 x x

0 1

0 1

Figure-2.23: Table showing the affect of 8086 Instructions on Flag Bits

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Chapter - 2

2.4.B9 IP ( Instruction Pointer ) Register Before getting into the functional meaning of IP-register, let us be familiar with some background information. After applying power to the 8086, we press the RESET switch and then release. This activity prepares the CPU to enter into its operational mode. Now, the CPU wants to know what it should do next. The programmer, in earlier time had to keep this information as coded binary bytes known as Instruction Code into ROM memory starting at a particular location known as Boot Location. In 8086 systems, the boot location has a 20-bit address and it is FFFF0h [Fig-2.24]. Starting from this location, there are only 16-memory locations to go to reach to the upper limit (FFFFFh) of the 8086-memory space [Fig-2.24]. This 16-byte wide (FFFF0h FFFFFh) ROM space is known as Boot Code Segment Memory, BCSM. The BCSM is not large enough to hold a useful program. Therefore, the CPU must be told to jump to a larger WCSM (Working Code Segment Memory) and let us assume that it is from F0000h FFFFFh. The beginning address of the new WCSM is F0000h and the end address is FFFFFh. In this address space, we observe that the lower 4-digit varies from 0000h to FFFFh. Now, we may employ a 16-bit register to point these locations one after another starting from 0000h (0000 0000 0000 0000B). This is the Instruction Pointer Register, which does this job. We may say that the IPregister is an offset pointer in the CSM. It means that the IP-register indicates how far a memory location is from the beginning address of the CSM. Why do we call it IP-register? The binary codes of an instruction (say, mov al, BYTE PTR ds:[di+7Fh]) are kept in the successive locations of the CSM. Let us agree that the binary codes of this instruction are: BA 45 7F and they have been kept in CSM as per diagram of Fig-2.24.

Figure-2.24: Diagram to Explain the Function of IP-register

The instruction codes (BA 45 7F) as indicated in Fig-2.24 collectively refers to the task of moving a data byte into al-register from a DSM location pointed by di+7Fh. The CPU cannot decide what to do until all the three code bytes of the instruction are read and interpreted. Therefore, after reading the 1st code byte (BA), the IP-register must be incremented by 01h in order to allow the CPU reading the next code byte. The CPU increments the IP-register again and reads the last code byte. Now, the CPU increments the IP-register to point to the next CSM location so that having done the task as described in the current instruction, it can easily read the 1st code byte of the next instruction. Now, we may say that the IP-register contains an unsigned value, which points to a CSM location from which the next instruction code byte would be read.

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89

Mechanism of Putting 16-bit value into IP Register: Putting new value into the ip-register means telling the MPU to transfer program control to another location. During reset cycle of the 8086, the IP-register is automatically loaded with 0000h and the CS-register is loaded with FFFFh. This means that the beginning address of the BCSM is FFFF0h and the IP-register is pointing to the 1st location of the BCSM. Now, the programmer can deposit new value into the CS- and IP-register by executing one of the following instructions:
i. FFFF0 jmp F1234H ; F000: 1234 After the execution of the above instruction, the CS-register is loaded with F000H (or whatever is there in the operand part of the instruction. The IP-register is loaded with 1234h (or whatever is there in the operand part of the instruction). The program execution will begin at location, F1234h ii F1234 mov bx, 2000h ; F1234 = F000:1234, bx=2000h jmp bx After the execution of the above instruction, the content of the IP-register would be replaced by the content of the bx-register. The content of CS-register will not be changed. Program execution will start from location, F2000h. F2000 - mov bx, 0600h ; assume DSM base address is: 00000 jmp [bx] After the execution of the above two instructions, the IP-register would be replaced by a 16bit value, which would be found in a DSM-based table similar to Fig-2.25.The beginning address of the table is in bx-register. The value of the CS-register will remain unchanged. Program execution will begin at location, F3000h.

iii.

Figure-2.25: Explaining the Meaning of jmp iv. F3000 - mov mov mov jmp

[bx] Instruction

bx, 0602h WORD PTR [bx], 0040h WORD PTR [bx+02h], 0100h DWORD PTR ds:[bx]

After the execution of the above four instructions, the IP-register would be replaced by a 16bit value, which would be found in a DSM-based table similar to Fig-2.26. The beginning address of the table is in bx-register. The value of the CS-register will be replaced by a 16-bit value, which would be found in the same table at an offset of [bx+02h]. Program execution will begin at location: 01000 + 0040 = 01040h.

Figure-2.26: Explaining the Meaning of jmp

DWORD PTR ds:[bx] Instruction

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2.4.B10 Code Segment Register (CSR) The function of the CSR can be stated by a single statement - It contains the upper 16-bit of the beginning address of the CSM. What do we really understand from this statement? In Fig-2.24, the base address of the WCSM (or simply CSM) is F0000h. The Upper 16-bit (F000h) is kept in the CS-register. The lower 4-bit is always 0s and is understood. We have data and we want that the CPU should do something on this data. It is the program, which tells the CPU to do something (say, adding two numbers) on the data. Or, we can say that it is the program through which we tell the CPU to do something on the data. What we have seen above is that the CPU executes the program to bring the desired change in the given input data. In order to allow the CPU executing a program, the program is converted into machine codes and then the machine codes (also known as Program Codes) are kept in a small part of the external memory space. At the time of execution, the CPU brings the machine codes into its internal Instruction Register (IR) [Fg-2.43]. The IR-register is not accessible by the programmer and for this reason it has not been shown in the register layout diagram of Fig-2.15. The small part of the external memory space, which holds the program codes is known as Code Segment Memory (CSM). In MicroTalk-8086 trainer, we have arbitrarily chosen the space 01000h 02FFFh [Fig-2.27] as the CSM.

Figure-2.27: Diagram showing Four Memory Segments with which a Program Works

Assume that the program codes B0 23 (binary codes for: mov al, 23h) are stored in the CSM starting at locations 01000h. That is we have like: (01000) = B0 ; memory locations 01000h contains B0 (01011) = 23 ; memory location 010011h contains 23 In order to execute the program codes, the CPU must read them one-by-one from the CSM and put them into its internal IR-register. Let us see how the above-mentioned CSM locations are selected for read operation and while seeing it we will get familiar with the use of the CSRregister.

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91

Read Sequence from CSM Location 01000h i. The CPU puts the 20-bit value (0000 0001 0000 0000 0000) of the address of the location on the address bus. The 20-bit value of the address is computed in the following way: a. The 20-bit address is split into two parts: 01000h (0000 0001 0000 0000 0000) 00000h + 1000h (0000 0000 0000 0000 0000 + 0001 0000 0000 0000) Referring to Fig-2.27, we may state that:
1. 2. 00000h defines the Base Address (BA) and it is 20-bit 1000h defines how far the Beginning Address of CSM is from BA.

b. c. d.

The BA is fixed (at least in this example). The offset part varies from 1000h to 2FFFh (at least in this example of Fig-2.27) The offset part may be kept in a suitable 16-bit register of the CPU and let us agree that is: IP (Instruction Pointer) register. Now, where to keep the 20-bit value of the Base Address? 100 million dollar question! Certainly, we need a 20-bit register! It has been very easy to say like this but was not possible for the Intel Engineers to incorporate 20-bit registers within the 8086 at the time of its development. Because, all the registers are of 16-bit size and it was easy to incorporate a new 16bit register named Code Segment Register (CSR or CS) to hold the base address. But, how a 16-bit register can hold the 20-bit value of the base address? Impossible! Not really impossible! It has been made possible by saying the following statements: 1. The base address will always be 20-bit but its lower 4-bit must be 0000b. 2. The upper 16-bit can have any value ranging from: 0000h FFFFh, which can easily be kept in the CSR. 3. Before asserting the address of the desired CSM location, its 20-bit address must be computed in accordance with the steps listed below:
i. Move the 16-bit value of the CSR into the upper 16-bits of a 20-bit temporary register. We call it Address Temporary Register (ATR) [Fig-2.28].. Put 0000B into the lower 4-bits of the address temporary register. Perform unsigned addition of the 16-bit value of IP-register with the lower 16-bit of the ATR. Move the lower 16-bit of the result into lower 16-bit of the ATR. Add the upper bit (the Carry bit) of the above addition process with the upper 4-bit of the ATR and leave the result into ATR.

ii. iii.

iv.

4.

Finally, move the 20-bit content of the ATR onto the physical address lines (A19 A0) of the 8086 microprocessor.

The above scenario is explained further with the help of the diagram of Fig-2.28. In this diagram, we have assumed that the:
i. ii. Base Address is: 00000h. Offset of the target location is: 3012h

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Figure-2.28: Diagram Explaining Computation of 20-Bit Address for CSM Locations using 16-bit Registers

Putting 16-bit values into CSR: i. At power up reset, FFFFh is automatically loaded into the CSR register. ii. The programmer can store any desired 16-bit value into CSR by executing the jmp DWORD PTR [bx] instruction [Fig-2.26]. ii. By interrupting the CPU. After an interruption, the CSR- and IPR-registers of the 8086 are replaced by the beginning address of the Interrupt Sub Routine (ISR). The programmer can choose any 20-bit (CS:IP) value for the beginning address of the ISR within the available memory space. In Chapter-5, we have included discussion about it. iii. By executing an artificial iret instruction. What is the meaning of executing the iret instruction artificially? After the occurrence of an interrupt signal over the INTR- or NMI-pin of the 8086, the CPU saves the return address on the SSM and then goes to the ISR. It finishes the ISR and then executes the iret instruction to resume the interrupted main line program. After the execution of the iret instruction, the CSR- and IPR-registers are loaded with the return addresses from the stack. Execution of the iret instruction artificially refers to the situation where the CPU had not been physically interrupted. The programmer wishes to load some known values into the CSR- and the IPR-registers. To achieve this goal, the programmer stores the desired values onto the stack [Fig-2.21] and then executes the iret instruction. The CPU is made fool to believe that a physical interruption had occurred and now it had to retrieve the return address from the stack. A programmer, if she wishes, she can use some locations of CSM to hold data. In such cases, she has to use one of the following instructions to access the target CSM location to read the data byte. The 20-bit address of the target location is computed using CSR and the specified pointer register.
i. ii. iii. iv. mov mov mov mov al, al, al, al, BYTE BYTE BYTE BYTE PTR PTR PTR PTR cs:[bx] cs:[si] cs:[bx+si] cs:[offset due to valid combination of bx, si, di]

Functions of the 8086 Registers

93

2.4.B11 Data Segment Register (DSR) Refer to Fig-2.27, the beginning address of DSM has been chosen as 03000h. This 20-bit value can be split into two parts (Base Address and the offset of the beginning address of DSM) similar to the beginning address of the CSM. The upper 16-bit of the base address (which is 0000h in this example) is kept in the DSR-register. The offset part of the beginning address of the DSM is kept in the bx-register. Now, the 20-bit address of the target location of the DSM is computed by using the algorithm of Fig-2.29. However, general features of the discussion made on the CSR are also applicable for the DSR.

Figure-2.29: Diagram Explaining Computation of 20-Bit Address for DSM Locations using 16-bit Registers

2.4.B12 Extra Segment Register (ESR) Refer to Fig-2.27, the beginning address of ESM has been chosen as 05000h. This 20-bit value can be split into two parts (Base Address and the offset of the beginning address of ESM) similar to the beginning address of the CSM. The upper 16-bit of the base address (which is 0000h in this example) is kept in the ESR-register. The offset part of the beginning address of the ESM is kept in the si- or di-register. Now, the 20-bit address of the target location within the ESM is computed by using the algorithm of Fig-2.30. General features of the discussion made on the CSR are also applicable for the ESR.

Figure-2.30: Diagram Explaining Computation of 20-Bit Address for ESM Locations using 16-bit Registers

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2.4.B13 Stack Segment Register (SSR) Refer to Fig-2.27, where the beginning address of SSM has been chosen as 07000h. This 20-bit value can be split into two parts (Base Address and the offset of the beginning address of SSM) similar to the beginning address of the CSM. The upper 16-bit of the base address (which is 0000h in this example) is kept in the ESR-register. The offset part of the beginning address of the SSM is kept in the sp-register. Now, the 20-bit address of the target location within the SSM is computed by using the algorithm of Fig-2.31. General features of the discussion made on the CSR are also applicable for the ESR.

Figure-2.31: Diagram Explaining Computation of 20-Bit Address for SSM Locations using 16-bit Registers

2.4.B14 Association of Segment Registers with Offset Pointer Registers There are four segment registers and these are:
i. ii. iii. iv. i. iv. CS Register : DS Register: ES Register: SS Register: BX Register BP Register It holds the upper 16-bit of the bases address of CSM. It holds the upper 16-bit of the base address of DSM. It holds the upper 16-bit of the base address of ESM It holds the upper 16-bit of the base address of SSM ii. v. SI Register SP Register iii. vi. DI Register IP Register

There are six offset pointer registers and these are:

Now, the question is: Which offset pointer register is associated with which segment register while accessing memory locations? The answer is given in Fig-2.32. The default association refers to the meaning that the indicated association comes up automatically after power up and remains like this until the programmer changes it by what we call Segment Override Prefix.
Offset Pointer Register
IP BX SI DI DI BP SP

Default Association
CSR DSR DSR DSR ESR SSR SSR

Example Default
Carried out by CPU mov al, BYTE PTR [bx] mov al, BYTE PTR [si] mov al, BYTE PTR [di] During string transfer [Section-2.4.B5] mov al, BYTE PTR [bp+00h] Carried out by CPU

Segment Override Prefix

mov mov mov mov al, cs:[bx] al, BYTE PTR cs:[bx] al, BYTE PTR es:[si] al, BYTE cs:[di]

mov al, BYTE PTR ds:[bp] mov al, BYTE PTR ss:[bx]

Figure-2.32: Default Association of Pointer Registers with Segment Registers and Memory Segments

Functions of the 8086 Registers

95

2.4 (c)

2.4.C1 Carry Flag ( CF or simply C): A LH-state at C-bit position indicates that: i. An arithmetic operation on two 8-bit unsigned numbers has produced a result, which is greater than 8-bit. For example: FF + FF = 1 FE . The programmer should always check the C-bit to know the size of the result. ii An arithmetic operation on two 16-bit unsigned numbers has produced a result, which is greater than 16-bit. For example: FFFF + FFFF = 1 FFFE . The programmer should always check the C-bit to know the size of the result. iii. A logical operation (like rotating or shifting the data bits through C-bit) has been carried out on 8-bit or 16-bit data. 8086 Instructions to Manipulate C-bit: i. clc : Clear Carry Bit 0C ii. cmc : Complement Carry Bit iii. jc LX : Sensing the LH-state of Carry Bit iv. jnc LY : Sensing the LL-state of carry Bit Use of C-bit: Carry bit allows accumulating the carry bits that are generated during the addition of two or more numbers.
Example-2.2 [adding the numbers: A9h, FFh and BDh using 8-bit registers]
A9h + FFh -------------------1 A8h
1st Carry

Detailed Function of the Flag Bits of Flag Register

A8h + BDh -------------------1 65h

2nd Carry Final Result = 1st Carry + 2nd Carry 65h = 2 65h

A9h + FFh + BDh -------------------2 65h

Accumulated Carry

23

Figure-2.33: Explaining the Use of Carry Bit

When we add the given three numbers using paper-pencil, we see that the Carry bit is generated for two times and the final result becomes 2 65h. However, if we wish to use a MPU to perform the addition of these three numbers, there must be a 1-bit location within the CPU to

96

Chapter - 2

accommodate the Carry, which is generated after adding each two numbers. This is the C-bit in the Flag Register [Fig-2.22] that holds this carry. Since, there is a possibility of the generation of carry for many times depending on the input number counts, the user program must declare a carry counter to add all these carry. The following flow chart of Fig-2.34 and the associated assembly codes are presented to clarify the concept one step further.

START: L1:

nop

Num1 +Num2 L2: Carry ?

C, al

L3:

Increase Carry_Counter L4: al + Num3 L5: Carry ? Y L6: C, al

Increase Carry_Counter L7: Final Result in ax-register L8: halt 23

Figure-2.34: Explaining the Use of Carry Bit to Accommodate Final Result

Assembly Codes for the Flow Chart of Fig-2.34:

START: L1: L2: L3: L4: L5: L6: L7: L8: L1: nop mov mov add jc jmp inc add jc jmp inc mov hlt Carry_Counter, 00h al, Num1 al, Num2 L3 .. Carry_Counter al, Num3 L6 .. Carry_Counter ah, Carry_Counter ; initially Carry Counter must hold 00

; result in ax < ah, al > register

Example-2.3: Adding the numbers: ABCBh, FFFFh and BCADh using 16-bit registers.
mov ax, Num1 add ax, Num2 L2: jc L3 . ; result is 17-bit and it is in C, ax

Functions of the 8086 Registers

97

2.4.C2 Parity Flag ( PF or simply P): The general meaning of parity is: exact analogy or equivalence. In mathematics, parity refers to a relationship between two integers. If both are odd numbers or both are even numbers they have the same parity. When a binary number contains even number of 1s, we say that the number has even parity. When the number contains odd number of 1s, it is an odd parity number. The number 66h (0110 0110) is an event parity number and the number 67h (0110 0111) is an odd parity number. By definition, the number 00h (0000 0000) is an even parity number. A LH-state at P-bit position indicates that: i. An arithmetic on two numbers (either 8-bit or 16-bit) has produced a result, which contains even number of 1s. For example:
mov add al, 23h al, 01h ; al= 24h (0010 0100)- an even parity number

ii.

A logical operation (either on 8-bit or 16-bit data) on a number has brought even number of 1s in the result. For example:
mov and al, 84h al, 05h ; al = 1000 0100 ; al = 0000 0101 P = 0 P = 1

8086 Instructions to Manipulate P-bit: i. There is no direct 8086 instructions to set or reset the P-bit. A known state of the P-bit can be achieved by executing the following instructions
:

pushf mov or popf

; keeping the FR register into stcak bp, sp ss:[bp+00h], 0004h ; putting LH at P-position ; now P-bit has assumed LH-state

i. iv.

jpe LX : Sensing even number of 1s jpo LY : Sensing odd number of 1s

Use of P-bit: The parity bit is widely used in data communication for error checking. The purpose is to see that the data sent from the transmitter has arrived at the receiver without any error. It doesnt ensure that the data has arrived correctly. For example: i. Transmitted data is: 1010 0001 : contains odd parity. ii. Received data is: 1010 0001 : contains odd parity iii. Data so received is correct and error free. But, let us look at the following example: i. Transmitted data is: 1010 0001 : contains odd parity ii. Received data is: 1010 0111 ; contains odd parity iii. Data so received is error free but incorrect. Parity check is a very simple check and is usually used for asynchronous serial communication. The CRC (Cyclic Redundancy Check Character) parity check is a complex and sophisticated parity check, which is used in data communication system like USB protocol. The following ASM codes add even parity to the number: 23h (0010 0011) by inserting LH at 7th bit position:

98
mov add jpe or al, 23h al, 10h LX al, 40h ; al = 0011 0011 ; There is even number of 1s ; al = 1110 0011 ; odd parity P = 1 P = 0

Chapter - 2

2.4.C3 Auxiliary Carry Flag ( AF or simply A): A LH-state at the A-bit position indicates that: i. An arithmetic operation on two 8-bit numbers has caused a carry (LH) to propagate to the next higher bit position from the middle of the result. This is to say that a carry has been generated from the 3rd bit). For example: data1 = 0111 1000 + data2 = 0000 1001 ---------------------------------------------result = 1000 0001 In the above operation, we see that a carry (LH) has propagated from bit-3 position to the next higher position. The CPU records this event by putting LH-state at the A-bit (auxiliary carry) position of the flag register. 8086 Instruction to manipulate A-bit: i. There is no direct instruction to manipulate the A-bit. However, the A-bit can be set/reset or its state can be known in an indirect way by executing the following instructions:
; sensing LH-state of the A-bit pushf mov bp, sp mov ax, WORD PTR ss:[bp+00h] mov cl, 05h rcr ax, cl ; now A-bit has come into C-bit jc LY ; Finding that A-bit is at LH-state

ii.

daa instruction internally checks the LH-state of the A-bit and if so the CPU takes action according to the meaning of daa instruction (Chapter-6) to obtain correct BCD result..

Use of A-bit: i. To obtain correct BCD result after telling the CPU to add two BCD numbers. When the CPU is instructed to add two BCD numbers, it adds them considering that the numbers are binary (hex) numbers and produces an incorrect BCD result. If the input BCD numbers is 78 and 09, then the addition process will produce the apparent result of 81 instead of 87. Now, let us add 06 with the apparent (incorrect) result to get the correct (adjusted) result of 87. Why to add 06h? Somebody has discovered that a carry propagates from bit-3 position while adding some particular pair of numbers like 78 and 09 (or similar). Under this condition, a correct BCD is found only by adding 06h with the incorrect BCD result. For example:
; adding the BCD numbers 78 and 09 mov al, 78h add al, 09h ; al = 81 = 1000 0001 daa ; al = 81+06 = 87

; expected value is: 87 ; corrected BCD

daa (Decimal Adjustment on the content of al-register after addition) instruction always works on 8-bit data and the data should be in the al-register.

Functions of the 8086 Registers 2.4.C4 Zero Flag ( ZF or simply Z): A LH-state at the Z-bit position indicates that: i. An arithmetic operation on an 8-bit (or 16-bit) data has produced a result, which is 00.
Example: mov dec mov and al, 01h al al, 21h al, 00h ; al = 00h. So, LH Z-bit

99

ii.

A logical operation on an 8-bit (or 16-bit) data has produced a result, which is 00.
Example: ; al = 00. So, LH Z-bit

8086 Instruction to manipulate Z-bit: i. There is no direct instruction to set/reset the Z-bit. ii. The Z-bit can be set/reset by putting it into the stack iii. jz LX ; sensing the LH-state of the Z-bit iv. jnz LY ; sensing the LL-state of the Z-bit Use of Z-Bit: To perform an instruction for so many times.
Example: AGND: mov dec jnz al, 05h al AGND

The decrement instruction is being executed for five times in order to get 00h in al-register. 2.4.C5 Sign Flag (SF or simply S): A LH-state at the S-bit position indicates that: i. An arithmetic operation on an 8-bit (or 16-bit) data has produced a result, which has LH at its MS-bit position.
Example: mov al, 00h ; 0000 0000 (00h) indicates positive number dec al ; al = FFh = 1111 1111 (00h01h=-01h) js LX ; negative signed number

8086 Instruction to manipulate S-bit: i. There is no direct instruction to set/reset the S-bit. ii. The Z-bit can be set/reset by putting it into the stack iii. js LX ; sensing the LH-state of the S-bit Use of S-Bit: i. In 8086 architectures, a negative number is represented using 2s complement form. For an 8-bit signed number, the MS-bit carries both sign and magnitude. Thus, LH at MS-bit certainly indicates that the number under question is negative. The sign-bit doesnt say anything about the value of the number. It is the programmers responsibility to extract the decimal value of the number.
Example: mov al, 0F2h dec al js LX LX: and al, 7Fh mov ah, 80h sub ah, al call BIN2BCD ; 1111 0010 indicates number (+ve or ve )? ; al = F1h = -15 (-14 1 = -15) ; negative number (-15);programmers choice ; al = 71 ; 80 = 1000 0000, the magnitude of sign bit ; 80h 71h = 0Fh ;ah=15; now place (minus sign) before 15

100
ii.

Chapter - 2 In conjunction with O-bit and C-bit, it determines the sign of the result after a Twos Complement Arithmetic (TCA) operation. The decision tree is given below in Fig-2.35.
START:

GM : 3-1- 07 : 611a15

TCA Operation SL1: SL2 : N OF=1 ? Y SL2A :

SL6:

SF=1 ? SL 3: Y

SF=1 ? SL 3A: CF=1 ? SL 4A: N N

SL 6A:

SL 8:

CF=1 ? SL7 : Y

SL5:

CF=1 ? SL 4: Y

SL5A :

CF=1 ? SL 7A: N

Y SL8A :

Unsigned Positive

Unsigned Positive

Signed Negative

Signed Negative

Signed Negative

Signed Negative

Unsigned Positive

Unsigned Positive

Figure-2.35: Use of S-bit, O-bit and C-bit to Determine the Sign of a Number after TCA Operation Example: We wish to subtract mov al, 6Ch mov ah, 0D1h sub al, ah jo LX LX: js LY .. LY: call BINBCD 47 from 108. The expected result is: +155 ; 6Ch = 108 ; D1 = -47 ; al = 9Bh; S-bit=1, C-bit=1 and O-bit=1

; al = |9Bh| = +155

2.4.C6 Trap Flag (tf or simply T): The set/reset conditions of the C-bit, P-bit, A-bit, Z-bit and S-bit were determined by the outcomes of the result of ALU operations on data. This is to say that the logic values of these five flag bits were Process Driven. The exception is the T-bit, which is intentionally set by the programmer and when set; the CPU is forced to do a particular job. This particular job is: execution of one instruction at a time known as Single-stepping or trace. A program consists of many instructions and the CPU usually executes the whole program in one GO. Very often, there are logical errors in the program, which dont prevent the CPU from executing the program but dont produce the expected result. Under this circumstance, we wish to find out the faulty instruction (s). Execution of one instruction at a time and then checking the register/memory locations for correct contents helps finding the incorrect instruction (s). The 8086 architectures has supported the single-stepping mechanism by including the T-bit in it flag register. The detailed description of the use of T-bit in executing one instruction is given in Chapter-5. In this section, we would be familiar with a brief introduction.

Functions of the 8086 Registers 8086 Instruction to manipulate T-bit: i. There is no direct instruction to set/reset the T-bit. ii. The T-bit can be set/reset by storing the FR into the stack
Example: pushf Mov or poph ; FR (16-bit ) is in stack (Fig-2.36) bp, sp ss:[bp+00h], 0100h ; 0000 0001 0000 0000; T-bit=LH ; now T-bit of FR is LH
1 FRH FRL 08FFF 08FFE 08FFD 08FFC 08FFB 08FFA 08FF9 08FF8 [sp-06h] 07000 00000 1 00 00 20 00 FRH FRL

101

08FFF 08FFE 08FFD 08FFC

SSM
[sp] [Sp-02h] 07000 00000

SSM

728y

(a) Putting LH at T-bit (b) Trick to Execute One Instruction Figure-2.36: Explaining the Trick of Putting LH at T-bit and Executing One Instruction

Use of T-Bit: Let us see the use of T-bit in the execution of only one instruction of the following sample program. The Sample Program:
02000 (0000:2000) 02002 (0000:2002) 02005 (0000:2005) B0 12 BA 00 36 : : mov mov al, 12h dx, 3600h

We wish to execute the 1st instruction only. After the execution of the 1st instruction, the 2nd instruction would be ready for execution. After that, the next instruction would be executed and so on until all the instructions are executed one-by-one. Procedures:
1. 2. 3. 4. 5. Push the FR into stack of Fig-2.36: Push the Segment part of the current instruction onto stack: Push the Offset part of the current instruction onto stack: Put LH at the T-bit of FR, which is on stack of Fig-2.36: pushf mov push ax mov push ax mov or ;[Fig-2.36 (a)] ax, 0000h ;[Fig-2.36 (b)] ax, 2000h ;[Fig-2.36 (c)] bp, sp [bp+04h], 0100h

To execute the 1st instruction, its address 0000:2000 must some how be placed in the CS- and IPregister of the 8086. This can easily be done by putting them on the stack in the way that we have done above. Now execute the instruction iret (not the ret). The IP- , CS-, and the FR-registers would be replaced by the values that are in the stack of Fig-2.36(b).

6.

During the execution of the iret instruction, the 8086 doesnt sample the flag bits of the FR. Therefore, the CPU will not be interrupted and it will proceed to the execution of the instruction pointed by cs:[ip], which is our 1st instruction in the program at location 02000.

[sp]

728y

102

Chapter - 2

While executing the current instruction at address 0000:2000, the CPU samples the FR-register and finds that the T-bit is set. The CPU is immediately interrupted and prepares to jump to an Interrupt Sub Routine due to Trap Interrupt (ISRT). Before jumping to the ISRT, the CPU: a. Finishes the instruction pointed by cs:[ip], which is our 1st program at location 02000h, b. Saves the FR onto the stack and resets the T-bit c. The 20-bit address of the next instruction (0000:2002) is saved in the stack. Now, we have seen that only one instruction of the program has been executed and the 2nd instruction is ready for execution. We may now follow steps-4, 6 to single-step the 2nd instruction. All the remaining instructions of the program could be easily single-stepped (S/S) in this manner. The summary procedure is:
Main ML1: ML2: ML3: ML4: Line Program: FR Stack 1st Instruction address Stack Put LH at T-bit of Stack if (s/s key not pressed) Goto ML4 ML5: execute iret artificially Interrupt Subroutine for Trap: ISRTL1: Display register contents ISRTL2: If (Home key not pressed) goto ISRTL1 ISRTL3: goto ML3 maintaining stack

The readers may perform the Single Stepping tasks of the MicroTalk-8086 trainer (AppendixA.1) to see that the above-mentioned control codes have really been implemented. 2.4.C7 Interrupt Flag (IF or simply I): Introduction: The CPU does not determine the set/reset state of the I-bit. It is the programmer who decides whether to put LH or LL at this bit. Putting LH at the I-bit serves the following purposes: i. An IDIC (like KBIC of Fig-2.37) can request the CPU to suspend its present job and then read data from the KBIC. Submitting a request like this way is known as interrupting the CPU. An input port can place an interrupt request (IRQ) signal to the 8086 microprocessors via its INTR (Interrupt) pin [Fig-2.37]. Detailed study on interrupt would be carried out in Chapter-5. However, without being interrupted, the CPU can still read data from IDIC at any time just by executing a read instruction. This method of reading data is known as polling. The interrupt method ensures that there is data inside the IDIC and thats why it has interrupted the MPU. The polling method doesnt ensure data availability inside the IDIC because probably, the IDIC has not yet received any data from the input device. ii. An output port (ODIC) can also place an IRQ signal to the CPU to receive data. 8086 Instruction to manipulate I-bit: i. sti (Set Interrupt Bit) : 1 I-bit ii. cli (Clear Interrupt Bit) : 0 I-bit After the interrupt, the CPU automatically puts LL at I-bit to prevent the CPU from being interrupted until the requested job is complete.

Functions of the 8086 Registers

103

Use of I-bit : In real situation, the CPU has many tasks to do, which it does one after another like regulating the temperature of four ovens in an industry [Fig-2.37]. Under this circumstance, an effort to read a less important data like checking if a guest has arrived and the door should be opened by polling method (reading again and again) may be considered as wastage of time. Now, the system designer can propose that the side job could be carried out by interrupt process using the INTR-pin of the CPU. Putting LH at the I-bit of the flag register enables the INTR interrupt. The design of the process may involve: i. The CPU will remain busy in looking after the ovens. We may call it Main Line Program (MLP). ii. Whenever a guest arrives, she will push a switch to announce her presence. The switchsignal will interrupt the CPU. iii. The CPU will suspend the MLP for a while and then will turn to the side job (also known as Interrupt Sub Routine = ISR) and will finish it. Here, the side job refers to opening of the automatic entrance door. Execution of the ISR becomes possible due to the presence of LH at the I-bit. iv. After finishing the ISR, the CPU resumes the MLP. The hardware arrangement of Fig-2.37 could be proposed to implement the above job that involves looking after four ovens on round-robin basis and serving one side job on interrupt..

Figure-2.37: Explaining the use of I-Bit for Serving Side Job by Interrupt

Program Codes to Control the Operation of the System of Fig-2.37:

Main Line Program (MLP): ML1: sti ML2: Regulate Heater1 ML3: Regulate Heater2 ML4: Regulate Heater3 ML5: Regulate Heater4 ML6: Goto ML2 ISR: ISRL1: ISRL2: ISRL3: ISRL4: CPU put LL at I-bit Open Door sti iret(Return to MLP from ISR)

While the CPU remains busy in executing the instructions ML2-ML6-ML2 of the main line program, the IRQ signal from the KBIC may arrive at any time (asynchronous arrival).

104

Chapter - 2

2.4.C8 Direction Flag (DF or simply D): The programmer decides the initial value (LH or LL) of the D-bit depending on her requirements. Putting LL at the D-bit serves the following purpose:
A block of data byte (or data word) would be moved from DSM (source) to ESM (destination) very quickly. The offset pointer for DSM (SI-register) and ESM (DI-register) would be automatically incremented. The counter (CX-register) holding the number of data items to be moved is automatically decremented.

8086 Instruction to manipulate D-bit: i. std (Set Direction Flag Bit) : ii. cld (Clear Direction Flag Bit) : Use of D-bit:
729

1 D-bit 0 D-bit

Data Source
FFFFF 04FFF

Data Destination
FFFFF 06FFF

DSM
si 03000 00000 di 05000 00000

ESM

Figure-2.38: Explaining the use of D-Bit for Quick Data Transfer Slow Process without Using D-bit: (Requires 11 lines of ASM Codes) To move 1024 (0400h) byte data from DSM to ESM of Fig-2.38 : L1: mov cx, 0400h ; Cx-register is counter for 1024 byte mov si, 3000h ; SI pointing at the beginning of DSM mov di, 5000h ; DI pointing at the beginning of ESM L2: mov al, BYTE PTR [si] ; data item is reda from DSM mov BYTE PTR [di], al ; data item is written into ESM L3: dec cx jz L5 ; transfer complete L4: inc si inc di jmp L2 L5: hlt

Quick Process using D-bit: (Requires only 6 lines of ASM Codes)

To move 1024 (0400h) byte data from DSM to ESM of Fig-2.38 : L1: mov cx, 0400h ; Cx-register is counter for 1024 byte mov si, 3000h ; SI pointing at the beginning of DSM mov di, 5000h ; DI pointing at the beginning of ESM cld ; 0 D-bit L2: REP movsb ; keep moving byte-by-byte from DSM to ESM L3: hlt ; until transfer is complete.

Having executed the movsb (move string byte-by-byte) instruction, the CPU auto decrements the CX-register and if it is not zero then SI- and DI-registers are automatically incremented.

Functions of the 8086 Registers

105

2.4.C9 Overflow Flag (OF or simply O): The CPU updates the O-bit, C-bit and the S-bit after the execution of the relevant instructions [Fig-2.23]. It allows the programmer to determine the sign (positive or negative) and the value of the result after arithmetic operations on the input data. In computer, the standard data size is 8-bit, which ranges from 00h FFh. The ALU of the MPU doesnt know anything about the sign and the size of the output data (the result). The CPU only produces the bit pattern. It is the responsibility of the programmer to decide it because she has some idea about the sign and size of her input data. The readers are referred to Section-2.4.C5 (Fig-2.35) and subtraction instruction (Ch-3) to see the role of the O-bit in the determination of the sign and the size of a result. However, in this section, we make a brief introduction on the O-bit. If the input numbers are always unsigned, then there is no problem to determine the sign and the size of the result. The C-bit constitutes the MS-bit of the result. If we assume that the input numbers could be both positive and negative and we want to deal with them by common rules (TC), then we face difficulties to determine the sign and the size of the result. The difficulties are removed by taking care of S-bit, C-bit and O-bit as per Fig-2.35. In 2s complement signed-number system, we have the following attributes for an 8-bit number: i. Maximum size and maximum value of Positive Number: 0111 1111 = 7Fh (+127) ii. Maximum size and minimum value of Negative Number: 1000 0000 = 80h (-128) Let us clarify the use of O-bit, with an example: a. We have two unsigned input numbers : +108 (6Ch) and +81 (51h) b. The expected result is : +189 (BDh) c. The 8086 instructions for addition: mov al, 6Ch add al, 51h ; al = BD = 1011 1101 d. 6Ch = 0110 1100 + 51h = 0101 0001 ----------------------------------result = 1011 1101 e. Because the inputs are positive numbers and are accommodated in the lower 7-bits, the result also should be positive. In Step-d above, we observe that the result could not be accommodated in lower 7-bit. This is to say that the result is greater than 7-bit but positive. This fact has been realized by the introduction of the overflow flag, O-bit. Under this circumstance, the O-bit is set to LH. But, the propagation of LH from the 7th bit has arrived at MS-bit and this has caused the S-bit to assume LH. But, the result is not a ve number! f. Now, what is the sign and size of the result? The answer is provided by looking at the flow chart of Fig-2.35, which has depicted all possible outcomes depending on the values of the Sbit, C-bit and O-bit g. The flow chart of Fig-2.35 dictates that the 8-bit result should be interpreted as an unsigned number to get the positive result of +189.

106
2.4 (d)
2.4.D1 Simplified Block Diagram

Chapter - 2

Internal Processing Blocks of 8086

Figure-2.39: Diagram Depicting the Major Processing Blocks of 8086 [2]

Bus Interface Unit (BIU): The 20-bit address for the target memory location (or Port Location) is computed with the help of Address Computing Unit (ACU) and is then asserted on the address bus. The memory (port) read/write control signals (not shown) are also generated and asserted on the control bus. Data (code byte or data byte) from the selected memory (or Port) comes into the CPU over the data bus. It the data is a code byte; it enters into the Instruction Stream Byte Queue (ISBQ) and then into the Control System of the EU unit for decoding and execution. For the case of a data byte, it enters into one of the general-purpose registers [Fig.2.43]. Execution Unit (EU): Instruction bytes are decoded and necessary actions are taken like: performing ALU operations using the ALU Unit or making a jump to another point of the program using Control System.

Internal Processing Blocks of 8086

107

2.4.D2 Address Computing Unit (ACU) During the execution period of a program, the CPU takes the help of the ACU unit to compute the addresses of memory (port) locations for code (data) read/write operations: i. Computing 20-bit Address of a CSM location from which the next code byte of the current instruction is to read. Example: 01000 (0000:1000) B0 23 : mov al, 23h st code byte (B0) from CSM location 01000 (0000:1000). The CPU is ready to read the 1 The ACU unit computes the address in the following way: a. The CS-register contains the value 0000h and the IP-register contains the value 1000h. b. The digit-0 (0000B) is placed at the right of CS-register by the mechanism as depicted in Fig-2.28 to get the 20-bit value of segment base address (SBA) and it is placed in ATR (Address Temporary Register). c. The content of IP-register is added with the 20-bit value of SBA. d. Finally the 20-bit physical address is placed on the address bus. e. To read code byte from the next CSM location, the content of IP-register is incremented and then the Step-c, d of above are followed. ii. Computing 20-bit Address of a DSM location from which a data byte (or a data word = 2 Byte) to read. Example: 01012 (0000:1012) 8A 47 10 : mov al, BYTE PTR ds:[bx+10] 01015 (0000:1015) -

Figure-2.40: Diagram Explaining the Computation of 20-bit Address of a Target Location in DSM

The instruction mov al, BYTE PTR ds:[bx+10h] tells the CPU to read the 8-bit content of DSM location 03010h and put the content into al-register. Let us see, how the ACU computes the 20-bit address of the target location in the DSM. a. From the opcode 8A 47, the CPU automatically understands that the current instruction is a data read operation from DSM and its 20-bit address should be computed as follows: 1. The current value of DS-register and BX-register would be added together by the ACU as per Fig-2.29 and 2.39.

38:GM:10-08

108
2.

Chapter - 2 From the opcode 8A 47, the CPU has understood that the current instruction is of 3-byte long and the last byte (10h) of the instruction code in an 8-bit displacement wrt to bx-register and it has to be added with bx-register to get the offset part of the address of the target location. The displacement part is in a memory location of the CSM and it has to be added by the ACU after it is read as a code byte. This fact has been depicted in Fig-2.39 by having a branch of the C-bus connected with the ACU. Finally, the ACU adds the content of the bx-register with the displacement, which has been encoded in the instruction. After that, the ACU adds the offset with the DS-register as per Fig-2.39 to find the 20-bit physical address of the target location in DSM. The address is put on the address bus, read command is generated; the content of the DSM location enters into the al-register. The CPU is ready to execute the next instruction at the CSM address 01015h.

3.

iii.

Computing 20-bit Address of an ESM location from which a data byte (or a data word = 2 Byte) to read. Example: 01012 (0000:1012) 26 8A 44 10 : mov al, BYTE PTR es:[si+10] 01016 (0000:1016) The data source location is situated in the ESM memory segment. The 20-bit address is given in the instruction by the expression BYTE PTR es:[si+10h]. The address computation mechanism is exactly similar to that of the instruction mov al, BYTE PTR ds:[bx+10h] but this time using the diagram of Fig-2.30.

iv.

Computing 20-bit Address of an SSM location from which a data byte (or a data word = 2 Byte) to read. Example: 01012 (0000:1012) 8A 46 10 : mov al, BYTE PTR ss:[bp+10h] 01016 (0000:1016) The data source location is situated in the SSM memory segment. The 20-bit address is given in the instruction by the expression BYTE PTR ss:[bp+10h]. The address computation mechanism is exactly similar to that of the instruction mov al, BYTE PTR ds:[bx+10h] but this time using the diagram of Fig-2.30.

2.4.D3 Instruction Stream Byte Queue (ISBQ) A program is a collection of assembly instructions like:
mov mov add mov mov hlt al, 23h ah, 45h al, ah bx, 3000h BYTE PTR ds:[bx+20h], al

; result is saved in CSM

The above six-line program adds the numbers 23h and 45h and saves the result at location 03020h of the DSM. In order to execute the program, it has to be converted into machine code, which are:
01000 (0000:1000) - B0 23 B4 45 02 C4 BB 00 30 88 47 20 F4

Internal Processing Blocks of 8086

109

The above machine codes are stored as binary codes in consecutive memory locations of the CSM starting at location 01000h. There is no spaces between the bytes but are shown only for clarity. The bold indicates that this is the beginning code of this instruction. The CPU finishes the program by executing its constituent instructions one after another. This is to say that when the CPU finishes one instruction, the next instruction is ready for execution. Thus the CPU sees the program as a Stream of Instructions. Now, let us see the function of the ISBQ, which is a six-byte long FIFO (First-in First-out) type storage area and is located inside the BIU unit of the 8086. We know that the CPU can execute an instruction once its machine codes are within it. Therefore, the CPU has to perform repeated read operations on the external CSM during which the external bus remains busy. Assume that the CPU has brought inside its decoding unit all the machine codes for the instructions up to add al, ah. The CPU has started the execution of the instruction add al, ah and of course, it will take some finite time to finfish this instruction. After finishing this instruction, the CPU has to perform three more read operations on the CSM to read the machine codes (BB 00 30) of the next instruction, mov bx, 3000h. The CPU will spend some finite time (Say, t-Sec) to read these instruction bytes. Can we save this time to increase the throughput of the CPU? Yes! How? While the CPU is busy in executing the codes for the add al, ah instruction, the external bus (address bus, data bus and the control bus) is free (idle). Now, a separate circuit within the CPU (let us call it EXBUS for exciting external bus at idle time) could be triggered, which will engage the bus system to read instructions codes bytes from the CSM in ahead of time and keep them inside the ISBQ. Depending on the execution time of the current instruction, the EXBUS can read as many as six instruction code bytes from the external CSM. After the execution of the add al, ah instruction, the CPU looks into its internal ISBQ for the next instruction rather than looking for them in the external CSM locations. And there is a very good chance that the CPU will find them in the ISBQ. There is a saving of three machine cycle time and it is due to the introduction of the EXBUS circuit and the ISBQ unit within the 8086. The throughput (performance) of the CPU has speeded up. The ISBQ is flashed (emptied), when the CPU executes a jump instruction. Under this situation, the CPU will not find any pre-fetched instructions within the ISBQ. Now, the CPU looks into the external CSM for the instruction codes. Why is six-byte space chosen for the ISBQ? Is the six-byte size of the ISBQ is enough? In assembly language, it generally appears that the size of the instructions remain limited within six-bytes. However, the author has found the following ASM instruction, which is of seven-byte length. If situation does arise for the CPU to execute such instruction, then serious question could be raised about the under size of the ISBQ!
mov WORD PTR ss:[bx+di+07FFh], 1234h : 36 C7 81 FF 07 34 12

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2.4.D4 Control System It is a very complex subsystem [Fig-2.43, P114] consisting of the following units: i. Instruction Register: To hold the opcode (s) of an instruction ii. Instruction Decoder:

Chapter - 2

It decodes the opcode (s) and extracts the following information: a. The size (in byte) of the current instruction b. The addressing mode (how to compute the address) To hold the 20-bit address of the target locations in DSM, ESM and SSM. To generate complex timing functions for the Sequence Generator (Control Matrix) of the CPU.

iii. Micro-code Dictionary: It helps the instruction decoder to extract information. iv. Address Temporary Register: v. Timing Logic:

2.4.D5 Arithmetic and Logic Unit It contains all the necessary circuitry to accomplish the following functions: i. Unsigned and signed arithmetic operations on 8-bit and 16-bit data. The operations could be: a. Addition with carry b. Subtraction with borrow c. Multiplication d. Division e. Decimal Adjustment after addition of BCD numbers f. Decimal adjustment after subtraction of BCD numbers g. Decimal adjustment after multiplication of BCD numbers h. 2s Complement ii. Logical operations on 8-bit and 16-bit data. The operations could be: a. Logical OR b. Logical XOR c. Logical AND d. Logical Negation (NOT) e. Arithmetic Shift f. Arithmetic Rotation

iii. The ALU operation updates nine independent active flag bits of the flag register of the 8086. The flag bits are:
Carry Flag (CF) Zero Flag (ZF) Interrupt Flag (IF) Parity Flag (PF) Sign Flag (SF) Direction Flag (DF) Auxiliary Flag (AF) Trap Flag (TF) Overflow Flag (OF)

iv.

The input data for the ALU operation can be either from any permissible 8-bit or 16-bit registers or from an external memory location or port. The result of the ALU can be placed on any permissible 8-bit or 16-bit registers or onto an external memory location or onto a port.

v.

Address Computation of Memory Locations

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2.4 (e)

2.4.E1 Introduction The machine codes of a program are stored in consecutive memory locations of CSM. The 20-bit addresses of the CSM locations, which hold the instruction codes, are automatically computed using the CS- and the IP-registers. Therefore, a programmer is not concerned much about the computation of the addresses of the CSM location unless she has some known data somewhere in CSM. During subroutine or interrupt call, the CPU automatically saves the return address onto SSM. The CPU uses the SS- and the SP-register to compute the addresses of the memory locations of the SSM into which the return address is to be saved. Therefore, a programmer is not concerned much about the computation of the addresses of the SSM location unless she has some known data somewhere in SSM. A programmer is very much concerned about her data. A program works on data. The program tells the CPU what to do with the data. The data are kept in the memory locations of the external Data Segment Memory (DSM) and ESM. The CPU accesses (reading it or modifying it by performing read-modify-write operation) a data byte of a memory location by knowing or computing the address of that location. The address of a memory location is an unsigned 20-bit value, which is composed of segment base address and offset. The offset part of the address, which is always a 16-bit value, is known as Effective Address (EA). The 20-bit value of the address is called Physical Address (PA). 2.4.E2 Addressing Mode Addressing Mode refers to the various ways of knowing or computing the address of a memory location or port location in order to access its content. There are basically three types of addressing modes and these are: (i) Immediate Addressing Mode. In immediate addressing mode, the data is a part of the instruction. It is the opcode of the instruction from which the CPU automatically knows the address of the data location. In this addressing mode, the data resides in the CSM location(s). Examples: a. 01000 (0000:1000) - mov al, 23h : B0 23 In this example, the data, which will enter into the al-register, is 23h. The data is an integral part of the instruction mov al, 23h. The opcode (operation code) of the instruction is B0, which is located in CSM location 01000h. The associated data is 23, which is located in the next immediate location of address 01001h. Thats why, the immediate addressing mode name is there! b. 01000 (0000:1000) - mov al, BYTE PTR ds:[bx] : 8A 07 In this example, the data, which will enter into the al-register, is not a part of the opcode. This is to say that the data is not located in any CSM location following the opcode locations. Therefore, this is not an immediate addressing mode. This is an example of an indirect addressing mode, where the address of the data location is computed from the values of the ds- and the bx-registers.

Address Computation of Memory Locations

112

Chapter - 2 (ii) Direct Addressing Mode In direct addressing mode, the 16-bit offset part (Effective Address) or the 20-bit physical address of a memory location is directly given in the instruction. However, this type of addressing mode is not allowed in the 8086 system for memory reference instructions like: mov al, BYTE PTR ds: [bx+si]. a. 01000 (0000:1000) - mov [3000h], al is not allowed. b. 01000 (0000:1000) mov 03000h, al is also not allowed. But, the 8086 architectures allow direct addressing mode for data read/write operations with fixed ports. In direct addressing mode, the port addresses are directly given in the instructions. For example: a. in al, 30h ; data is read from a fixed port whose address id 30h b. out 30h, al ; data is written into a fixed port whose address is 30h (iii) Indirect Addressing Mode In indirect addressing mode, the 20-bit PA (or 16-bit EA) of a memory location is indirectly specified using suitable registers as per diagram of Fig-2.32. The 8086 uses indirect addressing mode to access variable ports. The 16-bit address of a variable port is always passed via the dx-register. For example: a. in al, 3600h ; is not a valid instruction to read from a variable port b. mov dx, 3600h in al, dx ; valid instruction to read data from a variable port

2.4.E3

Address Computing Chart

Figure-2.41: 20-bit Physical and 16-bit Effective Address Computing Chart [2]

Address Computation of Memory Locations

113

The diagram of Fig-2.41 depicts the possible ways of computing the 20-bit physical address of a target location to read its content. In order to create correct and optimum assembly instructions, it is recommended to consult the diagrams of Fig-2.41 and 2.32 together. The target location may reside in any one of the four external memory segments, which are CSM, DSM, SM and SSM. The possible offset pointer registers are: DI, SI, BP and BX. The absence of the IP- and the SP-registers in the diagram indicates that these two registers are not available to the programmer for accessing a memory location. The diagram indicates that a displacement of either 8-bit or 16-bit value could be added with the pointer register while creating the expression for the address. The interpretation of the displacement is: i. If the displacement is declared as an 8-bit data (d8), it will always be taken as unsigned positive value. When the MS-bit of the d8 is appears to be LH (like 80h FFh), then 00 would be appended to its left to keep it still as an unsigned number. Examples:
mov mov mov WORD PTR ds:[bx+di+7Fh], 1234h : C7 41 7F 34 12 WORD PTR ds:[bx+di+80h], 1234h : C7 81 80 00 34 12 WORD PTR ds:[bx+di+0FFh], 1234h : C7 81 FF 00 34 12

ii.

If the displacement is declared as a 16-bit data (d16), it will always be taken as signed 2s complement value to cover the range of: -32768 (8000h) to +32767 (7FFFh). If d16 is given as FFFFh (-1), then it would be coded as FF (-1) in the instruction to reduce the number of code bytes. Examples:
mov mov mov mov BYTE BYTE BYTE BYTE PTR PTR PTR PTR ds:[bx+7FFFh], 1234h ds:[bx+8000h], 1234h ds:[bx+0EFFF], 1234h ds:[bx+0FFFFh],1234h : : : : C7 C7 C7 C7 41 81 81 41 7F 80 FF FF FF 00 EF 34 34 12 34 12 34 12 12

2.4.E4 Summary of Indirect Addressing Modes The following table of Fig-2.42 contains all possible addressing expressions made from the diagram of Fig-2.41 and 2.32. The expressions would ultimately be evaluated to 20-bit values when combined with the segment registers to refer to physical memory locations in the specified memory segment. Unless segment override prefix is declared, all expressions would be attached with DSM (Data Segment memory) and DSR (Data Segment Register) and as per Fig-2.32. The exception is for the expressions that contain BP-register - they are associated with SSM (Stack Segment memory) and SPR (Stack Pointer Register).
Memory Segment Association DSM DSM DSM DSM DSM SSM SSM SSM Segment Register Association SSR SSR SSR SSR SSR SPR SPR SPR Table 2.9 Effective Address of the Memory Location [bx] [si] [di] [bx + di] [bx + si] [bp] not allowed! [bp + di] [bp + si] [bx + d8] [si + d8] [di + d8] [bx + di + d8] [bx + si + d8] [bp + d8] [bp + di + d8] [bp + si + d8] [bx + d16] [si + d16] [di + d16] [bx + di + d16] [bx + si + d16] [bp + d16] [bp + di + d16] [bp + si + d16]

Figure-2.42: Table Showing 23 Possible Indirect Memory Addressing Modes for 8086

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2.5 (a) Conceptual View of the Internal Architecture of 8086

Chapter - 2

Print page: p114.doc

Figure-2.43

Conceptual View of the Internal Architecture of 8086

115

Let us examine the diagram of Fig-2.43 and see that it contains almost everything of the Internal Architecture those are tightly related with the working principles of the 8086 microprocessor. The Working Principles of a microprocessor refers to the ways of: i. Generating the 20-bit address of the external Code memory for reading instructions after power up reset. ii. Splitting an instruction into its constituent parts - Opcode and Operand. iii. Decoding the opcode and then planning for the next action. iv. Generating the 20-bit address of the external Data Memory for reading/writing data. v. Generating addresses for the fixed ports and the variable ports. vi. Performing arithmetic/logical operations on data and save the result into internal registers or external memory. vii. Commanding the Control Matrix for deciding which one to do out-of-many alternatives. viii. Collecting starting address of an Interrupt Sub Routine (ISR) or Subroutine (SUR). ix. Saving the Return Address (Radr) and other Critical Data during ISR or SUR calls. x. Releasing the bus to a requesting master for DMA (Direct Memory Access) action. The author believes that the readers will make a careful study on the diagram of Fig-2.43 as per following outlines in order to acquire a Solid Understanding and Convincing Feeling that the Internal Architecture Should be As it has been Shown in Fig-2.43 so that the 8086 can work as a Sequence Generator. A sequence generator is a complex machine, which generates all the necessary timing functions for its constituent hardware modules to accomplish tasks like: (a) Reading/writing on memory/port, (b) ALU operations, (c) Responding to external/internal interrupts, (d) Conditional/unconditional branching, (e) Releasing the bus to a requesting master and (f) Remaining in idle/freeze/waiting mode. In Section-2.5 (b), we will write ASM Codes wherever possible to verify that our Conceptual Understanding so far acquired on the internal architecture of 8086 makes sense.
1. U1 : Program Counter A Program Counter (PC) is an unsigned binary up counter, which generates address of the next memory location from where the CPU will read the next byte of the instruction. In 8086, the PC is a 20-bit counter and is made up of the CS-register and the IP-register. At power up, the U12 module puts the value FFFFh into the CS-register and 0000h into the IP-register. The CPU shifts the CS-register to the left by 4-bit and then add the IP-register to get FFFF0h [Fig-2.28]. This is known as Boot (Startup) Location/Address and is placed on the ABUS. 2. U2: Instruction Stream Byte Queue (ISBQ) The 8-bit content of the memory location FFFF0h (the Boot Location) is an opcode (this is not program data) and enters into the ISBQ. The ISBQ can queue as many as six instruction bytes. An instruction is composed of opcode and operand. The opcode (up to 3 bytes) enters into the Opcode Register and the operand (up to 4 bytes) enters into the Data-Address Register (U5).

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3.

Chapter - 2
U3: Opcode Register In 8086, an opcode could be as large as 3-byte (example: mov WORD PTR cs:[bx+di+07FFh], 1234h : 2E C7 80 07 FF 12 34). The CPU will not take any action (performing the current task) until all the bytes of the opcodes have entered into the Opcode Register and then into Opcode Decoder. U3A: Opcode Decoder The 1st byte (2E) of the opcode enters into the opcode decoder and gets interpreted with the help of Internal Micro-cod Dictionary. The Control Matrix understands that another opcode byte is required to understand the full meaning of the current instruction. The 2nd byte (C7) of the opcode enters into the opcode register. Now, the codes 2E C7 are jointly decoded and the control matrix understands that one more and the last opcode byte is required. The opcode byte (80) enters into the opcode decoder. Now, the codes 2E C7 80 are jointly decoded and the control matrix understands that the current instruction is of 7-byte long and the remaining 4-byte constitute the operand part. The opcode decoder also extracts the following information for the control matrix: (a) The current instruction is a WORD (16-bit) data write instruction into the CSM (b) The 20-bit address of the destination location should be computed as follows and the control matrix should generate the necessary timing functions accordingly. i. The next two byte (07 FF) of the operand must be added with the contents of cs-, bxand di-registers. The value should be kept into the Data-Address Register. (c) The last two byte (12 34) of the operand is the 16-bit data that should be written into the destination location.

4.

5.

U4: Control Matrix (CM) It generates all the necessary timing functions (read, write and sequencing signals) so that the whole machine advances according to the directives coming out-of-the opcode decoder. U5: Data-Address Register (DAR) The 1st two byte (07 FF) of the operand enters into the DAR and then enters into the 16-bit temporary register (TR16) of U6. The TR16 is added with CS-, bx- and di-registers. The resultant 20-bit value enters into the DAR as an address. The last two byte (12 34) of the operand enter into DAR and then into the TR16 of U6. The DAR asserts the address on the ABUS. The CM puts the TR16 on the DBUS and then generates the WR/-signal. The data 1234h is written onto the target CSM location. U11: ISR Address Generator During interrupts, the CPU receives the ITC code and computes the addresses of the four RAM locations that hold the segment and offset parts of the beginning address of ISR. For NMI interrupt, the ITC code is 02h. The memory locations that hold the address of ISR are: 00008h (0002h x 4), 00009h, 0000Ah, and 0000Bh. The addresses are asserted on the ABUS via DAR. The contents of these four locations constitute the starting address of the ISR. The segment and the offset part of the ISR address enter into CS- and IP-register via DAR. The program control transferred to the ISR. U8: Arithmetic/Logical Unit (ALU) It performs arithmetic and logical operations on 8- and 16-bit data. The result is accordingly routed into the 8- or 16-bit register. The statuses of the flag bits of the flag register (FR) are also affected by the result of the ALU [Fig-2.23]. The result of the ALU can also be stored into external memory locations. U10: External Stack (SSM) During SUR/ISR calls, the return addresses are saved onto the external SSM. The FR any other registers may also be saved onto the stack using PUSH instructions. U9: Flag Register (FR) There are nine active bits in the FR, which are single bit locations. These bits can assume either 0 or 1 depending on the result of the ALU. For example, C-bit assumes LH when a carry is generated after an addition. The CPU checks the C-bit to know that the result of addition is greater than 8- or 16-bit.

6.

7.

8.

9.

10.

Instruction Fetch and Execution Mechanism of Intel Architecture

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2.5 (b)
2.5.B1

Instruction Fetch and Execution Mechanism of Intel Architecture

Moving an Immediate Data into Register
mov mov al, 45h al, 45h : B0 45

Instruction: Coding: 01000 (0000:1000) Meaning: Fetch-Execution:

The data for the destination register comes from a memory location, which just follows the location that holds the opcode (See coding above and diagram below). Shown below in Fig-2.44.

Figure-2.44: Explaining Fetch-Execution Mechanism of mov al, 45h Instruction [17] 1. 2. 3. The PC asserts the address 01000h on the address bus. The CM (Control Matrix)sends the RD/-signal to the memory chip. The opcode B0 (content of CSM memory location 01000h) enters into the opcode decoder. The opcode is interpreted and the CM understands that current instruction is of two bytes long. The CM also understands that the content of the next location is a data and it must go into the al-register. The CM increments the PC, which is now 01001h. The address is put on the ABUS. The CM generates the RD/-signal. The content (45) of the memory location 01001h enters into the al-register via the DAR register.

4. 5. 6.

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2.5.B2 Moving an Immediate Data into a Memory Location
mov mov BYTE PTR ds:[bx+10h], 45h BYTE PTR ds:[bx+10h], 45h : C6 47 10 45 Instruction: Coding: 01000 (0000:1000) Meaning:

Chapter - 2

The data for the destination memory location comes from a memory location, which just follows the location (s) that holds the opcode bytes (instruction bytes). Assume that ds = 0000h, bx=3000h and then 45h would be stored at location 03010h Shown below in Fig-2.45.

Fetch-Execution:

Figure-2.45: Explaining Fetch-Execution Mechanism of mov BYTE PTR ds:[bx+10h], 45h Instruction 1. 2. 3. The PC asserts the address 01000h on the address bus. The CM sends the RD/-signal to the memory chip. The opcode C6 (content of CSM memory location 01000h) enters into the opcode decoder. The opcode is interpreted and the CM understands that current instruction has an opcode of two bytes long.

Instruction Fetch and Execution Mechanism of Intel Architecture

4. 5. 6. The CM increments the PC, which is now 01001h. The address is put on the ABUS. The CM generates the next RD/-signal. The opcode 47 (content of the memory location 01001h) enters into opcode decoder. The opcodes C6 47 are jointly decoded and the CM extracts the following information: i. ii. 7. 8. 9. 10. 11. 12. 13. 14. 15.

119

The current instruction is 4-byte long. Therefore, two more read operations must be carried out to bring the remaining two byes (10 45) information from the memory. Addressing Mode is determined as Immediate, which means that the last information byte (45) is the data for the destination.

The CM increments the PC, which is now 01002h. The address is put on the ABUS. The CM generates the RD/-signal. The data 10h (8-bit displacement) enters into the DAR from where it enters into TRA8 of U7. The CM increments the PC, which is now 01003h. The address is put on the ABUS. The CM generates the RD/-signal. The data byte 45h comes from the CSM and then enters into the TRB8 of U7. The content of ds, bx and TRA8 are added together to get the destination memory address as: 03010h. The resultant address is asserted on the ABUS. The contents of TRB8 (45) is placed on the DBUS. The CM sends data write signal to the memory chip. The data byte 45h enters into the DSM location: 03010h. BYTE

The above-mentioned 15 steps are required to accomplish the task defined by the instruction: mov PTR ds:[bx+10h], 45h. The instruction execution cycle consists of: i. Four read operations (1-3, 4-6, 7-9 and 10-12). ii. One write operation, which occurs in the background.

2.5.B3 Adding Immediate 16-bit Data with Memory Contents and Saving Result in Memory add WORD PTR ds: [bx+1234h], 5678h Instruction:
Coding: 01000 (0000:1000) Meaning: 81 87 12 34 5678 The 16-bit data for the addition process comes from two consecutive memory locations, which just follows the location (s) that holds the opcode bytes (instruction bytes). Assume that ds = 0000h, bx=3000h, (04235h)= 10h, (04234h) = 12h. After the addition, 66h (56h + 10h) would be stored at location 04235h and 8Ah (78h + 12h) would be stored at location 04234h. Fetch-Execution: Instruction Cycle: Fig-2.46. a. Six read operations to read all the instruction bytes. b. One machine cycle in the background to store the displacement into TRB16. c. One WORD Read operation in the background to bring the data 5678h (the contents of memory locations 031235h and 031234h) into TRA16. d. One machine cycle in the background to add the numbers. e. One WORD Write operation in the background to store the result into DSM.

The displacement part 1234h is placed inside the TRB16 register of U6. The contents of ds, bx and TRB16 are added together to find the target location address 04234h. The 16-bit immediate data (5678h) is read and kept in TRA16. After addition, the 16-bit result is stored into TRA16 register and then into external memory locations. Additional instructions would be required to save carry if any.

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Chapter - 2

ABUS
81 3 87 6 34 9 12 12 78 15 56 18 12 10 21

Address

DBUS
d
d, i

Data
01000 01001 01002 01003 01004 1 01005 4 10
0

U5
15 0 Data Buffer

U1
d
IP 19

Program Counter
CS 000,.,000 0000 1000 +

Data-Address Register

7
O D I T S Z A C P 0 0

13

21 18

15 12 9
15

16 DSM

22

3
81

U8

d
0

U2
Legend:
a = address d = data ( 8- or 16-bit c = control (timing) op = opcode i = Instruction Itc = interrupt type code`
6 5 4 3 87

OUT

22
04235 10, 66 12, 8A

22
IN
7 al ah bl bh cl ch dl dh TRA8 TRB8 ax cx dx bx = 3000 si di sp bp

8A 66

Instruction Stream Byte Queue ISBQ)

IN

ALU
1012

668A 5678
0

04234

U3

op

U7

03000

24 16 C6 47 Opcode (as large as: 3x8 = 24 bit)

CSM
01005 01004 01003 56 78 12 34 87 81

U3A

Opcode Register op 24 Opcode Decoder c

04234

01002 01001 01000

23

U4
Timing and Control Signals to All Internal Units c Timing Logic and Memory/Port Control Matrix 21 25 2 5 7 8

12A

1234

+
0000

18A

5678 1012 WR/

15

TRA16 = 5678 , 668A ds = 0000 es ss cs TRB16 = 1234, 1012 0

11 14 17 20

RD/

U6
Control
40c : 11-08 : GM

CBUS

Figure-2.46: Explaining Fetch-Execution Mechanism of add WORD PTR ds:[bx+1234h], 5678h Instruction

Working Principles: At the 1st machine cycle, the CPU reads the opcode byte 81 from CSM, which enters into the opcode decoder and gets interpreted. The CPU understands that there is a 2nd opcode byte, which the CPU reads at the 2nd machine cycle. Now, the opcode 81 87 is jointly decoded and reveals the following information: i. The current instruction is of 6-byte length
ii. iii. iv. The next two instruction bytes (1234h) is a displacement and must be used for PA calculation The 1st 16-bit data has been given in the current instruction as the last two bytes (5678h). The 2nd 16-bit data is in the external memory location.

At the 3rd and 4th machine cycles, the CPU reads the displacement (1234h) and keeps at TRB16. At the 5th and 6th machine cycles, the CPU reads the 1st 16-bit data (5678h) and places it into TRA16. At a background machine cycle, the CPU computes and asserts the physical address of the memory location that holds the 2nd 16-bit data. The 2nd data enters into TRB16. The CPU adds the 16-bit numbers and then writes the result on the destination memory locations.

Instruction Fetch and Execution Mechanism of Intel Architecture Fetch-Execution Events: A. 1st Machine Cycle :1. 2. 3. 2nd Machine Cycle :4. 5. 6. 3rd Machine Cycle 7. 8. 9. 01000h ABUS RD/ CBUS Receiving 1st byte of opcode (81) 01001h ABUS RD/ CBUS Receiving 2nd byte of opcode (87)

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B.

C.

01002h ABUS RD/ CBUS Receiving 3rd byte of instruction (lower 8-bit of displacement: 34)

D.

4th Machine Cycle :10. 01003h ABUS 11. RD/ CBUS 12. Receiving 4th byte of instruction (upper 8-bit of displacement: 12) Background M/C 12A 16-bit displacement 1234h enters into TRB16 of U7

5h Machine Cycle 13. 01004h ABUS 14. RD/ CBUS 15. Receiving 5th byte of instruction (lower 8-bit of immediate data 78) 6th Machine Cycle 16. 01005h ABUS 17. RD/ CBUS 18. Receiving 6th byte of instruction (upper 8-bit of immediate data: 56). Background M/C 18A Immediate 16-bit data 5678h enters into TRA16 Background M/C 19. Compute 20-bit address (ds:[bx+TRB16) : 04234h ABUS 20. RD/ CBUS (for word read) 21. Receive word data (1012h) from two DSM locations and save into TRB16. Background M/C 22. Adding two 16-bit data: TRA16 + TRB16 TRA16 Background M/C 23. Target location address: 04234h ABUS 24. 16-bit content of TRA16 is placed on DBUS 25. WR/ CBUS (for word write)

F.

Computation of Execution Time: 1. Assume 8086 Operating Clock: 2. 3. 4. 5. So, T-state: Time for Real Read Machine Cycles: Time for Background M/C: Total Execution Time:

2048 KHz (1/2048) x 10-3 s 6 x 3 x (1x2048) x 10-3 5 x 3 x (1x2048) x 10-3 T1 + T2 = 16.113 x 10-6 s = 488 ns = 8.789 x 10-6 s = T1 = 7.324 x 10-6 s = T1 = 16.113 s

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2.6 (a) Maximum Mode Operation of the 8086 Microprocessors (MAX86)

Chapter - 2

2.6.A1 Introduction The 8086 microprocessor has two modes of operation the minimum mode (MIN86) and the maximum mode (MAX86). In MIN86 mode, the CPU works alone and generates all the necessary bus signals to accomplish data read/write operations with memory and port devices. The pin/signal diagrams for the MIN86 are depicted in Fig-2.1, 2.2 and 2.3. In MIN86 mode, the 8086 will not work in parallel with a second processor like 8087 (called coprocessor). Examples of coprocessors are: 8087 Floating Point Unit (FPU) and 8089 IO coprocessors. Parallel operation of 8086-8087 requires complex timing functions, which must be asserted using the physical pins of the 8086. The conventional 40-pins of the 8086-chip is not enough to accommodate all the functions required by both MIN86 and MAX86. To keep the pin counts to 40 and at the same time operating the 8086 in the required mode, the chip designer has attached a pin named MN-MX/ with the chip. Attachment of LH signal with the MN-MX/ pin puts the 8086 into its MIN86 operation. To operate the chip into its MAX86 mode, a LL signal is attached with the MN-MX/ pin. 2.6.A2 Physical Pin Diagram of MAX8086 When the MN-MX/ pin of the 8086 is tied with the 0V, the 40-pins of the chip exhibit signals as shown in Fig-2.47.

Figure-2.47: physical Pin Diagram of MAX8086

In Fig-2.47, we find that the chip is not generating the WR/, M-IO/, BHE/, HOLD, HLDA, DEN/ and INTA/ signals. In stead, the chip generates status signals viz., S0/, S1/ and S2/, which must be decoded using an external Bus Controller (8288) [Fig-2.48] to get the required memory/port control signals. In MAX86 operation, the chip also generates few special signals like RQ/-GT0/, RQ/-GT1/, QS0, QS1 and LOCK/. These signals are essential for the parallel operations of 8086 with other coprocessors.

Maximum Mode Operation of the 8086 Microprocessor (MAX86) 2.6.A3 8288 Bus Controller
U3 8288 ALE DEN MC/PD DT/R AEN IOB CEN CLK S2 S1 S0 INTA AIOW IOW IOR AMW MWT MRD 5 16 17 4 14 12 11 13 8 9 7 IOWR/ IORD/ MEWR/ MERD/ ALE DEN MC-PD/ DT-R/ INTA/ AIOWC/ IOWC/ IORC/ AMWC/ MWRC/ MRDC/

123

GND +5V +5V CLK S2/ S1/ S0/

6 1 15 2 18 3 19

Figure-2.48: Schematic Diagram for the 8288 Bus Controller

The author discovered the schematic diagram of Fig-2.48 for the 8288-bus controller while putting efforts for the parallel operation of MAX86 with the 8087 in the year of 1997. The meaning of the signals AEN/, IOB and CEN were not very clear during that time but he managed to determine by trial and error that the logic values as indicated in Fig-2.48 should be attached with the input pins in order to make it work. The 8288-bus controller is a dynamic chip, which means that the chip works in synchronism with the operating clock (CLK) of the CPU. The chip produces the indicated output signals in response to the excitation of S0/, S1/ and S2/ signals as per following truth table.
Instruction Execution -------------in d, s out d, s hlt -------------mov d, s mov d, s ------------Table-2.10 MAX86 Bus Activities S0/ Processor State 0 Interrupt Acknowledgement in response to IRQ over INTR-pin 1 Read Data from Input Port 0 Write Data into Output Port 1 0 1 0 1 Halt Read Instruction Byte from CSM Read Data Byte from DSM Write Data into DSM -----------------------------------------Command Signals Generated by 8288 INTA/ (Interrupt Acknowledge) IORC/ (IO Read Control) IOWC/ (IO Write Control) AIOWC/ (Advance IOWC) --------------------------------MRDC/ (Memory Read Control) MRDC/ (Memory Read Control) MWTC/ (Memory Write Control) AMWC/ (Advance MWTC) ---------------------------------------------

S2/ 0 0 0 0 1 1 1 1

S1/ 0 0 1 1 0 0 1 1

Figure-2.49: Table Showing Command Signals Generated by 8288 in Response to MAX86 Status Signals

The CPU executes an instruction by reading its code byte(s) from Code Segment Memory (CSM). Here, the CPU is making a read operation on the external memory and hence the Memory Read signal is generated by the 8288. The 8288 generate advance write control signals AMWC/ and AIOWC/. These signals are connected with the physical Write Signals (pins) of the memory and IO devices of a system. These signals are made available to initiate early write procedures within the storage devices and thus prevent the microprocessor from entering into unnecessary wait state.

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2.6 (b) Bus-Structure Pin Diagram of MAX8086

Chapter - 2

Figure-2.50: Bus-structured Pin Diagram for the MAX8086

Depending on the functional similarities of the 40-pin of the MAX86 can be grouped as follows:
1. Time Multiplexed Address/Data Bus Address Lines : A00 A15 Data Bus : D00 D15 Time Multiplexed Address/Status Queue Status Bus Status DMA Lines CPU Control Lines Interrupt Request Line Interprocessor Communication Line Ungropued : AD00 AD15 (16)

: A16 A19 / S3 S6 : QS0 QS1 : S0/ - S2/ : RQ/-GT0/, RQ/-GT1 : MN-MX, READTY, RESET, CLK, Vcc, GND : NMI, INTR : TEST/ : BHE/-S7/, RD/, LOCK/

(4) (2) (3) (2) (7) (2) (1) (3)

2. 3. 4. 5. 6. 7. 8.

Brief Functional Description of MAX8086 Pin Signals

125

2.6 (c)

Brief Functional Description of MAX8086 Pin Signals

Signal Names A19/S7 A16/S3 AD15 AD00 S2/ - S0/ Direction Output Out/InOut Output Functions - 1st Emits upper 4-bit of address and then emits CPUs internal status. - 1st emits lower 16-bit of address and then turns into bi-directional data lines to exchange data - Emits encoded bus status signals and muse be decoded using 8288 bus controller to extract the bus control signals. See Fig-2.48, 2.49. - The CPU sends data read command signal to the selected memory or port device, which reside on the local bus of the 8086. - Activates to select ODD bank of storage locations - LH configures 8086 to operate in Minimum Mode. LL configures 8086 to operate in Maximum Mode. - LH tells the CPU to come out of cycle stretching. - LH keeps the CPU in the reset state. Transition from LH to LL initiates the start of the CPU. - Pulse train for the operating frequency of the CPU. - +5V Power supply for the CPU. - To sink the source current. - To receive nonmaskable external interrupt signal. - To receive maskable (deniable) external interrupt. - To establish communication with coprocessor (8087, 8089) during maximum mode operation. - Emits various status signals of the CPU during program execution being time multiplexed. - To prevent a bus master from requesting the CPU to release the bus. The CPU activates this signal before reading instruction from the CSM. - As Input Line (ReQust) by other bus master (DMA Device or Coprocessor) to tell CPU to release Bus. - As Output Line (GranT) , the CPU tells the bus requesting devices that the bus has been released for use. - An Input Line, the bus requesting device tells the CPU that it has used the bus and now it can be taken back by the CPU. - RQ/-GT0/ has the higher priority than GT/-GT1/ and these lines have internal pull-up resistors. - 8086 execute instructions from its ISBQ. The QS0 and QS1 provide information for external device like 8087 to track which instruction byte the 8086 is currently fetching from the queue or queue status.
QS1 0 0 1 1 QS0 0 1 0 1 Information No Operation Reads 1st byte of Instruction from Queue Queue Empty Reads next Instruction byte from Queue

Signals Category Multiplexed Address/Status , Address/Data (4+16 = 20) Bus Status (3)

Memory Read Control (2)

RD/

Out

CPU Control Lines (7)

BHE/ MN-MX/ READY RESET CLK Vcc GND (2) NMI INTR TEST/ S7 S3 LOCK/

Out Input Input Input Input Input Input Input Input Input Output Output

Interrupt Request Lines (2) Inter Processor Comm Line (1) Status Lines (5) Bus Control (1)

Request/Grant Lines (2)

RQ/-GT0, RQ/-GT1

In/Out

Queue Status (2)

QS0, QS1

Output

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2.6 (d) Parallel Operation of MAX8086 and 8087 Floating Point Unit

Chapter - 2

2.6.D1 Introduction to 8087 Math Coprocessor In this subsection, an overview of the 8087 math coprocessor (sometimes called Floating Point Unit, FPU) has been presented. A careful study and the practice of the example program (Page137) will hopefully allow us to write small and useful programs for the 8087. To acquire full programming control over the 8087, the readers are advised to study (i) Data Sheets, (ii) Application Notes and (iii) the Operation of MicroTalk-8087 Trainer. In scientific, engineering and business applications, we frequently deal with complex mathematical functions like trigonometric, logarithmic, and exponential and the similar. The values of these functions may be evaluated in the following ways: i. Write programs for the 8086 microprocessor and get them executed. This would be a slower process because of: (a) the program codes reside in the external memory and the CPU is required to bring them into its internal registers for execution, (b) the 8086 has the 16-bit architecture and can deal with only 16-bit numbers whereas the actual numbers could be as large as 80-bits or even more bigger. ii. Use a dedicated hardware circuit, which will take the input variables (the function name and the arguments) and deliver the result. This will be a quicker process because the hardware may be optimized to deal with numbers of required size. To evaluate the value of cos x, we are required to write a lengthy program for the series: cos x = 1 x2/2! + x3/3! x4/4! + The 8087 solve it easily. The 8087 has builtin hardware circuitry to compute the tangent of a variable. We execute FPTAN instruction to activate the built-in hardware circuit of the 8087 to find the tan x. After that the 8087 uses it Multiply, Add, Divide and Square Root instructions to compute cos x from the expression cos x = [(tan2x + 1) 1]. The 8087 is not a general-purpose microprocessor like 8086 though it has its own processor, highly specialized instructions and internal registers. It is a coprocessor and only works in conjunction with the 8086 microprocessor [Fig-2.62]. The 8086 knows which function it is supposed to evaluate and accordingly, it supplies data (function name and its arguments) to the 8087 via memory locations. The 8087 receive the parameters, computes the functions and makes the result available to the 8086 via memory locations for further processing. The data exchange events between the 8086 and the 8087 are synchronized and are accomplished through a series of 8086-8087 mixed up instructions. To find the value of cos x the instruction sequences are:
i. ii. iii. iv. v. vi. vii. viii. ix. Insert 8086 instructions to store x in memory Insert 8087 instruction to read x from memory Insert 8087 instruction to compute tan x Insert 8087 instruction to compute tan2x = (tan x * tanx ) Insert 8087 instruction to compute tan2x + 1 Insert 8087 instruction to compute (tan2x + 1) - 1 Insert 8087 instruction to compute [ (tan2x + 1) - 1] Insert 8087 instruction to write the result in memory Insert 8086 instruction to read the result from memory : mov BYTE PTR [bx], al : fld : fptan : fmul : fadd : fidiv : fsqrt : fstp DWORD PTR [bx] : mov ah, BYTE PTR [bx] DWORD PTR [bx]

Parallel Operation of MAX8086 and 8087 Floating Point Unit 2.6.D2 Physical Pin Diagram of 8087
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND AD14 AD13 AD12 AD11 AD10 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 AD01 AD00 NC NC CLK GND

127

8087

280a 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

Vcc AD15 A16-S3 A17-S4 A18-S5 A19-S6 BHE/-S7 RQ/-GT1/ INT RQ/-GT0/ NC NC S2/ S1/ S0/ QS0 QS1 BUSY RDY RST

Figure-2.51: Physical Pin Diagram of 8087 FPU

2.6.D3

Bus-structured Pin Diagram of 8087

Figure-2.52: Bus-structure Diagram for 8087 FPU

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2.6.D4 Internal Architecture of 8087

Chapter - 2

Figure-2.53: Internal Architecture of 8087 [1]

The 8087 is directly connected with the ABUS, DBUS, CBUS, Queue Lines and the Status Lines of the 8086 without any buffer [Fig-2.62]. By virtue of this direct connection, the 8087 can track the 8086 as to which instruction the 8086 is currently reading and decoding. Functions of Control Unit (CU): The CU receives instructions from the bus by tracking the queue lines. It performs data read/write operations with external memory by DMA action having borrowed the bus system from the 8086. It also executes the control instructions of the 8087. The CU is able to work independent of the Numeric Execution Unit (NEU). Numeric Execution Unit (NEU): The NEU executes all numeric instructions. The data path in the NEU is 84 bits wide (68 for fraction bits, 16 for exponent and sign bit). At the instant of executing an instruction, the NEU asserts LH on its BUSY-pin in order to inform the 8086 that the CPU shouldnt attempt fetching instructions until the 8087 have finished executing its instruction. Register Set (Register Stack) : There are eight registers and are designated as R0, R1,., R7 with corresponding addresses of 000B, 001B,., 111B. The registers set work as a Circular Queue. Status Word Register: The status word register reflects the overall operational status of the 8087. The 8087 can write the contents of the status register into memory from which the CPU can read it for examination. Control Word Register: There are several processing modes for the 8087, which are selected by writing control data into the control word register. The control words are first written into memory and then the 8087 read them from there.

Parallel Operation of MAX8086 and 8087 Floating Point Unit

129

2.6.D5 8087 Pin Classifications and Functions Multiplexed Address/Data Bus: In an 8086-8087 system [Fig-2.61], the 8086 works as the primary bus master and fetches instructions from the CSM both for itself and for the 8087. The 8087 collect its instructions from the ISBQ of the 8086 and perform data read/write operations with DSM locations as required. This is the situation when the 8087 become the secondary bus master and takes over the control of the bus from the 8086 in order establish direct communication with the memory devices. At the beginning of the bus cycle, the AD0 AD15 emits the lower 16-bit value (A0 A15) for the 20-bit address of the target memory location. And then, these lines turn into a 16-bit data lines (D0 D15) to exchange data with the memory locations. Multiplexed A16/S3 A19/S7 Lines: At the beginning of the bus cycle, these lines emit the upper 4bit value (A16 A19) of the 20-bit address of the target memory location. And then, these lines emit the status signals S3 S7. The definitions of the A16/S3 A19/S7 lines are the same as 8086. Multiplexed BHE/-S7 Line: At the beginning of the bus cycle, this line emits the BHE/ signal, which is used by the memory/port decoder to select the appropriate bank of memory/port. And then, the line emits CPU status signal S7. Queue Status Tracking Lines (QS1-QS0): Theses are the input lines and are directly connected with the corresponding QS1-QS0 lines of the MAX86. In normal situation, when the 8086 are busy in the internal processing, the bus system collects some instruction bytes from the external CSM in ahead of time and keeps them in the ISBQ [Fig-2.39]. At the same time, the 8087 also stores these instruction bytes in its internal queues. The QS1-QS0 lines help the 8087 to remain aligned (synchronized) all the time with that of the ISBQ queue of the 8086. Bus Status Signals (S0/-S2/): When the 8086 is the bus master; these lines are the input lines to the 8087. The 8087 monitor these lines and decode them internally to remain aware about their definition (read, write INTA/, Fig-2.49) for the current bus cycle. When the 8087 take over the control of the bus, the S0/-S2/ lines work as output lines and convey encoded information, which are decoded by the 8288 bus controller as per following definitions:
S2/(M-IO/) 1 1 S1/ 0 1 S0/ 1 0 Function Read data from memory Write data into memory

RQ/-GT/ (Bus Request/Grant Line): In the 8086-8087 system [Fig-2.62], the 8086 read the 1st data operand (one byte or one word) from the memory and pass it to the 8087. If this data operand is not enough for the 8087 to continue internal processing (for example: the fld DWORD PTR [bx]) dictates that the 8087 requires 4-byte data), the 8087 takes over the bus from the 8086 and accomplishes remaining data read operation by DMA action. The RQ/-GT/ line allows the 80868087 systems exchange handshaking as to the timing of the request-grant-release of the bus. Busy Line: The 8086 should not fetch instructions from the memory when the 8087 are busy. The 8087 informs its busy condition to the 8086 by asserting LH signal on its busy-pin, which is directly connected with the TEST/-pin of the 8086. The user forces the 8086 to execute the WAIT instruction so that it can monitor the TEST/-pin and keeps looping until the BUSY-pin is deactivated by the 8087. INT (Interrupt) Lin: INT line allows the 8087 to interrupt the 8086 while it detects any exception conditions during program execution. The error conditions are: (i) Invalid Operation, (ii) Overflow, (iii) Zero Division, (iv) Underflow, (v) Denormalized and (vi) Inexact Result.

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2.6.D6
R7 R6 R5 R4 R3 R2 R1 R0

Chapter - 2 Internal Registers of 8087

79 78 64 SIGN EXPONENT 63 SIGNIFICAND 0 111 110 101 100 011 010 001 000 2 0 1 0 15 CONTROL REGISTER STATUS REGISTER TAG WORD INSTRUCTION POINTER DATA POINTER 0

STACK POINTER

282b:GM:03/2005

Data Registers

TAG Field

Control-Status Registers

Figure-2.54: Internal Registers of the 8087 Math Coprocessor [2]

Data Registers: The 8087 has eight data registers as depicted in Fig-2.54. Each of the data registers is of 80-bit size and is composed of three fields: (i) Sign Field, (ii) Exponent Field and (iii) Significand Field. The registers have the symbolic names and numerical addresses as shown below:
Register Symbolic Names R7 R6 R5 R4 R3 R2 R1 R0 Register 3-bit Numerical Addresses 111 110 101 100 011 010 001 000

All data transfer operations between the 8086-8087-Memory occur through these eight registers. The R0-R7 registers work as Last In First out (LIFO) circular registers stack. After power up reset, the content of the stack pointer register is 000 and hence the Top of Stack (TOS) is the register, R0. In 8087 systems, the register that is currently the TOS, is referred to as ST(0) or simply ST. The TOS register, ST(0) is always a filled up location [Fig-2.55]. In 8087 systems, the stack grows towards registers with decreasing addresses. In the 8087 system, loading (reading from a memory location or copying from another stack register) data into the TOS is considered as push operation. In push operation, the stack pointer is automatically decremented by one and the data is written into the new ST(0). Transferring data from a TOS into a memory location or any other stack register is considered as a pop operation. In the pop operations, the data from ST(0) is copied to a destination and then the stack pointer is automatically incremented by one to obtain a new ST(0). Let us find better clarifications of these concepts with examples and diagrams:
i. After power up reset: see Fig-2.55 ST(0) is the register R0 or SR-0 (Stack Register 0) with address : 000 ST(1) is the register just one location down to ST(0). It is the register R1 (SR-1) with address 001. ST(2) is the register just two locations down to ST(0). It is the register R2 (SR-2) with address 010 . After the execution of the instruction : fld BYTE PTR [bx] See Fig-2.55 ST(0) is the register SR-7 with address : 111. ST(1) is the register one location down to ST(0) It is the SR-0 with address 000. ST(2) is the register two location down to ST(0). It is the register SR-1 with address 001.

ii.

Parallel Operation of MAX8086 and 8087 Floating Point Unit

131
0 111 110 101 100 011 010 001 000 ST(7) ST(6) ST(5) ST(4) ST(3) ST(2) ST(1) ST(0)

79 R7 R6 R5 R4 R3 R2 R1 R0

78

64

63

Figure-2.55: software Names of Stack Registers after Power up RESET

79 R7 R6 R5 R4 R3 R2 R1 R0 x 78 x 64 63 x 0 111 110 101 100 011 010 001 000 ST(0) ST(7) ST(6) ST(5) ST(4) ST(3) ST(2) ST(1)

Figure-2.55: Software Names of the Stack Registers after one PUSH Operation

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2.6.D7 Control Register

Chapter - 2

Figure-2.57: Definitions of Various Bits of the Control Registers of the 8087

2.6.D8

Status Register

Figure-2.58: Definitions of Various Bits of the Status Register of the 8087

Parallel Operation of MAX8086 and 8087 Floating Point Unit

133

2.6.D9 Introduction to Instruction of 8087 The mnemonics of the 8087 instructions begin with the character F, which stands for Floating Point Coprocessor. In the following discussion, the readers will notice that the most significant 5bit of the 8-bit opcode of the 8087 begins with the bit pattern of 11011. This unique bit pattern allows the 8086 believing that the instructions being fetched belongs to the 8087 and must not be executed by the 8086. The 8087 execute these instructions. In the 8087 system, writing data unto the stack registers is termed as Loading. Loading is considered as a Stack PUSH operation and the data is always copied at the Top of Stack, the ST(0). In the 8087, the ST(0) is always a filled up register. So, during a loading operation, the stack pointer is decremented by one so that the ST(0) can point to a vacant register into which data could be written. Likewise, reading data out of a stack register is termed as Storing. Storing is considered as a Stack POP operation and the data is always removed from the Top of Stack, the ST(0). In the 8087 systems, the ST(0) is always a filled up register. So, during a storing operation, the data is removed from the ST(0) and then the stack pointer is incremented by one so that the ST(0) can now point to a register, which is filled up. 2.6.D10 8087 Data Type The 8087 support the following data types:
Sno. i. ii. iii. iv. v. vi. vii. Name Word Integer Short Integer Long Integer Packed Decimal Short Real Long Real Temporary Real Size 16-bit (WORD) 32-bit (DWORD) 64-bit (QWORD) 80-bit (TBYTE) 32-bit (DWORD) 64-bit (QWORD) 80-bit (TBYTE) Comments 8087 convert it into 80-bit temporary-real format 8087 convert it into 80-bit temporary-real format 8087 convert it into 80-bit temporary-real format 8087 convert it into 80-bit temporary-real format 8087 convert it into 80-bit temporary-real format 8087 convert it into 80-bit temporary-real format 8087 convert it into 80-bit temporary-real format

2.6.D11 Classification of 8087 Assembly Instructions Data Transfer

Real fld fst fstp fxch Integer fild fist fistp Packed Decimal fbld fbstp

Arithmetic
Addition fadd, faddp fiadd Subtraction fsub, fsubp fisub Reversed Subtraction fsubr, fsubrp fisubr Multiply fmul, fmulp fmul Division fdiv, fdivp fidiv Reversed Division fdivr, fdivp fidivr Misc. Arith fsqrt fscale fprem frndint fxtract fabs fchs

Compare
fcom fcomp fcompp ficom ficomp ftst fxam

Transcendental
fptan fpatan f2xm1 fyl2x fyl2xp1

Processor Control
finit / fnint fdisi / fndisi feni / fneni fldcw fstcw / fnstcw fssw / fnstsw fclex / fnclex fsave / fnsave frstor fstenv / fnstenv fldenv fincstp fdecstp ffree fnop fwait

Constant Loading
fldz fld1 fldpi fld2 fldl2e fldlg2

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2.6.D12 Summary of 8087 Assembly Instructions Data Transfer Instructions
fbld fbstp fild fist fistp Load 10-byte packed decimal on stack Store 10-byte packed decimal and pop Load 2-, 4-, or 8-byte integer on stack Store 2- or 4-byte integer Store 2-, 4-, or 8-byte integer and pop stack fld fst fstp fxch

Chapter - 2

Load 4-, 8- or 10-byte real on stack Store real Store 4-, 8-, or 10-byte real and pop stack Exchange contents of stack element

Arithmetic
fabs fadd faddp fchs fdiv fdivp fdivr fdivrp fiadd fidiv fidivr fsubr fxtract Take absolute value of Stack Top Add real Add real and pop stack Change sign on the top stack element Divide real Divide real and pop stack Revised real divide Reversed real divide and pop stack twice Add 2- or 4-byte integer 2- or 4-byte integer divide Reversed 2- or 4-byte integer divide Reversed real subtract Extract exponent and Significand fimul fisub fisubr fmul fmulp fprem frndint fscale fsqrt fsub fsubp fsubrp 2- or 4-byte integer multiply 2- or 4-byte integer subtract Reversed 2- or 4-byte integer subtract Multiply real Multiply real and pop stack Partial remainder Round to Integer Scale Square root Subtract real Subtract real and pop stack Reversed real subtract and pop stack

Transcendental Instruction
f2xm1 fpatan fyl2pi Calculate 2x 1 Partial arctangent function Calculate Y log2 (x+1) fptan fyl2x Partial tangent function Calculate Y log2 x

fcom fcomp fcompp fxam

Compare Real Compare real and pop stack

Compare ficom ficomp ftst

Compare real and pop stack twice Examine top-of-stack element

2- or 4-byte integer compare 2- or 4-byte integer compare and pop stack Test top of stack

fclex fdecstp fdisi feni

Clear exception after WAIT Decrement stack pointer

Processor Control fninit fnsave fnstcw fnstenv

Disable interrupt after WAIT Enable interrupts after WAIT

Initialize processor, with no WAIT Save 8087 state (94 bytes) with no WAIT Store control word with no WAIT Store 8087 environment with no WAIT

Parallel Operation of MAX8086 and 8087 Floating Point Unit ffree fincstp finit fldcw fldenv fndisi fneni ffree fnop Free stack element Increment stack pointer Initialize processor after WAIT Load control word Load 8087 environment (14 bytes) Disable interrupts with no WAIT Enable interrupts with no WAIT Exchange top-of-stack element No operation Constant Loading fldln2 Load loge2 onto top of stack fldpi Load log2e onto top of stack Load onto top of stack fldz Load +0.0 onto top of stack Load log210 onto top of stack fnstsw frstor fsave fstcw fstenv fstsw fwait

135
Store 8087 status word with no WAIT Restore 8087 state ((94 bytes) Save 8087 state (94 bytes) after WAIT Store Control word with WAIT Store 8087 environment after WAIT Store 8087 status word after WAIT Wait for last 8087 operation to complete

fldi

Load +1.0 onto top of stack

fldl2e fldlg2

2.6.D13 Brief Description of Few Selected 8087 Instructions The 8087 support all possible addressing modes of the 8086 microprocessor. Data Transfer Instructions
Mnemonic fld Meaning Move at least 32-bit (DWORD) or 64-bit (QWORD) or 80-bit (TBYTE) data from memory locations or from any other stack element (stack register) onto to top-ofstack. Move 80-bit packed decimal number from meory locations onto the TOS. Move 80-bit data from TOS into another stack register or memory locations. If the destination is memory locations, then the number and its exponent will be rounded to fit in the destination memory locations. Examples fld DWORD [bx] fld QWORD PTR [bx] fld TBYTE PTR [bx+si+13h] fld ST(1) fbld TBYTE PTR [bx] fst fst fst fst DWORD PTR [bx] QWORD PTR [bx+si] TBYTE PTR [bx+si] ST(2)

fbld fst

Arithmetic Instructions
Mnemonic fadd Meaning Add 32-bit or 64-bit or 80-bit 80-bit real content of a stack element or memory locations with TOS and leave the result in TOS. 32-, 64- or 80-bit unsigned number of stack element or memory location is multiplied with the content of TOS. The result is left in TOS. The squre root of the content of TOS is extracted and the result is left in TOS. Examples fadd ST(0), ST(1) fadd QWORD PTR [bx] fadd TBYTE PTR [bx + si] fmul ST(0), ST(1) fmul DWORD PTR [bx] fsqrt

fmul

Fsqrt

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2.6.D14 Connection Diagram between MAX86 and 8087 for Data Exchange
GM:3/05:281b

Chapter - 2

M1: 8284
READY CLK RESET

M2: max8086

M3: 8087

RESET CLK READY TEST/

RESET CLK READY BUSY INT S2/ S1/ S0/

S2/ S1/ S0/

S0/ DEN/ DT-R/ RQ/-GT1/ RQ/-GT0/ QS1 QS0 A16/S4-A19/S6, BHE/-S7 AD8-AD15 AD0-AD7 +5

S1/

S2/

M4: 8288
ALE +5 RQ-GT1/ RQ/-GT0/ QS1 QS0 A16/S4-A19/S6, BHE/-S7 AD8-AD15 AD0-AD7

WR/ RD/

M7: Buffer

M6: Latch

Data Registers
SP BP DI SI DX CX BX AX 15 0

Data Registers
R7 R6 R5 R4 R3 R2 R1 R0 79 0

2x74LS245
D8-D15 D0-D7 A0-A7

3x74LS373
A8-A15 A16-A23 BHE/

Memoy Decoder, Read/Write Logic

F0000 - FFFFF : ROM 00000 - 0FFFF : RAM

RAM/ROM Memory System M5: DECODER-RAM-ROM

Figure-2.59: Connection Diagram among MAX86-8087-8288 for Parallel Operation

Working Principles: After power up reset, the 8086 take over the control of the bus and the 8087 remains in the passive state. If the 8086 have a data item to pass to 8087, the 8086 store the data item into a memory location from which the 8087 read it and store it into its internal register. The 8086 carry out the following steps to transfer a data item from its internal register into the register of the 8087.
i. ii. It stores the data into suitable RAM locations. Now is the time for the 8086 to inform the 8087 that there is a data item in memory location and it should read it. This happens this way: a. b. The 8087 has data read instruction like: fld dest, src. The machine codes of this instruction are kept in program memory in line with the instruction codes of 8086 (example program at P138). The 8086 reads the code bytes of the instructions fld dest, src from the program memory. As the code bytes appear on the data bus, they are also accepted by the 8086 and the 8087. Both processors decode the opcode of the instruction and the 8086 finds that the current instruction belongs to the 8087. The 8086 simply ignores it and waits until the 8087 has finished executing the instruction. The 8086 remains in the wait state until the TEST/-pin assumes LL state.

Parallel Operation of MAX8086 and 8087 Floating Point Unit

iii.

137

The 8087 executes the instruction fld dest, src and brings the data item from the memory into its internal register. The 8087 then asserts LL on its BUSY-pin and the 8086 comes out-of-wait state and fetches the next instruction from memory. The mechanism of how does the 8087 know the 20-bit address of the data item is explained below with the help of an example.

2.6.D15 Example Program (\mtk8086\p8087a.asm) Let us take an example to understand the data transfer mechanism between the 8086-8087Memory. The study may be carried out referring to Fig-2.59, 2.60, 2.61 and 2.62.
The data item 0000 0003h (32-bit) and 0000 0004h (32-bit) are kept in memory locations: 00474h 0047Bh in order to pass them to the internal registers of the 8087. The 8087 will read these data and then add them together. The 8087 will put the result (00007h) into memory locations: (0047Ch 0047Fh). The complete program codes are given below, which could be executed using MicroTalk-8087 trainer and then the destination memory locations could be examined for the value 00007h.
.8087 ; P8087a.asm): checking that data exchange correctly takes place among 8087-8087 1000 1001 1004 1007 100C 1011 1016 101B 101F 1023 1026 102A 90 9B DB BB C7 C7 C7 C7 9B D9 9B D9 9B D8 9B D9 F4 START: L1: E3 00 47 47 47 47 L1A: 0003 L2: 0000 0004 0000 L3: 47 74 L3A: L3B: 47 78 L3C: L4: C1 L4A: L5: 5F 7C L5A: L6: 04 74 76 78 7A nop finit mov mov mov mov mov fld fld fadd fstp hlt bx. 0400h WORD PTR [bx+74h], WORD PTR [bx+76h], WORD PTR [bx+78h], WORD PTR [bx+7Ah], DWORD PTR [bx+74h] DWORD PTR [bx+78h] ST(0), ST(1) DWORD PTR [bx+7Ch] ; initialize 8087 ; offset pointer init 0003h 0000h 0004h 0000h ; 1st 32-bit data ; 2nd 32-bit data ; 8087 reads 1st data ; 8087 reads 2nd data ; 8087 adds data ; 8087 puts result in memory

Figure-2.60: RAM Data Structure

Figure-2.61: 8087 Stack Data Structure

Working Principles of the program relating to 8086-8087 Synchronization: Explained in Section-2.8 [Q35] Working Principles of the program relating 8087-Memory DMA Operation: Explained in Section2.8 [Q34]

138
2.6 (e)

Chapter - 2

Connection Diagram of MAX8086-8087-Memory of MicroTalk-8087 Trainer

Print : p138.doc Figure-2.61

Schematic Diagrams of MicroTalk-8086 Learning/Dev System

139

2.7 Schematics of MicroTalk-8086 Learning/Dev System

2.7 (a) Schematics of CPU Subsystem
1 Vcc VCC RN2 4k7

RES/ Y1 VCC 17 16 D1 R3 5k R3 5k 11 100uF + C31 6 3 7 14 1 15 13 4 U1 8284 OSC PCLK RESET Y1=6.144MHz 1/6Y=1024KHZ RESET HLDA/ 1 18 17 14 13 8 7 4 3 RDY2 AEN1 AEN2 EFI CSYNC ASYNC F/C RDY1 VCC Vcc 8 5 10 2 12 33 U2 MIN-MX CLK READY RESET MIN86 INTA M-IO RD WR DT-R DEN ALE 24 28 32 29 27 26 25 6.144MHz R2 100

X1

X2

2 3 4 5 6 7 8 9

RES

CLK READY RESET PCLK OSC

CLK 1/3Y1 19 RDY 22 21

INTA/ M-IO/ RD/ WR/ DT-R/ DEN/ ALE

RDY1

U6 OE D7 D6 D5 D4 D3 D2 D1 D0 U7 1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 39 2 3 4 5 6 7 8 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 18 17 14 13 8 7 4 3 OE D7 D6 D5 D4 D3 D2 D1 D0 U8 1 OE D7 D6 D5 D4 D3 D2 D1 D0

74LS373 LE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 74LS373 LE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 74LS373 LE Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 11 19 16 15 12 9 6 5 2 A07 A06 A05 A04 A03 A02 A01 A00 11 19 16 15 12 9 6 5 2 A15 A14 A13 A12 A11 A10 A09 A08 11 19 16 15 12 9 6 5 2

BHE/S7 A19/S6 A18/S5 A17/S4 A16/S3

34 35 36 37 38

S7 S6 S5 S4 S3

BHE/ A19 A18 A17 A16

TEST/ HOLD HLDA/

23 31 30

TEST HOLD HLDA

NMI INTR

17 18

NMI INTR

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

9 10 11 12 13 14 15 16

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

18 17 14 13 8 7 4 3

U4 74LS245 19 1 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 9 8 7 6 5 4 3 2 G DIR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 11 12 13 14 15 16 17 18 D15 D14 D13 D12 D11 D10 D09 D08

U5 74LS245 19 1 9 8 7 6 5 4 3 2 RN1 4k7 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 9 8 7 6 5 4 3 2 G DIR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 11 12 13 14 15 16 17 18 D07 D06 D05 D04 D03 D02 D01 D00

GND

Figure-2.63: Schematic Diagram of 8284-8086-74LS245-74LS373 Based Subsystems [6]

140
2.7 (b) Composite Memory-Port Decoding Subsystem

Chapter - 2

PRINT: Page: P140 P151

Figure-

Schematic Diagrams of MicroTalk-8086 Trainer

141

2.7 (c) Memory Subsystem print: p145 -

142
2.7 (d) 8279-based Keyboard/Display Subsystem

Chapter -2

Schematic Diagrams of MicroTalk-8086 Trainer

143

2.7 (e)

Parallel IO Subsystem to Drive LEDs and Stepper Motor Interface

144
2.7 (f) 8255-based PO Subsystem-II to Drive DOT Matrix LEDs

Chapter - 2

Schematic Diagrams of MicroTalk-8086 Trainer 2.7 (g) 8253-baesd Programmable Interval Timer

145

146 2.7 (h) AD0804

Chapter - 2

Schematic Diagrams of MicroTalk-8086 Trainer

147

2.7 (i) AD556

148 2.7 (j) 8259-based IPC

Chapter - 2

Schematic Diagrams of MicroTalk-8086 Trainer

149

2.7 (k) 2x16 LCD

150 2.7 (l) 6151-based SIO

Chapter - 2

Schematic Diagrams of MicroTalk-8086 Trainer

151

2.7 (m) Power Supply

152 2.8 Problems and Solutions

1

Chapter - 2

Why is it so important for us to study External Architecture of the 8086 microprocessors? Ans: The building blocks of a microprocessor- based system are connected with the pins of the microprocessor. Therefore, it is very important that the system designers have good understanding on the characteristics of the pins (the external architecture) of the MPU. Refer to Fig-2.1, indicate the meaning of the signal AD06 associated with Pin-10. Ans: at time t1, the Pin-10 is an outgoing line and sends address signal A06 on the address bus, at time t2, the Pin-10 turns itself into a bi-directional data line D06 to exchange data. How many signals are there for the 8086? How many pins are there to activate all these signals? Ans: (i) 61 signals [Fig-2.22] (ii) 40 pins How is it possible to activate 61 different signals using only 40-pins instead of 61-pins? Ans: Because there are many signals, which dont occur at the same time like A15 A0 and D15 D0 signals. So, there is no need for allocating dedicated pins for these 32 signals. It is sufficed to have only 16-pins to handle these 32 signals using time-multiplex. What is the advantage of having two ground pins for the 8086? Ans: Two ground pins support two parallel paths for the drainage of the supply current. This parallel path arrangement reduces the noise level compare to single path arrangement. Define Bus Activity and Bus Cycle. Explain the meaning of bus activity with example. Bus Activity: A bus is said to have acquired activity when the logic values of its present bus cycle is different from the previous bus cycle. A Bus cycle refers to the time from T1-to-T4 [Fig-2.4] during which the CPU performs a read (write) operation on an external memory (port) location. Meaning of Bus Activity: Let us try to clarify the meaning with the help of the following example and the timing diagram of Fig-2.4: 01000 a. B0 23 :mov al, 23h The 1st Bus Cycle deals with reading the code byte B0 from even memory location 01000h. During this read operation, we have the following bus activity [Fig-2.63]: i. 0000 0001 0000 0000 0000 bit pattern is sent on the ABUS ii. 1 (LH) is put on BHE/ signal iii. LH-H-LL (short duration High pulse) is asserted on the ALE line. iv. LL is put on the DT-R/ line v. LL is put on the DEN/ line vi. LL-L-LH (short duration Low pulse) is put on the RD/-signal vii. LH signal is put on WR/signal viii. LH signal is put on the M-IO/ line ix. xxxx xxxx D7 D0 appears on the DBUS The 2nd Bus cycle deals with reading the code byte 23 from odd memory location 01001h. During this read operation, the following bus activities appear on the bus signals [Fig-2.63]. i. 0000 0001 0000 0000 0001 bit pattern is sent on the ABUS ii. 0 (LL) is put on BHE/ signal iii. LH-H-LL (short duration High pulse) is asserted on the ALE line. iv. LL is put on the DT-R/ line v. LL is put on the DEN/ line vi. LL-L-LH (short duration Low pulse) is put on the RD/-signal vii. LH signal is put on WR/signal viii. LH signal is put on the M-IO/ line ix. D15 D8 xxxx xxxx appears on the DBUS

3 4

b.

Problems and Solutions

7

153

Why is it so important to know the loading conditions for the pins of the 8086? Ans: Loading conditions indicate the permissible voltage and current ratings of the pins. Loading conditions allow us determining the safe fanin/fanout for the pins. Define Instruction Cycle, Machine Cycle and T-state. Define Memory Access Time. Ans: Refer to the timing diagram of Fig-2.4 The CPU asserts address on the ABUS at time T1. After a while (say, T1+ t1), the address signal becomes stable. And then (say at time T1+t2) the CPU asserts RD/signal. And then (say, at time T1+t3) the data from the addressed memory location appears on the DBUS. Now, the memory access time is: t3 t1. Write down the values that the internal registers of the 8086 assume following the power up reset. Explain the role of the 74LS373 latch in isolating the address information from the DBUS in a time multiplexed address/data bus system. Indicate the space range that has been reserved for the Interrupt Vector table of the 8086. Draw Port Organizational Diagram of 8086 showing ODD/EVN banks and port decoder. Briefly describe the functions of the Segment Registers. Indicate the various uses of the al and ax registers. Indicate the various uses of the dx-register. Write down the names of the categories into which the 40-pins of the 8086 could be classified. Draw simplified Bus-structured diagram for the 40-pins of the 8086 and then label the signal classes. Draw layout diagram for the Internal Registers of the 8086. Draw bit pattern for the Flag Bits of the Flag Register of the 8086. Briefly explain with examples the use of the CF, ZF and SF. a. Use of Carry Flag (CF) The CF is a single bit storage location within the 8086. It automatically holds the carry (either 1 or 0), which is generated after the addition of two 8-bit (16-bit) numbers. The CF can also be loaded with 0 or 1 by program instructions. The CPU can look into the CF-bit and then takes action accordingly. Examples: i. mov al, 45h add al, 0D2h ; result in CF, al jc LX ii. The CF-bit can also be affected by executing shift and rotate instructions. The execution of the following instructions

8 9

10 11 12 13 14 15 16 17 18 19 20

21 22

Draw Memory Organizational diagram for 8086 showing ODD/EVN banks and the memory decoder. Briefly describe the functions of the following signals of the 8086. i. MN-MX/ ii. RESET iii. ALE iv. M-IO/ v. BHE/

MN-MX/ : A LH signal at this pin allows the 8086 to operate in its minimum mode. In this mode, the 8086 generate the bus signals that do not support the parallel operations of 8087 math co-processor. A LL signal at this pin allows the 8086 to operate in parallel with 8087 math co-processor but the bus signals are now generated with the help of 8288 bus controller. RESET : A short duration LH pulse at this pin initiates the starting phase of the 8086. When the signal enters into inactive state, the CPU begins fetching the instruction at location: FFFF0H (FFFF:0000). ALE : This is a short duration LH pulse, which occurs at the beginning of every machine cycle. The ALE signal transfers the address signal to the output of an auxiliary latch in the multiplexed address/data bus system of 8086.

154

Chapter - 2
M-IO/: This signal carries LH signal to the decoder to select memory devices during the execution of mov instruction. A LL value for the M-IO/ signal selects the port devices during the execution of in/out instruction. BHE/: This pin carries LL signal to the decoder for selecting odd bank of memory/port devices.

23

Refer to the following diagram and explain how the addition of the pull up resistor R1 has helped raising the output voltage of the 8086 so that it can now drive a CMOS gate.
+5V I OL = 2.5m A R1=2k2 I OL = 0.51m A

+5V Rc2: 100 Rc4: 1.5k T2

I IL = -10pA

8086
I OH = - 400uA 5.00 Vcc Logic-H I IH = 10pA 5.00 3.5

4011

R1: 2k

V DD

D
3.6 2.40 V OH V IH

4011
T3 Vo

0.45 0V GM:667:8/2004

V OL GND

1.5 Logic-L 0V

V IL Vss

667

Without the insertion of the pull up resistor R1 in Fig-2.5, we have: VOH (8086) = 2.4V (minimum) and VIH (CMOS) = 3.5V (minimum). And at no load condition (no fanout), the VO (Output voltage) = 5 2x0.7 = 3.6V. Therefore, to maintain the value of VOH (8086) at least just greater than 3.6V, we require installing a pull up resistor between the 8086 and the CMOS. Let us now see how the resistor R1 in the circuit of Fig-2.76 has helped raising the output voltage of the 8086 gate above 3.6V when the output is at Logic-H. Fig-2.76 describes the position of the interface resistor R1 with the output section of the 8086 gates. Without the resistor R1 and assuming that the 8086 is fanned-out by one CMOS gate, we have: VO = VCC VBE2 VD VRC2 = 5 0.7 0.7 1.5kx10x10-12 A = 3.6V, which is just marginal to meet the requirement of VIH (8086) VIH (CMOS) With the resistor R1 installed, the output terminal will be pulled up towards +5V (VCC rails) through the resistor R1. The path RC2-BEJ2-D will be bypassed because of the voltage drop across the two-diode junction. Thus, practically the output voltage will be much higher than the 3.6V. 24 Draw Truth Table for the RD/, WR/, M-IO/, BHE/ and A0 signals showing all possible read operations. RD/ 0 0 0 0 0 0 WR/ 1 1 1 1 1 1 M-IO/ 1 1 1 0 0 1 BHE/ 1 0 0 1 0 0 A0 0 1 0 0 1 0 Function Read 8-bit data from even bank of memory Read 8-bit data from odd bank of memory Read 16-bit data from both bank of memory starting at even bank. Read 8-bit data from even bank of port Read 8-bit data from odd bank of port Read 16-bit data from both bank of port starting at even bank.

Problems and Solutions

25 Read the following memory organizational diagram and then answer to the questions that follow.

155

Questions: How many lines are there in the address bus of A (the value of x). Indicate the type number of the IC (74LSXXX) that could be used to replace the discrete components based memory decoder? iii. Indicate the logic values of M-IO/, BHE/ and A0 signals for which the SE/-signal will always assume LL-state. iv. Write the ASM code that will read a data byte from a location of MEB into ah-register of the 8086. v. What is the function of the BHE/ signal? vi. What is the function of the A0 signal? vii. Write an instruction in ASM code or Pseudo code, which when executed forces the RD/ signal to assume LL-state. viii. Write an instruction in ASM code or Pseudo code, which when executed forces the M-IO/ signal to assume LL-state. ix. Write an ASM code to read 16-bit data from both memory banks at the same time. x. How many port locations are there in the given system that the 8086 can access? xi. Draw truth table and then show that the SE/-pin really goes to LL-state when an even-numbered memory reference instruction is executed. xii. Draw truth table and then show that the SO/-pin really goes to LL-state when an even-numbered memory reference instruction is executed. 26 Write down the possible tasks that the CPU carries out during a machine cycle. Ans: During a machine cycle, the 8086 microprocessor performs only one event out-of-the following: i. ii. iii. iv. v. Data read from a memory location. Data write into a memory location. Data read from a port location. Data write into a memory location. Interrupt Type Code read from an internal interrupt controller. i. ii.

156
27

Chapter - 2
How does the system work when we wish to read two bytes data from two memory locations (00001h and 00002h) beginning with an odd numbered address? Ans: Now the CPU cannot handle the two bytes data operation in one machine cycle. It takes two machine cycles to complete the data transfer operation. The reasons are explained below: To handle 16-bit data operation with both the banks simultaneously and starting at the ODD bank, the CPU should execute the following memory referenced instructions starting at the odd boundary: mov ax, (00002h, 00001h) Now, the memory decoder circuit of Fig-2.12 could never activate the SO/ and SE/ signals at the same time. This is due to the fact that the CPU asserts an odd numbered address on the address bus first, which puts LL for BHE/ signal. SO/-pin assumes LL state and the ODD bank is selected. But the SE/pin assuming Logic-H state and disables the EVN bank. The CPU completes the word operation by having handled the ODD bank first and then the EVN bank. The CPU takes two machine cycles (double time) to complete the word-read operation.

28

Read the following 74LS138-based decoding system. Indicate the range of addresses for which the given memory chips would be selected.

Ans: Chip Select CS/ 0

M-IO/ 1

Bus Signals A19 A18 A17 0 0 1

A16 1

A15 1

Address Signals A14, ., A0 xxx xxxx xxxx xxxx (7FFF 0000)

So, the address range for which the RAM would remain selected is: 38000h 3FFFFh 29 Assume that the memory location 01500h contains a data value of 35h. Now, during the execution of the instruction: mov bl, BYTE PTR (01500h): 8A 9F 00 15, there are activities on the bus, which are partially recorded in the following table. Your task is to fill up the gaps with correct data. [Assume that the program codes are stored staring at location: 00400h]
Address Bus (A19A00) 1 2nd 3rd 4th 5th
st

Machine Cycle 0000 0000 0100 0000 0000 0000 0000 0100 0000 0001 0000 0000 0100 0000 0010 0000 0000 0100 0000 0011 0000 0001 0101 0000 0000

Bus Activity Data Bus (D15 D00) xxxx xxxx 1000 1010 1001 1111 xxxx xxxx xxxx xxxx 0000 0000 0001 0100 xxxx xxxx xxxx xxx 0011 0101

Control Bus (RD/, WR/, M-IO/, BHE/) ---------------------------------------------------------------------------

30

Look at the timing diagram of Fig-2.4 and observe that there exits a clean and idle time slot after the data bus is loaded with data. Can you locate this time slot? Similar time slot also exits in the 8085 architecture. Zilog architecture has utilized this time slot giving a fantastic job to the Z80A microprocessor. Make a good guess what could the job that was assigned to the Z80A.

Problems and Solutions

31

157

What is DMA protocol? Draw a block diagram using 8257 DMA Controller and then explain the working principles of DMA protocol. DMA stands for Direct Memory Access. We know that data transfer from a source area to a destination area takes place byte-by-byte or word-by-word. If there is a large amount of data (like loading a game of 2 Mbyte from a CD into memory) to move, a considerable amount of time is required. How can we reduce this loading time? It is possible by devising a means where the peripheral controller (the CD- Drive) will directly transfer the data into RAM. This is to say that the CD-Drive is directly accessing the RAM bypassing the CPU. In doing this job, the peripheral controller takes the help of a dedicated controller (the DMA Controller), which supervises the data read/write operations and behaves like a Smart CPU for the rime being.

Working Principles of DMA Protocol: a. The CD-drive contains smart electronics circuitry that tells U5 using DREQ (DMA Request) line that it wants direct data transfer with memory b. The DMAC (DMA Controller), U5 immediately requests the 8086 over the HOLD line to release the bus to it so that direct data transfer between CD-drive and memory can take place. c. The CPU finishes the current machine cycle (and not the current instruction) and then releases the bus. This is indicated to the DMAC over the HLDA line. As a result, the following events occur: i. Address bus of the memory chip is switched over from 1A-position to 1B-position, ii. Control Bus (CBUS) of memory is switched over from 2A-positin to 2B position. iii. Data bus of memory is witched over from 3A-positin to 3B-position. d. Upon receiving the HLDA signal from the CPU, the U5 tells the CD-drive over the DACK (DMA Acknowledge) line that the CD-drive can begin the data transfer. e. The DMAC furnishes the incremented addresses for the memory chip. It also generates the read/write control signals for the memory and IO devices. The DMAC knows how many bytes to transfer in one GO. f. At the end of data transfer, the CD-drive interacts. The bus goes back to its previous positions. g. The DMAC deactivates the HOLD line. The CPU regains the control of the bus and continues its task.

158
32 Discuss the various ways of putting a desired value into the CS- and IP-reusters. Ans: The CS- and the IP-registers are loaded in the following ways: a. At Powerup reset by the internal Reset logic of the CPU [Fig-2.43] FFFF CS 0000 IP The program execution automatically begins at location: FFFF0h b. By executing the following unconditional jump instruction: jmp DWORD ds:[bx]

Chapter - 2

The CS- and IP-registers are loaded with the values from a memory-based table, whose beginning address is in bx-register. To transfer program control at location 43210h, the steps to be carried out are: i. To create the memory-based table within the scratch pad of Fig-2.11. The table will hold the address of the target location, 4000:3210 (43210). mov ax, 0000h mov ds, ax mov bx, 0F00h mov WORD PTR ds:[bx], 3210h mov WORD PTR ds:[bx+02h], 4000h ii. iii. c. Execute the instruction: jmp DWORD PTR ds:[bx] The program execution will automatically begin at location: 43210h

IRQ Radr

By keeping the desired value in the stack and then executing the iret instruction. Assume that the CPU is interrupted at label ML2: (01002h) of the following mainline program (MLP). It is intended that the CPU should resume the MLP at label ML1: (01000h) rather at ML3 after finishing the ISR. The program codes under ISR will do it. ML1: 01000 mov al, 23h : B0 23 ML2: 01002 mov dx, 3600h : BA 00 36 ML3: 01005 out dx, al : EE --------------------------------------------------------------------------------------------------------ISR: ISRL1: nop -------------ISRL2: mov bp, sp mov WORD PTR ss:[bp+02h], 1000h ; segment of ML1 mov WORD PTR ss:[bp+04h], 0000h ; offset of ML1 ISRL3: iret Stack Diagram at Label ISRL3
FFFFF 08FFF 08FFE

Stack Diagram at Label ISRL1:

FFFFF 08FFF 08FFE

Stack Diagram at Label ML1

FFFFF 08FFF 08FFE

FRH FRL 00 00 10 05

SSM
07000 00000

FRH FRL 00 00 10 00

SSM

sp

FRH FRL 00 00 10 00

SSM

sp-06

07000 00000 728x

Sp-06

07000 728x 00000 728x

After interruption, the CPU saves FR, Radr (Return Address: 0000:1005) onto stack and the scenario appears like the left figure. At ISRL2:, the CPU is forced to executes few instructions that change the Radr from 1005h to 10000h on the stack and the scenario is depicted in the middle figure. At ISRL3:, the CPU returns from the ISR and resumed MLP at label ML1: rather than at label ML3:. Stack goes to its original position where it was before the interruption.

Problems and Solutions

c.

159

There is another way of transferring program control to a target location, which is described below. The author devised this method at the time of building the MicroTalk-8086 learning system. i. ii. iii. Assume that the target location is the beginning address (say, 01000 = 0000:1000) of a user program that has been stored in RAM starting at location 01000h. The address would be entered from the keyboard as 5-digit hex. At the end of 5-digit address entry, the monitor program carries out the following steps: 1. Converts the 5-digt hex (01000) into Segment:Offset format of: 0000:1000. 2. The following information bytes are placed in the RAM locations as indicated: EA (opcode for Jump) 00F00h 00 (OFF_Low of Target address) 00F01h 10 (OFF_High 0f target Address) 00F02h 00 (Seg_Low of Target Addres) 00F03h 00 (Seg_High of Target Address) 00F04h 3. Now the monitor program makes jump at location 00F00h by executing the following machine codes, which are equivalent to: jmp 00F00h. EA 00 0F 00 00 4. The CPU arrives at the location 00F00h where it founds the opcode (EA) of another jump instruction with the inscribed target location of: 01000h. 5. The CPU reaches at location 01000h and begins the execution of the user program.

33

It is possible to write a program for the 8086 to solve a mathematical problem like finding the Hypotenuse of a Right Triangle given the sides A and B. But instead of using the 8086 for this purpose, we prefer to employ the 8087 coprocessor in parallel with the 8086. Explain briefly the role of the 8087 for quick calculation of this mathematical problem. Ans: 8086 is designed to solve general purpose problems like moving data among memory (port) and the CPU and performing 16-bit ALU operations. The CPU is not optimized to solve mathematical problem like finding the square root of a number. This is to say that the 8086 does not have Square Root instruction. To find the hypotenuse of a right triangle, we have to write a program to solve the expression (A2 + B2), which involves extracting square root. Because the 8086 do not have square root instruction, we have to first transform the expression into a series and then adding up the terms. This process would certainly take relatively longer time and the solution method may not be acceptable in the practical field. Therefore, the alternate way is to use a dedicated hardware (the 8087 chip), which has square root (FSQRT) instruction. Now, the 8087 can invoke the FSQRT instruction for automatic activation of the internal electronic circuitry that will quickly evaluate the expression (A2 + B2) in real time and then pass the result to the 8086 for further processing.

34

Explain with the help of the program codes of Sction-2.6.D15 (Page-137), the DMA operation that the 8087 performs to exchange data with the memory. Let us begin the study of the program from label L3: of the example program codes of Fig-137. The DMA action being taken place may be described in the following way: a. The address 0101Eh (0000:101E) is on the ABUS. This is the address of the CSM location from which the 8086 read the last code byte (74h) at label L3A: b. The instruction D9 47 74 is taken by both 8086 and 8087. This instruction tells the 8087 to read 4byte (DWORD = 32-bit) data from the memory locations < 00474 , 00475, 00476, 00477 >. c. The 8086 computes the 1st address of DSM from the instruction (D9 47 74) as 00474h and assert it on the ABUS along with necessary CBUS signals (A0=0, RD/=0, WR/=1, M-I)/=1, BHE/=0) to perform a word-data read operation. . The 16-bit data from the memory locations <00474, 00475 > are available on the DBUS, which the 8087 put into its internal register. The 8086 ignores it.

160
d.

Chapter - 2
If the 16-bit data is not enough for the 8087 to carry out its intended processing, then it acquires the remaining data from memory locations under DMA protocol. The current 8087 instruction fld DWORD PTR [bx+74h] dictates that the 8087 requires 32-bit data. The DMA operation between the 8086-8087 takes place in the following ways: i. The 8087 grab the present address value (00474h) from the bus. It now wishes to take over the control of the bus for reading the next data-word from the memory locations <00476, 00477 >. ii. The 8087 send low-going pulse on the RQ/-GT0/ line [Fig-2.62] to the 8086 to mean Bus Request. iii. In response, the 8086 send another low-going pulse on the same RQ/-GT0/ line to the 8087 to mean that Bus Request is granted. iv. The 8087 adds 02h with the address signal (00474h) that it grabbed from the ABUS and assert it (00476h) on the ABUS along with word-data read control signals. v. The 16-bit data from the memory locations < 00476, 00477 > is available on the DBUS and the 8087 store it in its internal register. vi. 32-bit data read by the 8087 is complete. Now, the 8086 send another low-going pulse on the same RQ/-GT0/ line to the 8086 to mean that the CPU can have the bus back.

35

Explain with the help of the program codes of Section-2.6.D15 (Page-137), the synchronization that the 8086 and 8087 maintain among them during program execution. This is to saying that: Explain the mechanism that the 8086 and 8087 employ in order to ensure that: i. The 8086 does not execute the instruction that belongs to 8087 and vice versa. ii. That the 8086 do not attempt to read next instruction that belongs to the 8087 until the 8087 has finished the execution of its current instruction. 8086-8087 Synchronization: It refers to the establishment of a mechanism in which the 8086 keeps checking that the 8087 have finished its current instruction and only then the 8086 will fetch the next instruction from memory that belongs to it or the 8087. The synchronization is maintained in the following way: a. At label L1: of examples codes of Page-137, the CPU finds the opcode 9B, which is for the wait instruction and it belong to the 8086. Seeing the code 9B means that the next instruction that the 8086 are going to read from memory certainly belongs to 8087. Therefore, the CPU has to wait until the 8087 are ready to accept the next instruction. The MASM assembler is so clever that it automatically puts the code (9B) for WAITT instruction when it finds an 8087 instruction. b. c. The CPU enters into loop mode and keeps checking its TEST/-pin for LH logic. Because, the 8087 has not yet executed any instruction beyond L1:, the CPU finds that the TEST/pin is at LL. This means that the 8087 are not busy and the 8086 may read the next instruction from memory. At the instant of executing an instruction, the 8087 put LH at its BUSY-pin, which is directly connected with the TEST/-pin of the 8086. The 8086 reads the next instruction DB E3 from memory. At the same time, the 8087 also read these instruction bytes. The 1101 1xxx pattern of 1st byte (1101 1xxx indicates 8087 instruction) informs the 8086 that the instruction belongs to the 8087. The 8086 ignore it and internally execute a nop instruction and then go to the label L1A: to read the next instruction. The 8087 has begun the execution of the instruction DB E3. At the instant of execution, the 8087 has asserted LH-signal on the BUSY-TEST/ line to inform the 8086 that it (8087) is now busy. The CPU finds the code BB 00 04, which has not proceeded with the code 9B. So, this instruction does not belong to the 8087 and thee is not need to into wait state by polling the TEST/-pin. At L3:, the 8086 finds the opcode 9B for its wait instruction. It checks the TST/-pin and sees that it is at LL. The 8087 are ready. So, the 8086 read the instruction bytes of L3A: that belongs to 8087.

d.

e. f.

Problems and Solutions

161

The 8086 ignores the 8087 instruction, spend a time delay by executing the nop instruction and then goes to the label L3B:. During this time, the 8086 has started executing its instruction D9 47 74 of L3A; and has asserted LH on the BUSY-TEST/ line. At label L3B:, the 8086 has read the 9B (code for wait instruction) from memory and immediately (without reading the next codes bytes of L3C:, D9 47 78 that certainly belongs to 8087) enters into checking the TEST/-pin (it has already made LH by 8087) and find that it is at LH. Who asserted LH here? It was asserted by 8087 at L3A:. The 8086 enter into wait state. The 8087 finishes its instruction (D9 47 74 of L3A:) and assert LL on BUSY-TEST/ line. The 8086 is it at label L3B and understands that the 8087 is ready to accept the next instruction. The 8086 reads the instruction bytes of L3C: (D9 47 78) and makes them available for 8087. Now, the synchronization mechanism among 8086-8087 during the execution of the 8087 instructions from L4: - to L5: are explainable.

g.

h. i. j. 36

Refer to Fig-2.62 and then answer to the following questions: a. Explain the reasons for connecting together the S2/-S0/, QS1-QS0, ABUS and DBUS lines of the 8086-8087 processors. b. A user program contains instructions for both the 8086 and the 8087. The program is submitted to the 8086 for execution. The 8086 reads all the instructions from the CSM but executes only its own instructions. Explain how does the 8087 collect its instructions and then execute them. c. How does the 8086 know that a particular instruction do not belong to it and should be ignored? d. Assume that the data item of 80-bit long (0123456789ABCDEF0123h) is stored into ten memory locations starting from 00474h. Describe how the 8086 and 8087 work together to bring the data item into the ST (Stack Top) register of the 8087. e. Describe briefly how the DMA Handshaking takes place among 8086 and 8087 during data exchange with memory. f. Describe the mechanism that prevents the 8086 from reading the next instruction byte for the 8087 until the 8087 have finished executing its current instruction. g. Why is the AIOWC/ (Advance IO Write Control) signal instead of IOWC/ signal connected with the WR/-pin of the 8279 controllers? Describe the operation of the Circular Queue System of the 8087 and then answer to the following questions: Circular Queue: There are 8-registers (each 80-bit) within the 8087 in the form of a Circular Queue as is shown in the right-side diagram. In a circular queue, the registers may be viewed as having placement on the surface of a cylinder. At Powerup reset, the Stack Register-000 (SR000) is considered as StackTop [ST or ST(0)] and is always a filled up location. SR-001 that got filled up before ST(0) is designated as ST(1), SR-010 as ST(2) and so on. In 8087 systems, the stack grows towards decreasing stack registers. So, if we execute the instruction: fld DWORD PTR [bx] instruction, the data from memory will enter (known as push) into the empty Stack Register (000-1 = 111). Now, the new StackTop [ST = ST(0)] is the SR-111. SR-000 now becomes ST(1), SR-001 becomes ST(2), SR010 becomes ST(3) and so on. We can say that the cylinder turns by one stack register in the direction indicated. After 2nd push, SR-110 becomes ST(0), SR-111 becomes ST(1), SR-000 a. Which and register becomes ST(2)stack so on. is the Stack Top (ST) at Powerup reset?

37

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a.

Chapter - 2
Which stack register of the 8087 will become the stack top after reading a data item into its current ST? Assume that the current ST is the stack Register-110. Ans: Stack grows in decreasing Stack Register. So, the new ST will be SR-101. Briefly describe the working principles of the following 8087 instruction: i. fadd ST(0), ST(4) The 80-bit content of ST(4) (which is 4 location down from ST) will be added with the contents of ST(0) and the result will be left in ST(0). ii. faddp ST(1), ST(0) The content of ST(0) will be added with the content of ST(1) and the result is left in ST(1). After that a pop instruction is internally executed. Now, ST(1) becomes ST and it holds the result of the given instruction. iii. fld DWORD PTR ds:[bx] The 8087 read 32-bit data from four consecutive memory locations of DSM and pointed by bx-register. The data is saved into ST (StackTop) register iv. fsqrt The square root of the content of the TOP element will be extracted and the result will be left on the TOS register. v. fldpi The value of will be loaded onto the TOS register. vi. fstcw WORD PTR ds:[bx] The 16-bit content of the control register of the 8087 is stored into memory locatiobs of DSM pointed by bx-register. vii. fptan The instruction finds the tangent of an angle given via TOS. The angle should be in radian and in the range 0 < angle < /4. The result is left in TOS. Draw a table below and then document the machine codes of the 8087 instructions of Q37c. Sno. 1 2 3 4 5 6 7 Instruction fadd ST(0), ST(4) faddp ST(1), ST(0) fld DWORD PTR ds:[bx] fsqrt fldpi fstcw WORD PTR ds:[bx] fptan Machine Codes 9B D8 C4 9B DE C1 9B D9 04 9B D9 FA 9B D8 EB 9B D9 3F 9B D9 F2 Found By

b.

c.

MASM V5.10

38

What is the meaning of normalizing a number? Say, we have a decimal number, 17.345. Let us write it like this 1.7345 x 101 and this is called the normalized form of the number 17.345. So, normalizing means placing the decimal point to the right of most-significant nonzero digit. The normalized form of 0.00234 is: 2.34 x 10-3. The digit part (234) is known as Significand or mantissa and the exponent part is (-3) of the decimal number 0.00234. What is the meaning of representing a number in scientific notation? It means normalizing a number as is shown in the answer of Q38. Explain the concept of fixed-point number. In fixed-point representation of a number, we do not engage any mechanism to track the position of the decimal point rather we as programmers remember the position of the decimal point wrt to the right-most digit of the number. For example, in fixed-point representation, the BCD format of the number 23.75 is: 0010 0011 0111 0101. We remember the decimal point on a piece of paper by writing that the decimal point is located at a point that is two-digits away from the right-most digit.

39 40

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163

In fixed-point representation, the result of the multiplication of the numbers 19.99 and 99.99 is obtained in the following ways: a. Take off the decimal point of the first number (but record its position), we get : 1999 b. Convert the decimal number 1999 into Binary (hex) and we get : 07CF : 9999 c. Take off the decimal point of the 2nd number and we have d. Convert the decimal number 9999 into Binary (hex) and we get : 270F e. Now, multiply the above two-hex numbers and we get : 0130FE21 f. Convert the hex (hex is a compact form of binary) number 0130FE21, we get : 19988001 g. Put the decimal point at the correct place (we know from our record that the decimal Point should be located at a place that is 2+2 = 4 digits away from the Right-most digit), we get : 1998.8001 h. In practice, we make it two-decimal rounding and we get : 1998.80 41 Explain the concept of floating-point representation of number. In practice, we deal with very big numbers (positive or negative) and containing fractional parts. These numbers are known as real numbers. While dealing with these real numbers of great size, it is not practically feasible to keep records of the decimal (binary) points. Therefore, we must engage a mechanism in the number so that the position pf the point is automatically taken care off. This is to say that the number should be represented in such a way so that it contains both the integer part and the fractional part. These numbers are known as floating-point numbers. Explain with examples the meaning of: Word Integer, Short Integer and Long Integer. Word Integer The decimal range of the number is: -32768 x +32767. In computer memory, the range is represented using 16-bit data in 2s complement form.. So, the value of x is: x = - b15 x 215 + (b14 x 214 + + b0 x 20 ) Short Integer The decimal range of the number is: - 2 x 109 x 2 x 109. In computer memory, the range is represented using 32-bit data in 2s complement form.. So, the value of x is: x = - b31 x 231 + (b30 x 230 + + b0 x 20 ) Long Integer The decimal range of the number is: - 9 x 1018 x + 9 x 1018. In computer memory, the range is represented using 64-bit data in 2s complement form.. So, the value of x is: x = - b63 x 263 + (b62 x 262 + + b0 x 20 ) 43 Explain with examples the meaning of Packed Decimal.

42

Eighteen BCD digits (d17 d0) are accommodated into 72-bits using SM (Signed Magnitude) number representation format. Bit-79 is the sign bit. To represent: a. - 9999 9999 9999 9999 99, we keep: 1001 1001, ..., 1001 1001 at positions d17 d0 and LH (1) at bit-79; Bit-72 to bit-78 are not used. b. + 9999 9999 9999 9999 99, we keep - 1001 1001, .., 1001 1001 at positions d17 d0 and LL (0) at bit-79; Bit-72 to bit-78 are not used.

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44

Chapter - 2 Given below the Fetch-Execution Mechanism that the 8086 employs for finish the instruction add WORD PTR ds:[bx+1234h], 5678h. Read it carefully and then answer to the questions that follow:

i. ii. iii. iv. v. vi. vii. viii. ix. x.

What are the two 16-bit numbers that are being added? Write down the numerical value of the Opcode for this particular add instruction. How many read operations are there for the execution of the given instruction? What numerical code the MASM would produce for the given add instruction? . Which flag bit will enter into ALU over the IN3-path during the execution of adc instruction? Write down the names of the Temporary Registers that are involved in the given add operation. Assume the operating frequency of the CPU is 4MHz. One machine cycle lasts for 4 clock cycles. How much time the CPU would take to finish the given add instruction? From which part of the Opcode, the CPU does know that the current instruction is of 6-byte long? Indicate the circuit designation (which U?) of the module that computes the addresses of the Data Source and Data Destination locations. During what type of ALU operations, the 8-bit temporary registers TRA8 and TRB8 take place?

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