Signature of The Chairman BOS M.E (AE) : KCT-M.E (AE) - I To IV Semester Curriculum and Syllabus R - 2009

KUMARAGURU COLLEGE OF TECHNOLOGY, COIMBATORE-6 (An Autonomous College Affiliated to Anna University, Coimbatore) M.E.
APPLIED ELECTRONICS REGULATION 2009 SEMESTER I Code No. THEORY MAT506 ANE501 ANE502 ANE503 ET1*** ET2*** PRACTICAL ANE701 Total Course Title Applied Mathematics for Electronics Engineers Advanced Digital System Design VLSI Design Techniques Advanced Digital Signal Processing Elective I Elective II VLSI Laboratory SEMESTER II Code No. THEORY ANE504 ANE505 ANE506 ANE507 ET3*** ET4*** PRACTICAL ANE702 Total Course Title Analysis and Design of Analog Integrated Circuits Computer Architecture and Parallel Processing Embedded Systems ASIC Design Elective III Elective IV Electronic System Design Project SEMESTER III Code No. THEORY ET5*** ET6*** ET7*** ANE524 PRACTICAL ANE703 Total Course Title Elective V Elective VI Elective VII Research Methodology Project Work (Phase I) L 3 3 3 2 0 T 0 0 0 0 0 P 0 0 0 0 12 1/48 C 3 3 3 2 6 17 L 3 3 3 3 3 3 0 T 1 0 0 0 0 0 0 P 0 0 0 0 0 0 3 C 4 3 3 3 3 3 1 20 L 3 3 3 3 3 3 0 T 1 1 0 0 0 0 0 P 0 0 0 0 0 0 3 C 4 4 3 3 3 3 1 21
KCT- M.E [AE] I to IV Semester Curriculum and Syllabus R 2009
Signature of the Chairman BOS M.E [AE]
SEMESTER IV Code No. ANE703 Total Course Title Project Work (Phase II) L 0 T 0 P 24 C 12 12
GRAND CREDIT: 70 LIST OF ELECTIVES M.E. APPLIED ELECTRONICS Code No. ANE508 ANE509 ANE510 ANE511 ANE512 ANE513 COM517 COM519 ANE514 COM521 COM522 ANE515 ANE516 ANE517 ANE518 MAT507 CSE501 CSE502 CSE504 CSE505 CSE506 ANE519 ANE520 ANE521 ANE522 ANE523 Course Title Digital Image Processing Neural Networks and Applications Low Power VLSI Design DSP Integrated Circuits Digital Control Engineering Design and Analysis of Algorithms Soft Computing Internetworking Multimedia DSP Processor Architecture and Programming High Performance Communication Networks High Speed Switching Architecture Advanced Processors VLSI Signal Processing Analog VLSI Design Computer Aided Design of VLSI Circuits Stochastic Models and Simulation Data Structures and Algorithms Advanced Computer Architecture Network Engineering Object Oriented Software Engineering Web Technology Mobile Computing Cellular and Mobile Communication E-Commerce Technology Real Time and Embedded Systems Visualization Techniques L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 T 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 P 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 3 3 4 3 3 3 3 3 3 3
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MAT506 APPLIED MATHEMATICS FOR ELECTRONICS ENGINEERS 3 1 0 4 (Common to Communication Systems and Applied Electronics) UNIT I NUMERICAL SOLUTION OF EQUATIONS AND EIGEN VALUE PROBLEM 9 Method of false position Newton Raphson method Iteration method Solution of linear system by Gaussian elimination and Gauss-Jordon methods- Iterative methods: Gauss Jacobi and Gauss-Seidel methods Eigen values of a matrix by Power method. UNIT II WAVE EQUATION 9 Solution of initial and boundary value problems Characteristics Significance of characteristic curves Laplace transform solutions for displacement in a long string. UNIT III SPECIAL FUNCTIONS 9 Bessels equation Bessel Functions Legendres equation Legendre polynomials Rodrigues formula Recurrence relations Generating functions and orthogonal property of Bessel functions and Legendre Polynomials. UNIT IV RANDOM VARIABLES 9 One-dimensional Random Variables Moments and MGF Binomial, Poisson, Geometric, Exponential and Normal distributions Two-dimensional Random Variables Marginal and Conditional distribution Covariance and Correlation coefficient. UNIT V QUEUEING THEORY 9 Single and Multiple server - Markovian queueing models Steady state system size probabilities Littles formula M/G/1 queueing system P-K formula (Derivations excluded for all models). L: 45 T: 15 Total : 60 TEXT BOOKS: 1. Jain M.K., Iyengar S.R.K & Jain R.K., Numerical Methods for Scientific and Engineering Computation, New Age International Publishers (P) Ltd, 2007. 2. Sankara Rao K., Introduction to Partial Differential Equation, Prentice Hall of India, 2007. 3. Grewal B.S., Higher Engineering Mathematics, Khanna Publications, 40th Edition 2007. 4. Veerarajan. T., Probability and Random Process, Tata McGraw Hill,2008
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REFERENCES: 1. Kapur J.N., Saxena H.C., Mathematical Statistics, S. Chand & Company Limited, New Delhi 2007. 2. Taha H.A., Operations Research - An Introduction, Prentice Hall of India, 2008. 3. Gross. D & Harris C.M., Fundamentals of Queuing Theory, John Wiley & Sons, 2008. 4. Jain R.K., Iyengar S.R.K., Advanced Engineering Mathematics, Narosa Publishers, 2007. 5. Kandasamy P., Thilagavathi K. and Gunavathi K., Probability, Statistics and Queuing Theory, S.Chand and Company Ltd, 2007.
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ANE501 ADVANCED DIGITAL SYSTEM DESIGN 3 1 0 4 UNIT I 9 SEQUENTIAL CIRCUIT DESIGN Analysis of Clocked Synchronous Sequential Networks (CSSN) Modeling of CSSN State Stable Assignment and Reduction Design of CSSN Design of Iterative Circuits ASM Chart ASM Realization. UNIT II 9 ASYNCHRONOUS SEQUENTIAL CIRCUIT DESIGN Analysis of Asynchronous Sequential Circuit (ASC) Flow Table Reduction Races in ASC State Assignment Problem and the Transition Table Design of ASC Static and Dynamic Hazards Essential Hazards Data Synchronizers Designing Vending Machine Controller Mixed Operating Mode Asynchronous Circuits. UNIT III 9 IMPLEMENTING LOGIC FUNCTIONS USING MSI AND PROGRAMMABLE DEVICES Implementing Logic Functions using MSI Multiplexers Shannons Expansion Theorem, Designing with Multiplexers, Additional Techniques for Designing with Multiplexers, Implementing Logic Functions using MSI Decoders, Implementing Logic Functions using Exclusive OR and Exclusive NOR Elements, Implementing Logic Functions using Programmable Devices - Programmable Read Only Memory(PROM), Programmable Array Logic(PAL), Programmable Logic Array(PLA), Multi Level PLDs. UNIT IV 9 FAULT DIAGNOSIS AND TESTABILITY ALGORITHMS Fault Table Method Path Sensitization Method Boolean Difference Method Kohavi Algorithm Tolerance Techniques The Compact Algorithm Practical PLAs Fault in PLA Test Generation Masking Cycle DFT Schemes Built-in Self Test. UNIT V 9 SYSTEM DESIGN USING VHDL VHDL Description of Combinational Circuits Arrays VHDL Operators Compilation and Simulation of VHDL Code Modeling using VHDL Flip Flops Registers Counters Sequential Machine Combinational Logic Circuits - VHDL Code for Serial Adder, Binary Multiplier Binary Divider complete Sequential Systems Design of a Simple Microprocessor. - Introduction to test benches. L: 45 T: 15 Total : 60 TEXT BOOK: 1. Donald G. Givone, Digital principles and Design, Tata McGraw Hill 2002 2. Nripendra N Biswas, Logic Design Theory, Prentice Hall of India, 2001. 3. Richard S.Sandige, Modern Digital Design, McGraw Hill International Editions, 1990. 4. Volnei A. Pedroni, Circuit Design with VHDL, MIT Press, 2004.
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REFERENCES: 1. Stephen Brown and Zvonk Vranesic, Fundamentals of Digital Logic with VHDL Design, Tata McGraw Hill, 2002. 2. Peter J Ashendem, The Designers Guide to VHDL ,Harcourt India Pvt Ltd, 2002. 3. Mark Zwolinski, Digital System Design with VHDL ,Pearson Education, 2004.
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ANE502
VLSI DESIGN TECHNIQUES
3 0 0 3
UNIT I 9 MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY NMOS and PMOS transistors, Threshold voltage- Body effect- Design Equations Second order effects. MOS models and small signal AC characteristics. Basic CMOS technology. UNIT II 9 INVERTERS AND LOGIC GATES NMOS and CMOS Inverters, Stick diagram, Inverter ratio, DC and transient characteristics , switching times, Super buffers, CMOS logic structures , Transmission gates, Static CMOS design, dynamic CMOS design. UNIT III 9 CIRCUIT CHARACTERISATION AND PERFORMANCE ESTIMATION Resistance estimation, Capacitance estimation, Inductance, Inverter switching characteristics fall time, rise time, propagation delay. CMOS - Gate transistor sizing, power dissipation. UNIT IV 9 VLSI SYSTEM COMPONENTS CIRCUITS AND SYSTEM LEVEL PHYSICAL DESIGN Multiplexers, Decoders, comparators, priority encoders, Shift registers Arithmetic circuits Ripple carry adders, Carry look ahead adders, High-speed adders, Multipliers. Physical design Delay modelling, cross talk, floor planning, power distribution. Clock distribution. UNIT V 9 TESTING AND DESIGN FOR TESTABILITY Need for testing-Fault models- Fault Orient test pattern generation Fault simulation Testability improvement Structural design for testability Boundary scan test. Total: 45 TEXT BOOK: 1. Neil H.E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, Pearson Education ASIA, 2nd edition, 2000. REFERENCES: 1. Pucknell, Basic VLSI Design, Prentice Hall of India Publication, 1995. 2. John P.Uyemura ,Introduction to VLSI Circuits and Systems, John Wiley & Sons, Inc., 2002. 3. Samir Palnitkar, Verilog HDL, Pearson Education, 2nd Edition, 2004. 4. Mark Zwolinski Digital system Design with VHDL , Second Edition, Pearson Education Pvt .Ltd, New Delhi-2004.
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ANE503 ADVANCED DIGITAL SIGNAL PROCESSING 3 0 0 3 [Review of discrete-time signals and systems- DFT and FFT, Z-Transform, Digital Filters is recommended] UNIT I 9 DISCRETE RANDOM SIGNAL PROCESSING Discrete Random Processes- Ensemble averages, stationary processes, Autocorrelation and Auto covariance matrices- Parameter estimation: Bias and consistency-Parseval' s Theorem, Wiener-Khintchine Relation- Spectral Factorization, Filtering random processes, Low Pass Filtering of White Noise. UNIT II 9 SPECTRUM ESTIMATION Estimation of spectra from finite duration signals, Non-Parametric Methods-Correlation Method, Periodogram Estimator, Performance Analysis of Estimators -Unbiased, Consistent Estimators- Modified Periodogram, Bartlett and Welch methods, Blackman Tukey method. Parametric Methods - AR, MA, ARMA model based spectral estimation. Parameter Estimation -Yule-Walker equations. UNIT III 9 LINEAR ESTIMATION AND PREDICTION Linear prediction- Forward and backward predictions, Solutions of the Normal equationsLevinson algorithm, Levinson-Durbin algorithm. Least mean squared error criterion Wiener filter for filtering and prediction, FIR Wiener filter and Wiener IIR filters, Discrete Kalman filter. UNIT IV 9 ADAPTIVE FILTERS FIR adaptive filters -adaptive filter based on steepest descent method-Widrow-Hoff LMS adaptive algorithm, Normalized LMS. Adaptive channel equalization-Adaptive echo cancellation-Adaptive noise cancellation- Adaptive recursive filters (IIR). RLS adaptive filters-Exponentially weighted RLS-sliding window RLS. UNIT V 9 MULTIRATE DIGITAL SIGNAL PROCESSING Mathematical description of change of sampling rate - Interpolation and Decimation , Decimation by an integer factor - Interpolation by an integer factor, Sampling rate conversion by a rational factor, Filter implementation for sampling rate conversion- direct form FIR structures, Polyphase filter structures, time-variant structures. Multistage implementation of multirate system. Application to sub band coding - Wavelet transform and filter bank implementation of wavelet expansion of signals. L :45 Total: 45 TEXT BOOK: 1. Monson H.Hayes, Statistical Digital Signal Processing and Modeling, John Wiley and Sons, Inc., Singapore, 2002.
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REFERENCES: 1. John G. Proakis, Dimitris G.Manolakis, Digital Signal Processing Pearson Education, 2002. 2. John G. Proakis et.al.,Algorithms for Statistical Signal Processing, Pearson Education, 2002. 3. Dimitris G.Manolakis et.al.,Statistical and adaptive signal Processing, McGraw Hill, New York, 2000. 4. Rafael C. Gonzalez, Richard E.Woods, Digital Image Processing, Pearson Education, Inc., Second Edition, 2004.( For Wavelet Transform Topic)
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ANE701
VLSI LABORATORY
0 0 3 1
Experiments based on front-end and back-end tools of the following circuits: Using Xilinx ISE front-end software (using VHDL only) Combinational logic: 4-bit parallel adder 4-bit serial adder Parallel multipliers Multiply Accumulate unit Sequential logic: Multi-bit pre-settable, up/down counters FIFO buffer Sequence detectors Real-time Clock Using Microwind /Tanner back-end software: 4-bit parallel adder 4-bit serial adder 4-bit pre-settable, up/down counters 16 byte FIFO buffer 3-bit Sequence detectors
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ANE504 ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS 3104 UNIT I 9 MODELS FOR INTEGRATED CIRCUIT ACTIVE DEVICES Depletion region of a PN junction large signal behavior of bipolar transistors- small signal model of bipolar transistor- large signal behavior of MOSFET- small signal model of the MOS transistors- short channel effects in MOS transistors weak inversion in MOS transistors- substrate current flow in MOS transistor. UNIT II 9 CIRCUIT CONFIGURATION FOR LINEAR IC Current mirrors using BJT, Analysis of difference amplifiers with active load using BJT and FET, supply and temperature independent biasing techniques, voltage references. Output stages: Emitter follower, Push pulls output stages. UNIT III 9 OPERATIONAL AMPLIFIERS Operational amplifiers with single ended output, Analysis of operational amplifiers circuit, Bi-polar amplifier, Quantitative description of circuit operation, DC analysis of 741 operating amplifier, Small signal analysis of 741 operational amplifiers, Design consideration of bi-polar, monolithic operating amplifier. Designs of low drift Operational amplifier and low input current operational amplifier. Analysis of frequency response of 741 operating amplifier, high frequency equivalent circuit of 741 op-amp, calculation of -3dB frequency of 741 op-amp, non dominant pole of 741. UNIT IV 9 ANALOG DESIGN WITH MOS TECHNOLOGY MOS Current Mirrors Simple, Cascode, Wilson and Widlar current source Source follower output stage, CMOS Class AB output stages Two stage MOS Operational Amplifiers, with Cascode, MOS Telescopic-Cascode Operational Amplifier MOS Folded Cascode and MOS Active Cascode Operational Amplifiers UNIT V 9 ANALOG MULTIPLIER AND PLL Analysis of four quadrant and variable trans conductance multiplier, voltage controlled oscillator, closed loop analysis of PLL, Monolithic PLL design in integrated circuits. Noise In Integrated Circuits -Sources of noise- Noise models of Integrated-circuit Components Circuit Noise Calculations Equivalent Input Noise Generators Noise Bandwidth Noise Figure and Noise Temperature, Op-amp noise. Total: 45 TEXT BOOK: 1. Gray, Meyer, Lewis, Hurst, Analysis and design of Analog ICs, Fourth Edition, Willey International, 2002.
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REFERENCES: 1. Behzad Razavi, Principles of data conversion system design, S.Chand and company ltd, 2000 2. Nandita Dasgupata, Amitava Dasgupta,Semiconductor Devices, Modelling and Technology, Prentice Hall of India Pvt. Ltd, 2004. 3. Grebene, Bipolar and MOS Analog Integrated circuit design, John Wiley & sons, Inc., 2003. 4. Phillip E.Allen Douglas R. Holberg, CMOS Analog Circuit Design, Second Edition- Oxford University Press-2003
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ANE505 COMPUTER ARCHITECTURE AND PARALLEL PROCESSING 3 0 0 3 UNIT I 9 PRINCIPLES OF PARALLEL PROCESSING Multiprocessors and Multicomputers Multivector and SIMD Computers- PRAM and VLSI Models- Conditions of Parallelism- Program Partitioning and scheduling-program flow mechanisms- parallel processing applications- speed up performance law. UNIT II 9 PROCESSOR AND MEMORY ORGANIZATION Advanced processor technology Superscalar and vector processors- Memory hierarchy technology- Virtual memory technology- Cache memory organization- Shared memory organization. UNIT III 9 PIPELINE AND PARALLEL ARCHITECTURE Linear pipeline processors- Non linear pipeline processors- Instruction pipeline designArithmetic design- Superscalar and super pipeline design- Multiprocessor system interconnects- Message passing mechanisms. UNIT IV 9 VECTOR, MULTITHREAD AND DATAFLOW ARCHITECTURE Vector processing principle- Multivector Multiprocessors- Compound Vector processingPrinciples of multithreading- scalable and multithread architectures Dataflow and hybrid architectures. UNIT V 9 SOFTWARE AND PARALLEL PROCESSING Parallel programming models- parallel languages and compilers- parallel programming environments- synchronization and multiprocessing modes- message passing program development- multiprocessor UNIX design goals- MACH/OS kernel architecture- OSF/1 architecture and applications. Total: 45 TEXT BOOK: 1. Kai Hwang, Advanced Computer Architecture, TMH 2001. REFERENCES: 1. William Stallings, Computer Organization and Architecture, McMillan Publishing Company, 1990. 2. M.J. Quinn, Designing efficient Algorithms for parallel computer, McGraw Hill International, 1994.
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ANE506
EMBEDDED SYSTEMS
3003
UNIT I 9 EMBEDDED ARCHITECTURE Embedded Computers, Characteristics of Embedded Computing Applications, Embedded system design process- Requirements, Specification, Architectural Design, Designing Hardware and Software Components, System Integration, Unified modeling language (UML), Formalism for System Design- Structural Description, Behavioral Description, Design Example: Model Train Controller. UNIT II 9 EMBEDDED PROCESSOR AND COMPUTING PLATFORM ARM processor- processor and memory organization, Data operations, Flow of Control, SHARC processor- Memory organization, Data operations, Flow of Control, parallelism with instructions, CPU Bus configuration, ARM Bus, SHARC Bus-Design Example : Alarm Clock. UNIT III 9 NETWORKS Distributed Embedded Architecture- Hardware and Software Architectures, Networks for embedded systems- I2C, CAN Bus, SHARC link ports, Ethernet, Myrinet, Internet, Network-Based design- Communication Analysis, system performance Analysis, Hardware platform design, Allocation and scheduling, Design Examples: Elevator Controller, Ink jet printer- Hardware Design and Software Design, Personal Digital Assistants, Set-top Boxes. UNIT IV 9 REAL-TIME CHARACTERISTICS Clock driven Approach, weighted round robin Approach, Priority driven Approach, Dynamic Versus Static systems, effective release times and deadlines, Optimality of the Earliest deadline first (EDF) algorithm, challenges in validating timing constraints in priority driven systems, Off-line Versus On-line scheduling. UNIT V 9 REAL TIME OPERATING SYSTEM Operating system service-I/O sub system- Network operating systems-Interrupt routines in RTOS environment- RTOS task scheduling models-interrupts- Performance metric in scheduling models-IEEE standard POSIX functions for standardization of RTOS and inter task communication functions- List of basic function and pre emptive schedulingfifteen point strategy for synchronization between processors, ISRs, OS functions and tasks Organization OF Vx Works- RTOS programming & Debugging tools- Examples for RTOS Total: 45
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TEXT BOOK: 1. Wayne Wolf, Computers as Components: Principles of Embedded Computing System Design, Morgan Kaufman Publishers, 2001. 2. Rajkamal, Embedded System Architecture Programming and Design Tata McGraw- Hill, First reprint, 2003 REFERENCES: 1. Jane.W.S. Liu ,Real-Time systems, Pearson Education Asia, 2000. 2. C. M. Krishna and K. G. Shin, Real-Time Systems, McGraw-Hill, 1997. 3. Frank Vahid and Tony Givargi Embedded System Design: A Unified Hardware/Software Introduction, s, John Wiley & Sons, 2000.
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ANE507
ASIC DESIGN
3 0 0 3
UNIT I 9 INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN Types of ASICs - Design flow - Combinational Logic Cell Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor Parasitic Capacitance- Logical effort Library cell design - Library architecture. UNIT II 9 PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC I/O CELLS Anti fuse -Static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT - Xilinx LCA Altera FLEX - Altera MAX - DC & AC inputs and outputs - Clock & Power inputs - Xilinx I/O blocks. UNIT III 9 PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY Actel ACT - Xilinx LCA - Xilinx EPLD - Altera MAX 5000 Altera FLEX Design systems - Schematic entry - Low level design language - EDIF- CFI design representation. UNIT IV 9 LOGIC SYNTHESIS, SIMULATION Logic synthesis -Logic synthesis - Examples for simple combinational logic and sequential logic circuits using VHDL UNIT V 9 SIMULATION AND FAULT ANALYSIS Types of simulation Types of faults - Fault models D-calculus- Fault simulation LFSR - Signature analysis Built in self test - Automatic test pattern generation algorithms. Total: 45 TEXT BOOK: 1. M.J.S .Smith, "Application Specific Integrated Circuits, Addison Wesley Longman Inc., 1997. REFERENCES 1. Farzad Nekoogar and Faranak Nekoogar, From ASICs to SOCs: A Practical Approach, Prentice Hall PTR, 2003. 2. Wayne Wolf, FPGA-Based System Design, Prentice Hall PTR, 2004. 3. R. Rajsuman and Santa Clara, System-on-a-Chip Design and Test, CA: Artech House Publishers, 2000. 4. F. Nekoogar, Timing Verification of Application-Specific Integrated Circuits (ASICs), Prentice Hall PTR, 1999.
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ANE702
ELECTRONIC SYSTEM DESIGN PROJECT RULES AND REGULATIONS
0 0
There shall be three reviews during the course of the semester. The students are required to submit a report (not exceeding 25 pages) in the prescribed format at the end of the semester. The work shall be carried out in the department only. There shall be a supervisor for each student, and also an internal committee comprising of the following members to monitor the progress of the mini project : HOD Course Coordinator Project Coordinator Class Advisor Project Guide There shall be 50 marks for internal evaluation and 50 marks for external evaluation (Total: 100 marks). The internal marks distribution for the mini project is as below: Reviews : 30 (minimum of three with 10 marks each) Attendance : 5 Report : 15 -------------------------Total : 50 --------------------------
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ANE524
RESEARCH METHODOLOGY
2002
UNIT I RESEARCH CONCEPTS 6 Concepts, meaning, objectives, motivation, types of research, approaches, research (Descriptive research, Conceptual, Theoretical, Applied & Experimental). Formulation of Research Task Literature Review, Importance & Methods, Sources, quantification of Cause Effect Relations, Discussions, Field Study, Critical Analysis of Generated Facts, Hypothetical proposals for future development and testing, selection of Research task. UNIT II MATHEMATICAL MODELING AND SIMULATION 6 Concepts of modeling, Classification of Mathematical Models, Modeling with Ordinary differential Equations, Difference Equations, Partial Differential equations, Graphs, Simulation, Process of formulation of Model based on Simulation. UNIT III EXPERIMENTAL MODELING 6 Definition of Experimental Design, Examples, Single factor Experiments, Guidelines for designing experiments. Process Optimization and Designed experiments, Methods for study of response surface, determining optimum combination of factors, Taguchi approach to parameter design. UNIT IV ANALYSIS OF RESULTS 6 Parametric and Non-parametric, descriptive and Inferential data, types of data, collection of data (normal distribution, calculation of correlation coefficient), processing, analysis, error analysis, different methods, analysis of variance, significance of variance, analysis of covariance, multiple regression, testing linearity and non-linearity of model. UNITV REPORT WRITING 6 Types of reports, layout of research report, interpretation of results, style manual, layout and format, style of writing, typing, references, tables, figures, conclusion, appendices. Total : 30 REFERENCES 1. R. Panneerselvam, Reseach Methodology, PHI 2004. 2. Douglas Montgomary, Design of Experiments, Statistical Consulting Services, 1990. 3. Douglas H. W. Allan, Statistical Quality Control: An Introduction for Management, Reinhold Pub Corp, 1959. 4. Cochran and Cox, Experimental Design, John Willy & Sons, 2nd Edition , May 1992 5. S. S. Rao, Optimization Theory and Application, Wiley Eastern Ltd., New Delhi, 1996. 6. C. R. Kothari, Research Methodology, New Age Publishers, 2005.
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ANE508
DIGITAL IMAGE PROCESSING
3 0 0 3
UNIT I 9 DIGITAL IMAGE FUNDAMENTALS Elements of digital image processing systems, Elements of visual perception, Image sampling, Quantization, Mathematical representation of quantization, psycho visual model, brightness, contrast, hue, saturation, mach band effect, Color image fundamentals -RGB,HSI models, Psychovisual model. UNIT II 9 IMAGE TRANSFORMS 1D DFT, 2D transforms DFT, DCT, Walsh-Hadamard, Slant, KLT, Wavelet Transform- Properties of transforms. UNIT III 9 IMAGE ENHANCEMENT AND RESTORATION Histogram modification and specification techniques, Noise distributions, Spatial averaging, Directional Smoothing, Median, Geometric mean, Harmonic mean, Contraharmonic and Yp mean filters, Homomorphic filtering, Color image enhancement. Image Restoration degradation model, Unconstrained and Constrained restoration, Inverse filtering removal of blur caused by uniform linear motion, Wiener filtering, Geometric transformations spatial transformations, Gray-Level interpolation. UNIT IV 9 IMAGE SEGMENTATION AND RECOGNITION Edge detection. Image segmentation by region growing, region splitting and merging, edge linking.. Image Recognition Patterns and pattern classes, Matching by minimum distance classifier, Matching by correlation, Back Propagation Neural Network, Neural Network applications in Image Processing. UNIT V 9 APPLICATIONS IN IMAGE PROCESSING Need for Data compression- Huffman, Run length encoding, Arithmetic coding, Vector Quantization, Transform Coding - DCT Wavelet, JPEG, MPEG standards-Noise, Types of Noise in image, transmission effects, quantization effects, noise model, Denoising Techniques. Total: 45 TEXT BOOK: 1. Rafael C. Gonzalez, Richard E.Woods, Digital Image Processing, Pearson Education, Inc., Second Edition, 2004. REFERENCES: 1. David Salomon ,Data Compression The Complete Reference, Springer Verlag New York Inc., 2nd Edition, 2001 2. Rafael C. Gonzalez, Richard E.Woods, Steven Eddins, Digital Image Processing using MATLAB, Pearson Education, Inc., 2004. 3. William K.Pratt, Digital Image Processing, John Wiley, New York, 2002. 4. Milman Sonka, Vaclav Hlavac, Roger Boyle, Image Processing, Analysis, and Machine Vision, Brooks/Cole, Vikas Publishing House, II ed., 1999.
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ANE509
NEURAL NETWORKS AND APPLICATIONS
3 0 03
UNIT I 9 BASIC LEARNING ALGORITHMS Biological Neuron Artificial Neural Model - Types of activation functions Architecture: Feed forward and Feedback Learning Process: Error Correction Learning Memory Based Learning Hebbian Learning Competitive Learning - Boltzman Learning Supervised and Unsupervised Learning Pattern Space Weight Space Learning Tasks: Pattern Association Pattern Recognition Function Approximation Control Filtering - Beamforming Memory Single Layer Perceptron Perceptron Learning Algorithm Perceptron Convergence Theorem Least Mean Square Learning Algorithm Multilayer Perceptron Back Propagation Algorithm XOR problem Limitations of Back Propagation Algorithm. UNIT II 9 RADIAL-BASIS FUNCTION NETWORKS AND SUPPORT VECTOR MACHINES: RADIAL BASIS FUNCTION NETWORKS: Covers Theorem on the Separability of Patterns - Exact Interpolator Generalized Radial Basis Function Networks - Learning in Radial Basis Function Networks - Applications: XOR Problem Image Classification. Support Vector Machines: Optimal Hyper-plane for Linearly Separable Patterns and Non- Separable Patterns Support Vector Machine for Pattern Recognition XOR Problem - -insensitive Loss Function Support Vector Machines for Nonlinear Regression UNIT III 9 COMMITTEE MACHINES: Ensemble Averaging - Boosting Associative Gaussian Mixture Model Hierarchical Mixture of Experts Model (HME) Model Selection using a Standard Decision Tree A Priori and Postpriori Probabilities Maximum Likelihood Estimation NEURODYNAMICS SYSTEMS: Dynamical Systems Attractors and Stability Non-linear Dynamical SystemsLyapunov Stability Neuro Dynamical Systems The Cohen- Grossberg Theorem. UNIT IV 9 ATTRACTOR NEURAL NETWORKS: Associative Learning Attractor Neural Network Associative Memory Linear Associative Memory Hopfield Network Content Addressable Memory Strange Attractors and Chaos - Error Performance of Hopfield Networks Simulated Annealing Bidirectional Associative Memory BAM Stability Analysis Error Correction in BAMs -Continuous BAMs Adaptive BAMs Applications ADAPTIVE RESONANCE THEORY: Noise-Saturation Dilemma - Solving Noise-Saturation Dilemma Building Blocks of Adaptive Resonance Substrate of Resonance Structural Details of Resonance Model Adaptive Resonance Theory Applications
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UNIT V 9 SELF ORGANISING MAPS: Self-organizing Map Maximal Eigenvector Filtering Sangers Rule Generalized Learning Law Competitive Learning - Vector Quantization Mexican Hat Networks Self-organizing Feature Maps Applications PULSED NEURON MODELS: Spiking Neuron Model Integrate-and-Fire Neurons Conductance Based Models Computing with Spiking Neurons. Total: 45 TEXT BOOK: 1. Satish Kumar, Neural Networks: A Classroom Approach, Tata McGraw- Hill Publishing Company Limited, New Delhi, 2004. 2. Simon Haykin, Neural Networks: A Comprehensive Foundation, 2ed, Addison Wesley Longman (Singapore) Private Limited, Delhi, 2005. REFERENCES: 1. Martin T.Hagan, Howard B. Demuth, and Mark Beale, Neural Network Design, Thomson Learning, New Delhi, 2003. 2. James A. Freeman and David M. Skapura, Neural Networks Algorithms, Applications, and Programming Techniques, Pearson Education (Singapore) Private Limited, Delhi, 2003.
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ANE510
LOW POWER VLSI DESIGN
0 0 3
UNIT I 9 POWER DISSIPATION IN CMOS Hierarchy of limits of power Sources of power consumption Physics of power dissipation in CMOS FET devices- Basic principle of low power design. UNIT II POWER ESTIMATION 9 Power estimation techniques Logic level power estimation Simulation power analysis Probabilistic power analysis. UNIT III POWER OPTIMIZATION 9 Logical level power optimization Circuit level low power design Circuit techniques for reducing power consumption in adders and multipliers. UNIT IV 9 DESIGN OF LOW POWER CMOS CIRCUITS Computer Arithmetic techniques for low power systems Reducing power consumption in memories Low power clock, Interconnect and layout design Advanced techniques Special techniques. UNIT V 9 SYNTHESIS AND SOFTWARE DESIGN FOR LOW POWER Synthesis for low power Software of low power- Software for Power optimization Behavioral level transforms- Software design for low power co design for low power. TEXT BOOK: 1. K.Roy and S.C. Prasad , LOW POWER CMOS VLSI Wiley,2000 REFERENCES: 1. Dimitrios Soudris, Chirstian Pignet, Costas Goutis, DESIGNING CMOS CIRCUITS FOR LOW POWER, Kluwer,2002 2. J.B. Kuo and J.H Lou, Low voltage CMOS VLSI Circuits, Wiley 1999. 3. A.P.Chandrakasan and R.W. Broadersen, Low power digital CMOS design, Kluwer, 1995. 4. Gary Yeap, Practical low power digital VLSI design, Kluwer, 1998. 5. Abdellatif Bellaouar, Mohamed.I. Elmasry, Low power digital VLSI Design, Kluwer, 1995. 6. James B. Kuo, Shin chia Lin, Low voltage SOI CMOS VLSI Devices and Circuits, John Wiley and sons, inc 2001
Total: 45 circuit design,
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ANE511
DSP INTEGRATED CIRCUITS
3 0 0 3
UNIT I 9 NUMBER SYSTEMS, ARITHMETIC UNITS AND INTEGARTED CIRCUIT DESIGN Conventional number system, Redundant Number system, Residue Number System .Bitparallel and Bit-Serial arithmetic, Basic shift accumulator, Reducing the memory size, Complex multipliers, Improved shift-Accumulator. UNIT II 9 DIGITAL SIGNAL PROCESSING Digital signal processing, Sampling of analog signals, Selection of sample frequency, Signal-processing systems, Frequency response, Transfer functions, Signal flow graphs, Filter structures, Adaptive DSP algorithms, FFT-The Fast Fourier Transform Algorithm, Image coding, Discrete cosine transforms. UNIT III 9 DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS FIR filters, FIR filter structures, FIR chips, IIR filters, Specifications of IIR filters, Multirate systems, Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate filters. Finite word length effects -Parasitic oscillations, Scaling of signal levels, Round-off noise, Measuring round-off noise, Coefficient sensitivity, Sensitivity and noise. UNIT IV 9 DSP INTEGARTED CIRCUITS AND VLSI CIRCUIT TECHNOLOGIES Standard digital signal processors, Application specific ICs for DSP, DSP systems, DSP system design, Integrated circuit design. MOS transistors, MOS logic, VLSI process technologies, Trends in CMOS technologies. UNIT V 9 DSP ARCHITECTURES AND SYNTHESIS OF DSP ARCHITECTURES DSP system architectures, Standard DSP architecture, Ideal DSP architectures, Multiprocessors and multi computers, Systolic and Wave front arrays, Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based on complex PEs, Shared memory architecture with Bit serial PEs, Layout of VLSI circuits, FFT processor, DCT processor and Interpolator as case studies. Total: 45 TEXT BOOK: 1. Lars Wanhammer, DSP INTEGRATED CIRCUITS, Academic press, New York 1999. REFERENCES: 1. A.V.Oppenheim et.al, Discrete-time Signal Processing Pearson education, 2000. 2. Emmanuel C. Ifeachor, Barrie W. Jervis, Digital signal processing A practical approach, 2nd edition, Prentice Hall, 2001. 3. Keshab K.Parhi, VLSI digital Signal Processing Systems design and Implementation John Wiley & Sons, 1999.
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ANE512
DIGITAL CONTROL ENGINEERING
3003
UNIT I 9 INTRODUCTION TO DISCRETE TIME SYSTEMS Introduction discrete systems, Transform methods, properties of Z transform, Solution of difference equation, Inverse Z transform, Simulation Diagram and flow Graphs, Sampled Data control systems, Ideal Sampler, Evaluation of E*(S),Results from the Fourier Transform, Properties of E*(S),Data Reconstruction, Digital to Analog Conversion , Analog to Digital Conversion. UNIT II 9 STATE SPACE ANALYSIS State space representation of discrete time system, solving discrete time space equation, Pulse transfer function matrix, Continuous time state space equation, Discretization of continuous time state space equation, controllability, observability, useful transformation in state space analysis and design. UNIT III 9 DESIGN IF DISCRETE TIME CONTROL SYSTEM VIA TRANSFORM METHODS Introduction, Obtaining discrete time equivalent of continuous time filter, Discretizing a simple continuous time filter, Backward difference method, Bilinear transformation method, Bilinear transformation method with frequency and prewarping, Impulse invariance method, Step invariance method, matched pole Zero mapping method, Design principle based on a discrete time equivalent of an analog controller. UNIT IV 9 TIME RESPONSE AND STABILITY ANALYSIS OF DISCRETE TIME SYSTEM Transient analysis and steady state response analysis, transient response specification for second order continuous time system, relationship between Z plane pole and zero location and transient response, steady state error analysis is designed based on root locus method, design based on the frequency response method , Bode Diagrams., StabilityBilinear transformation , Routht Hurwitz criterian, Juriss stability test. UNIT V 9 DIGITAL CONTROLLER DESIGN Control system specification, Compensation, Phase lag compensation, Phase lead compensation, Design procedure using Bode plot, Integration and Differentiation, Digital DIP controllers. Total : 45 TEXT BOOK: 1. Katsuhiko Ogata, Discrete Time Control System, Prentice Hall.inc, 1987. REFERENCES: 1. Charles .L Phillips and H.Troy Nagle,Digital control system analysis and design Third Edition ,Prentice Hall International Edition. 2. M.Gopal Digital control and state variable methods,Tata McGraw publication company limited.
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ANE513
DESIGN AND ANALYSIS OF ALGORITHMS
3003
UNIT I 9 INTRODUCTION Polynomial and Exponential algorithms, big "oh" and small "oh" notation, exact algorithms and heuristics, direct / indirect / deterministic algorithms, static and dynamic complexity, stepwise refinement. UNIT II 9 DESIGN TECHNIQUES Subgoals method, working backwards, work tracking, branch and bound algorithms for traveling salesman problem and knapsack problem, hill climbing techniques, divide and conquer method, dynamic programming, greedy methods. UNIT III 9 SEARCHING AND SORTING Sequential search, binary search, block search, Fibonacci search, bubble sort, bucket sorting, quick sort, heap sort, average case and worst case behavior, FFT. UNIT IV 9 GRAPH ALGORITHMS Minimum spanning, tree, shortest path algorithms, R-connected graphs, Even' and s Kleitman' algorithms, ax-flow min cut theorem, Steiglitz' link deficit algorithm. s s UNIT V 9 SPECIAL ALGORITHMS NP Completeness Approximation Algorithms, NP Hard Problems, Strasseu' Matrix s Multiplication Algorithms, Magic Squares, Introduction To Parallel Algorithms and Genetic Algorithms, Monti-Carlo Methods, Amortised Analysis. TEXT BOOK: Total : 45
1. Sara Baase, "Computer Algorithms: Introduction to Design and Analysis", Addison Wesley, 1988. REFERENCES 1. T.H.Corman, C.E.Leiserson and R.L.Rioest, "Introduction to Algorithms", Mc Graw Hill, 1994. 2. E.Horowitz and S.Sahni, "Fundamentals of Computer Algorithms", Galgotia Publications, 1988. 3. D.E.Goldberg, "Genetic Algorithms: Search Optimization and Machine Learning", Addison Wesley, 1989.
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COM517
SOFT COMPUTING
3003
UNIT I 9 ARTIFICIAL NEURAL NETWORKS Supervised learning Neural networks-Introduction, Perception- Adaline, Back propagation- Multi layer perception- Unsupervised learning and other Neural networksIntroduction, Competitive learning networks, Kolonen self organizing networks, Learning vector quantization, Hebbian learning, Hopfield network , Content addressable nature, Binary Hopfield network, Continuous-valued Hopfield network , Travelling Salesperson problem. UNIT II 9 FUZZY SET THEORY Fuzzy sets, Basic definitions and terminology, Member function formulation & parameterization, Fuzzy rules , fuzzy reasoning - Extension principle, Fuzzy relation, Fuzzy inference systems: Mamdani model, Sugeno model. Tsukamoto model, Input space partitioning, Fuzzy modeling. UNIT III 9 OPTIMIZATION Derivative based optimization-Descent methods, Method of steepest descent, Classical Newtons method, Step-size determination; Derivative free optimization- Genetic algorithm, Simulated annealing, Random search, Downhill search. UNIT IV 9 ADVANCED NEURO-FUZZY MODELLING Classification and regression trees: decision tress, Cart algorithm Data clustering algorithms: K means clustering, Fuzzy C means clustering, Mountain clustering, Subtractive clustering rule base structure , Input space partitioning, rule based organization, focus set based rule combination; Neuro fuzzy control: Feedback Control Systems, Expert Control, Inverse Learning, Specialized Learning, Back propagation through Real Time Recurrent Learning. UNIT V 9 GENETIC ALGORITHM Fundamentals of genetic algorithm- Basic concepts, creation of offsprings, Working principle , Encoding Binary, Octal , Hex, Permutation, Value and tree, ReproductionRoulette-wheel selection, Boltzman selection, Tournament selection, Rank selection, Steady state selection, Crossover single site, Two point, Multi point, Uniform and matrix, Crossover rate, Inversion , Deletion and duplication ,Deletion and Regeneration, Segregation, Crossover, Mutation, Generational cycle. Total: 45 TEXT BOOK: 1. Jang J.S.R.,Sun C.T and Mizutani E Neuro Fuzzy and Soft computing, Pearson education (Singapore) 2004.
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REFERENCES: 1. S.Rajasekaran and G.A.Vijayalakshmi Pai Neural networks, Fuzzy logics, and Genetic algorithms, Prentice Hall of India,2003. 2. David E.Goldberg : Genetic Algorithms in Search, Optimization, and Machine Learning, Pearson Education, Asia,1996 3. Laurene Fauseett: Fundamentals of Neural Networks, Prentice Hall India, New Delhi, 1994. 4. Timothy J.Ross: Fuzzy Logic Engineering Applications, McGraw Hill, New York, 1997.
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COM 519
INTERNETWORKING MULTIMEDIA
3003
UNIT I 9 MULTIMEDIA NETWORKING Digital sound, video and graphics, basic multimedia networking, multimedia characteristics, evolution of Internet services model, network requirements for audio/ video transform, multimedia coding and compression for text, image, audio and video. UNIT II 9 BROADBAND NETWORK TECHNOLOGY Broadband services, ATM and IP, IPV6, High speed switching, resource reservation, Buffer management, traffic shaping, caching, scheduling, and policing, throughput, delay and jitter performance. Storage and media services, voice and video over IP, MPEG-2 over ATM/IP, indexing synchronization of requests, recording and remote control. UNIT III 9 RELIABLE TRANSPORT PROTOCOL AND APPLICATIONS Multicast over shared media network, multicast routing and addressing, scaling multicast and NBMA networks, Reliable transport protocols, TCP adaptation algorithm, RTP, RTCP. MIME, Peer- to-Peer computing, shared application, video conferencing, centralized and distributed conference control, distributed virtual reality, light weight session philosophy. UNIT IV 9 MULTIMEDIA COMMUNICATION STANDARDS Objective of MPEG- 7 standard, Functionalities and systems of MPEG-7, MPEG-21 Multimedia Framework Architecture, - Content representation, Content Management and usage, Intellectual property management, Audio visual system- H322: Guaranteed QOS LAN systems; MPEG_4 video Transport across internet. UNIT V 9 MULTIMEDIA COMMUNICATION ACROSS NETWORKS Packet Audio/video in the network environment, video transport across Generic networks- Layered video coding, error Resilient video coding techniques, Scalable Rate control, Streaming video across Internet, Multimedia transport across ATM networks and IP network, Multimedia across wireless networks. Total : 45 TEXT BOOK: 1. Jon Crowcroft, Mark Handley, Ian Wakeman, Internetworking Multimedia, Harcourt Asia Pvt. Ltd. Singapore, 1998. REFERENCES: 1. B.O. Szuprowicz, Multimedia Networking, McGraw Hill, Newyork. 1995 2. Tay Vaughan, Multimedia - Making it to work, 4ed, Tata McGraw Hill , New Delhi, 2000. 3. K.R.Rao, Zoran S. Bojkovic and Dragorad A. Milovanovic, Multimedia Communication systems, PHI , 2003 KCT- M.E [AE] I to IV Semester Curriculum and Syllabus R 2009 27/48
ANE514 DSP PROCESSOR ARCHITECTURE AND PROGRAMMING 3 0 0 3 UNIT I 9 FUNDAMENTALS OF PROGRAMMABLE DSPs Multiplier and Multiplier accumulator Modified Bus Structures and Memory access in P-DSPs Multiple access memory Multi-port memory VLIW architecture- Pipelining Special Addressing modes in P-DSPs On chip Peripherals. UNIT II 9 TMS320C5X PROCESSOR Architecture Assembly language syntax - Addressing modes Assembly language Instructions - Pipeline structure, Operation Block Diagram of DSP starter kit Application Programs for processing real time signals. UNIT III 9 TMS320C3X PROCESSOR Architecture Data formats - Addressing modes Groups of addressing modesInstruction sets - Operation Block Diagram of DSP starter kit Application Programs for processing real time signals Generating and finding the sum of series, Convolution of two sequences, Filter design Introduction to code composer studio UNIT IV 9 ADSP PROCESSORS Architecture of ADSP-21XX and ADSP-210XX series of DSP processors- Addressing modes and assembly language instructions Application programs Filter design, FFT calculation. UNIT V 9 ADVANCED DSP PROCESSORS Architecture of TMS320C54X: Pipe line operation, Code Composer studio - Architecture of TMS320C6X - Architecture of Motorola DSP563XX Comparison of the features of DSP family processors. Total : 45 TEXT BOOK: 1. B.Venkataramani and M.Bhaskar, Digital Signal Processors Architecture, Programming and Applications Tata McGraw Hill Publishing Company Limited. New Delhi, 2003. REFERENCES: 1. User guides Texas Instrumentation, Analog Devices, Motorola.
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COM521 HIGH PERFORMANCE COMMUNICATION NETWORKS
3003
UNIT I 9 PACKET SWITCHED NETWORKS OSI and IP models, Ethernet (IEEE 802.3), Token ring (IEEE 802.5), Wireless LAN (IEEE 802.11) FDDI, DQDB, SMDS: Internetworking with SMDS UNIT II 9 ISDN AND BROADBAND ISDN ISDN - overview, interfaces and functions, Layers and services - Signaling System 7 (SS7)- Broadband ISDN architecture and Protocols. UNIT III 9 ATM AND FRAME RELAY ATM: Main features-addressing, signaling and routing, ATM header structure-adaptation layer, management and control, ATM switching and transmission. Frame Relay: Protocols and services, Congestion control, Internetworking with ATM, Internet and ATM, Frame relay via ATM. UNIT IV 9 ADVANCED NETWORK ARCHITECTURE IP forwarding architectures overlay model, Multi Protocol Label Switching (MPLS), integrated services in the Internet, Resource Reservation Protocol (RSVP), Differentiated Services UNIT V 9 BLUE TOOTH TECHNOLOGY The Blue tooth module-Protocol stack Part I: Antennas, Radio interface, Base band, The Link controller, Audio, The Link Manager, The Host controller interface; The Blue tooth module-Protocol stack Part I: Logical link control and adaptation protocol, RFCOMM, Service discovery protocol, Wireless access protocol, Telephony control protocol. Total : 45 TEXT BOOK: 1. Jean Walrand and Pravin varaiya ,High Performance Communication networks,2nd edition, Harcourt and Morgan Kauffman,London,2000. REFERENCES: 1. William Stallings,ISDN and Broadband ISDN with Frame Relay and ATM, 4th edition, Pearson education Asia, 2002. 2. Leon Gracia, Widjaja, Communication networks ", Tata McGraw-Hill, New Delhi, 2000. 3. Jennifer Bray and Charles F.Sturman,Blue Tooth Pearson education Asia, 2001. 4. Sumit Kasera, Pankaj Sethi, ATM Networks ", Tata McGraw-Hill, New Delhi, 2000. 5. Rainer Handel, Manfred N.Huber and Stefan Schroder ,ATM Networks,3rd edition, Pearson education asia,2002. 6. C.Siva Ram Murthy and B.S.Manoj AdHoc Wireless Networks Architecture and protocols ,Pearson Education ,First Indian Reprint 2005
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COM522
HIGH SPEED SWITCHING ARCHITECTURE
3003
UNIT I 9 HIGH SPEED NETWORK: Introduction- LAN, WAN, Network evolution through ISDN to B-ISDN, Transfer mode and control of B-ISDN, SDH multiplexing structure, ATM standard, ATM adaptation layers. UNIT II 9 LAN SWITCHING TECHNOLOGY: Switching Concepts, switch forwarding techniques, switch path control, LAN Switching, cut through forwarding, store and forward, virtual LANs UNIT III 9 ATM SWITCHING ARCHITECTURE Switch model, ATM,QOS,Blocking networks - basic - and- enhanced banyan networks, sorting networks - merge sorting, re-arrangable networks - full-and- partial connection networks, non blocking networks - Recursive network construction, comparison of nonblocking network, Switching with deflection routing - shuffle switch, tandem banyan UNIT IV 9 QUEUES IN ATM SWITCHES Internal Queueing -Input, output and shared queueing, multiple queueing networks combined Input, output and shared queueing - performance analysis of Queued switches. UNIT V 9 IP SWITCHING Addressing model, IP Switching types - flow driven and topology driven solutions, IP Over ATM address and next hop resolution, multicasting, Photonic switching - Photonic switching architectures. Total : 45 TEXT BOOK: 1. Achille Pattavina, Swtching Theory: Architectures and performance in Broadband ATM networks "John Wiley & Sons Ltd, New York. 1998. REFERENCES: 1. Christopher Y Metz, Switching protocols & Architectures, McGraw Hill Professional Publishing, NewYork.1998. 2. Rainer Handel, Manfred N Huber, Stefan Schroder, ATM Networks Concepts Protocols, Applications III Edition, Addison Wesley, New York. 1999. 3. John A.Chiong: Internetworking ATM for the internet and enterprise networks. McGraw Hill, New York, 1998. 4. S.Kar and T.Srinivas, Optical fiber communications ,Priniciples and Practice,Tatav Mc Graw Hill ,2002.
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ANE515
ADVANCED PROCESSORS
3 0 0 3
UNIT I 9 MICROPROCESSOR ARCHITECTURE Instruction set Data formats Instruction formats Addressing modes Memory hierarchy register file Cache Virtual memory and paging Segmentation Pipelining The instruction pipeline pipeline hazards Instruction level parallelism reduced instruction set Computer principles RISC versus CISC RISC properties RISC evaluation. UNIT II 9 HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM The software model functional description CPU pin descriptions Addressing modes Processor flags Instruction set Bus operations Super scalar architecture Pipe lining Branch prediction The instruction and caches Floating point unit Programming the Pentium processor. UNIT III 9 HIGH PERFORMANCE CISC ARCHITECTURE PENTIUM INTERFACE Protected mode operation Segmentation paging Protection multitasking Exception and interrupts - Input /Output Virtual 8086 model Interrupt processing. UNIT IV 9 HIGH PERFORMANCE RISC ARCHITECTURE: ARM The ARM architecture ARM assembly language program ARM organization and implementation The ARM instruction set - The thumb instruction set. UNIT V 9 SPECIAL PURPOSE PROCESSORS Altera Cyclone Processor Audio codec Video codec design Platforms General purpose processor Digital signal processor Embedded processor Media Processor Video signal Processor Custom Hardware Co-Processor. Total : 45 TEXT BOOK: 1. Daniel Tabak, Advanced Microprocessors McGraw Hill.Inc., 1995. 2. James L. Antonakos, The Pentium Microprocessor , Pearson Education, 1997. REFERENCES: 1. Steve Furber, ARM System On Chip architecture Addison Wesley, 2000. 2. Gene .H.Miller. Micro Computer Engineering, Pearson Education, 2003. 3. Barry.B.Brey, The Intel Microprocessors Architecture, Programming and Interfacing , PHI, 2002. 4. Valvano "Embedded Microcomputer Systems" Thomson Asia PVT LTD first reprints 2001. 5. Iain E.G.Richardson, Video codec design, John Wiley & sons Ltd, U.K, 2002
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ANE516
VLSI SIGNAL PROCESSING
3 0 0 3
UNIT I 9 INTRODUCTION TO DSP SYSTEMS Introduction To DSP Systems -Typical DSP algorithms; Iteration Bound data flow graph representations, loop bound and iteration bound, Longest path Matrix algorithm; Pipelining and parallel processing Pipelining of FIR digital filters, parallel processing, pipelining and parallel processing for low power. UNIT II 9 RETIMING Retiming - definitions and properties; Unfolding an algorithm for Unfolding, properties of unfolding, sample period reduction and parallel processing application; Algorithmic strength reduction in filters and transforms 2-parallel FIR filter, 2-parallel fast FIR filter, DCT algorithm architecture transformation, parallel architectures for rank-order filters, Odd- Even Merge- Sort architecture, parallel rank-order filters. UNIT III 9 FAST CONVOLUTION Fast convolution Cook-Toom algorithm, modified Cook-Took algorithm; Pipelined and parallel recursive and adaptive filters inefficient/efficient single channel interleaving, Look- Ahead pipelining in first- order IIR filters, Look-Ahead pipelining with power-oftwo decomposition, Clustered Look-Ahead pipelining, parallel processing of IIR filters, combined pipelining and parallel processing of IIR filters, pipelined adaptive digital filters, relaxed look-ahead, pipelined LMS adaptive filter. UNIT IV 9 BIT-LEVEL ARITHMETIC ARCHITECTURES Scaling and roundoff noise- scaling operation, roundoff noise, state variable description of digital filters, scaling and roundoff noise computation, roundoff noise in pipelined first-order filters; Bit-Level Arithmetic Architectures- parallel multipliers with sign extension, parallel carry-ripple array multipliers, parallel carry-save multiplier, 4x 4 bit Baugh- Wooley carry-save multiplication tabular form and implementation, design of Lyons bit-serial multipliers using Horners rule, bit-serial FIR filter, CSD representation, CSD multiplication using Horners rule for precision improvement. UNIT V 9 PROGRAMMING DIGITAL SIGNAL PROCESSORS Numerical Strength Reduction sub expression elimination, multiple constant multiplications, iterative matching. Linear transformations; Synchronous, Wave and asynchronous pipelining- synchronous pipelining and clocking styles, clock skew in edge-triggered single-phase clocking, two-phase clocking, wave pipelining, asynchronous pipelining bundled data versus dual rail protocol; Programming Digital Signal Processors general architecture with important features; Low power Design needs for low power VLSI chips, charging and discharging capacitance, short-circuit current of an inverter, CMOS leakage current, basic principles of low power design. Total : 45 KCT- M.E [AE] I to IV Semester Curriculum and Syllabus R 2009 32/48
TEXT BOOK: 1. Keshab K.Parhi, VLSI Digital Signal implementation, Wiley, Inter Science, 1999. REFERENCES: 1. Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998. 2. Mohammed Isamail and Terri Fiez, Analog VLSI Signal and Information Processing, Mc Graw-Hill, 1994. 3. S.Y. Kung, H.J. White House, T. Kailath, VLSI and Modern Signal Processing, Prentice Hall, 1985. 4. Jose E. France, Yannis Tsividis, Design of Analog - Digital VLSI Circuits for Telecommunication and Signal Processing, Prentice Hall, 1994. Processing systems, Design and
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ANE517
ANALOG VLSI DESIGN
3 0 0 3
UNIT I 9 BASIC CMOS CIRCUIT TECHNIQUES, CONTINUOUS TIME AND LOWVOLTAGESIGNAL PROCESSING: Mixed-Signal VLSI Chips-Basic CMOS Circuits-Basic Gain Stage-Gain Boosting Techniques-Super MOSTransistor- Primitive Analog Cells-Linear Voltage-Current Converters-MOS Multipliers and Resistors-CMOS,Bipolar and Low-Voltage BiCMOS Op-Amp Design-Instrumentation Amplifier Design-Low Voltage Filters. UNIT II 9 BASIC BICMOS CIRCUIT TECHNIQUES, CURRENT -MODE SIGNAL PROCESSING AND NEURAL INFORMATION PROCESSING Continuous-Time Signal Processing-Sampled-Data Signal Processing-Switched-Current Data Converters-Practical Considerations in SI Circuits Biologically-Inspired Neural Networks - Floating - Gate, Low-Power Neural Networks-CMOS Technology and Models-Design Methodology-Networks-Contrast Sensitive Silicon Retina. UNIT III 9 SAMPLED-DATA ANALOG FILTERS, OVER SAMPLED A/D CONVERTERS AND ANALOG INTEGRATED SENSORS First-order and Second SC Circuits-Bilinear Transformation - Cascade Design-SwitchedCapacitor Ladder Filter-Synthesis of Switched-Current Filter- Nyquist rate A/D Converters-Modulators for Over sampled A/D Conversion-First and Second Order and Multibit Sigma-Delta Modulators-Interpolative Modulators Cascaded ArchitectureDecimation Filters-mechanical, Thermal, Humidity and Magnetic Sensors-Sensor Interfaces. UNIT IV 9 DESIGN FOR TESTABILITY AND ANALOG VLSI INTERCONNECTS Fault modelling and Simulation - Testability-Analysis Technique-Ad Hoc Methods and General Guidelines-Scan Techniques-Boundary Scan-Built-in Self Test-Analog Test Buses-Design for Electron -Beam Testablity-Physics of Interconnects in VLSI-Scaling of Interconnects-A Model for Estimating Wiring Density-A Configurable Architecture for Prototyping Analog Circuits. UNIT V 9 STATISTICAL MODELING AND SIMULATION, ANALOG COMPUTER-AIDED DESIGN AND ANALOG AND MIXED ANALOG-DIGITAL LAYOUT Review of Statistical Concepts - Statistical Device Modeling- Statistical Circuit Simulation-Automation Analog Circuit Design-automatic Analog Layout-CMOS Transistor Layout-Resistor Layout-Capacitor Layout-Analog Cell Layout-Mixed Analog -Digital Layout. Total : 45
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TEXT BOOK: 1. Mohammed Ismail, Terri Fiez, Analog VLSI signal and Information Processing ", McGraw-Hill International Editons, 1994. REFERENCES: 1. Malcom R.Haskard, Lan C.May, Analog VLSI Design - NMOS and CMOS ", Prentice Hall, 1998. 2. Randall L Geiger, Phillip E. Allen, " Noel K.Strader, VLSI Design Techniques for Analog and Digital Circuits ", Mc Graw Hill International Company, 1990. 3. Jose E.France, Yannis Tsividis, Design of Analog-Digital VLSI Circuits for Telecommunication and signal Processing ", Prentice Hall, 1994
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ANE518
COMPUTER AIDED DESIGN OF VLSI CIRCUITS
3 0 0 3
UNIT I 9 VLSI DESIGN METHODOLOGIES Introduction to VLSI Design methodologies - Review of Data structures and algorithms Review of VLSI Design automation tools - Algorithmic Graph Theory and Computational Complexity - Tractable and Intractable problems - general purpose methods for combinatorial optimization. UNIT II 9 LAYOUT & PARTITIONING Layout Compaction - Design rules - problem formulation - algorithms for constraint graph compaction - placement and partitioning - Circuit representation - Placement algorithms - partitioning UNIT III 9 FLOORPLANNING & ROUTING Floor planning concepts - shape functions and floor plan sizing - Types of local routing problems - Area routing - channel routing - global routing - algorithms for global routing. UNIT IV 9 SIMULATION & SYNTHESIS Simulation - Gate-level modeling and simulation - Switch-level modeling and simulation - Combinational Logic Synthesis - Binary Decision Diagrams - Two Level Logic Synthesis. UNIT V 9 HIGH LEVEL SYNTHESIS High level Synthesis - Hardware models - Internal representation - Allocation assignment and scheduling - Simple scheduling algorithm - Assignment problem High level transformations. Total : 45 TEXT BOOK: 1. S.H. Gerez, "Algorithms for VLSI Design Automation", John Wiley & Sons, 2002. REFERENCES 1. N.A. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwar Academic Publishers, 2002. 2. Drechsler, R., Evolutionary Algorithms for VLSI CAD, Kluwer Academic Publishers, Boston, 1998. 3. Hill, D., D. Shugard, J. Fishburn and K. Keutzer, Algorithms and Techniques for VLSI Layout Synthesis, Kluwer Academic Publishers, Boston, 1989.
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MAT507
STOCHASTIC MODELS AND SIMULATION
UNIT I INTRODUCTION TO PROBABILITY 9 Sample space and events; Probability axiom; Conditional probability; Independent events, Bayes formula, Simple problems. UNIT II RANDOM VARIABLE & DISTRIBUTIONS 9 Random Variables, Distribution functions, continuous and discrete random variables, Bernoulli, Binomial, Geometric, Poisson random variables, uniform, exponential, normal random variables, jointly distributed random variables, expectations and moment generating functions, Properties, simulation samples for the above mentioned distributions. UNIT III MARKOV CHAINS 9 Markov chains, Chapman Kolmogorov equations, Classification of states, examples of Markov chains. Gamblers ruin problem, mean time spent in transient states, Branching process. UNIT IV POISSON PROCESSES 9 Properties of exponential distribution, convolution of exponential random variables, Poisson process. Inter arrival of waiting time distribution, Applications to reliability problems, Estimating software reliability. UNIT V RENEWAL THEORY, QUEUING THEORY & SIMULATION 9 Renewal Theory - examples, distribution of the counting process N(t), alternating renewal process, Regenerative process, computing the renewal function, semi Markov process, Computation of renewal function, Poisson process as a renewal process. Single server exponential queuing system, Queue with finite capacity, Shoe shine shop, network of queues, open and closed systems. Methods of simulation of random variables - Inverse transformation method, Rejection method. TEXT BOOK: 1. Sheldon M. Ross, Introduction to Probability Models, Academic press, 2005. REFERENCES: 1. Karlin and H.M. Tailor, A First Course in Stochastic Processes, Academic Press, 1975. 2. Sheldon M.Ross, A First Course in Probability, Sixth Edition, Prentice Hall, New Jersey, 2002.
L: 45
T: 15
Total : 60
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CSE501
DATA STRUCTURES AND ALGORITHMS
3003
UNIT I COMPLEXITY ANALYSIS & ELEMENTARY DATA STRUCTURES 9 Asymptotic Notations Properties of Big Oh Notation Asymptotic Notation with Several Parameters Conditional Asymptotic Notation Amortized Analysis NPCompleteness NP-Hard Recurrence Equations Solving Recurrence Equations Arrays Linked Lists Trees. UNIT II HEAP STRUCTURES 9 Min-Max Heaps Deaps Leftist Heaps Binomial Heaps Fibonacci Heaps Skew Heaps Lazy- Binomial Heaps. UNIT III SEARCH STRUCTURES 9 Optimal Binary Search Trees AVL Trees 2-3 Trees 2-3-4 Trees Red-Black Trees B-Trees Splay Trees Tries. UNIT IV DESIGN TECHNIQUES - GREEDY, DIVIDE AND CONQUER 9 Tree Vertex Splitting Job Sequencing with Deadlines Optimal Storage on Tapes Quick Sort Strassens Matrix Multiplication Convex Hull Problem. UNIT V DYNAMIC PROGRAMMING AND BACKTRACKING 9 Multistage Graphs 0/1 Knapsack using Dynamic Programming Flow Shop Scheduling 8-Queens Problem Graph Coloring Knapsack Using Backtracking. Total : 45 TEXT BOOKS: 1. G.Brassard and P.Bratley, Fundamentals of Algorithmics, Printice Hall, 1996. (Unit I) 2. E. Horowitz, S.Sahni and Dinesh Mehta, Fundamentals of Data structures in C++ , Galgotia , 1999.( Unit II & III ) 3. E. Horowitz, S.Sahni and S. Rajasekaran, Fundamentals of Computer Algorithms , Galgotia, 1999.( Unit IV & V )
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CSE502
ADVANCED COMPUTER ARCHITECTURE
3 0 0
UNIT I FUNDAMENTALS OF COMPUTER DESIGN 9 Introduction- Classes of Computers- Defining Computer Architecture- Trends in Technology- Dependability- Measuring, Reporting and Summarizing PerformanceQuantitative Principles of Computer Design. Instruction set Principles: Introduction-Classifying Instruction set Architectures- Memory Addressing- Type and Size of Operands- Operations in the Instruction set - Instructions for Control Flow- Encoding an Instruction set. UNIT II INSTRUCTION LEVEL PARALLELISM 10 Pipelining: Introduction- The Major Hurdle of PipeliningPipeline Hazards. Instruction Level Parallelism: Concepts and Challenges- Basic Compiler Techniques for Exposing ILP- Reducing Branch Costs with Prediction - Overcoming Data Hazards with Dynamic Scheduling- Hardware Based Speculation- Exploiting ILP using Multiple Issue and Static Scheduling- Exploiting ILP using Dynamic Scheduling, Multiple Issues and Speculation. UNIT III LIMITS ON ILP 8 Limits on Instruction-Level Parallelism: Introduction- Studies of the Limitations of ILPLimitations on ILP for Realizable processors- Crosscutting Issues: Hardware versus Software speculation- Multithreading: Using ILP Support to exploit Thread-Level Parallelism. UNIT IV MULTIPROCESSORS AND THREAD -LEVEL PARALLELISM 9 Introduction- Symmetric Shared-Memory Architectures- Performance of Symmetric Shared- Memory Multiprocessors- Distributed Shared Memory and Directory-Based Coherence- Synchronization The Basics- Models of Memory consistency an Introduction- Crosscutting Issues. UNIT V MEMORY HIERARCHY DESIGN AND I/O 9 Memory Hierarchy Design: Introduction- Eleven Advanced Optimizations of Cache Performance Memory Technology and Optimizations- Protection: Virtual Memory and Virtual Machines. Storage Systems: Introduction- Advanced Topics in Disk Storage- Definition and Examples of Real Faults and Failures-I/O Performance, Reliability Measures and Benchmarks. Total : 45
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TEXT BOOK: 1. John L. Hennessey and David A. Patterson," Computer Architecture: A Quantitative Approach", Fourth Edition, Morgan Kaufmann, 2007. REFERENCES: 1. D. Sima, T. Fountain and P. Kacsuk, " Advanced Computer Architectures: A Design Space Approach", Addison Wesley, 2000. 2. Kai Hwang Advanced computer architecture Parallelism Scalability Programmability" Tata McGraw Hill Edition 2001. 3. Vincent P.Heuring, Harry F.Jordan, Computer System Design and Architecture, Addison Wesley, 2nd Edition 2004.
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CSE 504 NETWORK ENGINEERING 3 1 0 4 UNIT I NETWORK ARCHITECTURE AND QUEUING ANALYSIS 12 Internet Architecture Link and Medium Access Protocol: Design Issues - Case Study: Ethernet Token Rings Wireless Local Area Networks. Queuing Analysis- Queuing Models Single Server Queues Multiple Server Queues. UNIT II NETWORK LAYER AND ROUTING TECHNIQUES 7 Circuit Switching Packet Switching Switching and Forwarding Bridges and LAN Switches Cell Switching Internetworking Routing Techniques: Distance Vector Routing Link State Routing Routing Information Protocol (RIP) Open Shortest Path First (OSPF) Subnetting Classless Inter Domain Routing (CIDR). UNIT III TCP AND CONGESTION CONTROL 11 User Datagram Protocol (UDP) Transmission Control Protocol (TCP) TCP Flow Control - Effects of Congestion Congestion Control Traffic Management Congestion Control in Packet Switching Networks TCP Congestion Control Retransmission Timer Management Exponential Timer backoff KARNs Algorithm - Congestion Avoidance Mechanisms. UNIT IV NETWORK SECURITY AND APPLICATION 9 Cryptographic Algorithms Data Encryption Standard (DES) Rivest, Shamir and Adleman (RSA) Algorithm Message Digest 5 (MD5) Security Mechanisms Fire Walls Name Service Traditional Applications Simple Mail Transfer Protocol (SMTP) Hyper Text Transfer Protocol (HTTP) Multimedia Applications: Real Time Transfer Protocol (RTP) Real Time Control Protocol (RTCP). UNIT V NETWORK MANAGEMENT 6 Introduction Network Monitoring Network Control Simple Network Management Protocol Version I (SNMPV I) Network Management Concepts Information Standard MIBs. L: 45 T: 15 Total : 60 TEXT BOOKS: 1. Larry L.Peterson and Brule S.Davie, Computer Networks A System Approach MarGankangmann Harcourt Asia, Third Edition, 2003 2. William Stallings, HIGH SPEED NETWORKS AND INTERNET, Pearson Education, Second Edition, 2002 3. William Stallings, SNMP, SNMP V2, SNMPV3, RMON 1 and 2, 3rd Edition. Addison Wesley, 6th Indian reprint 2002 (Unit V).
[
REFERENCES: 1. J.F Kurose and K.W. Ross, Computer Networking A top down approach featuring the internet, Addison Wesley, 2001. 2. Mani Subramanian, Network Management: Principles and Practice, Addison Wesley, 2000.
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CSE505
OBJECT ORIENTED SOFTWARE ENGINEERING 3 0 0 3
UNIT I INTRODUCTION TO SOFTWARE ENGINEERING AND MODELING WITH UML 9 Software Related Problems Software Engineering Concepts Development Models and Activities. Modeling with UML. Project Organization Concepts - Project Communication Concepts Organization Activities. UNIT II REQUIREMENTS ELICITATION AND ANALYSIS 9 Requirements Elicitation - Concepts & Managing Requirements. Analysis Overview Concepts - Activities and Managing Analysis. UNIT III SYSTEM DESIGN 9 Design Overview Concepts - Activities and Managing System Design Object Design Overview Concepts - Activities and Managing Object Design UNIT IV TESTING AND RATIONALE MANAGEMENT Testing Overview Concepts - Activities and Managing Rationale Overview Concepts - Activities and Managing Rationale. 9 Testing.
UNIT V SOFTWARE CONFIGURATION AND PROJECT MANAGEMENT 9 Configuration Management Overview Concepts - Activities Managing Changes. Project Management Overview Concepts and Project Management Activities. Total : 45 TEXT BOOK: 1. Bernd Bruegge and Allen H. Dutoit, Object-Oriented Software Engineering Using UML, Pattern and Java, Pearson Education, 2nd Edition, 2004. REFERENCES: 1. Roger S. Pressman., Software Engineering: A Practitioners Approach (Sixth Edition), McGraw Hill, 2005. (UNIT I) 2. Ali Bahrami, Object Oriented System Development, Mc Graw Hill International Edition, 1999. 3. Martin Fowler, UML Distilled, PHI/Pearson Education, 2nd Edition, 2002.
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CSE506
WEB TECHNOLOGY
3 0 0 3
UNIT I INTRODUCTION 9 History of the Internet and World Wide Web Introduction to HTML - Protocols HTTP, SMTP, POP3, MIME, and IMAP. Introduction to JAVA Script Object Based Scripting for the Web- Control structures Functions Arrays Objects- Client-Side Scripting with VB Script UNIT II COMMON GATEWAY INTERFACE AND DYNAMIC HTML 9 Common Gateway Interface: How CGI works-CGI Script Structure-Environment Variables-Server-Side Includes- DHTML: Introduction Cascading Style Sheets- Object Model and Collections-Event Model Filters and Transitions-Data Binding with Tabular Data Control. UNIT III MULTIMEDIA, ECOMMERCE AND WEB SERVERS 9 Audio and Video Speech Synthesis and Recognition - Electronic Commerce EBusiness Model E- Marketing Online Payments -Security Web Servers Introduction- HTTP Request Types System Architecture-Client Side Versus Server Side Scripting -Accessing Web Servers IIS Apache Web Server. UNIT IV DATABASE- ASP XML 9 Database: Introduction- Relational Database Model Overview - SQL ASP : Working of ASP Objects File System Objects Session Tracking and Cookies ADO Access a Database from ASP Server Side ActiveX Components XML : IntroductionStructuring Data Name spaces DTD and Schemas DOM XSL-SAX . UNIT V SERVLETS AND JSP 9 Servlet : Introduction Overview and Architecture Handling HTTP Request Get and Post Request Redirecting Request Using JDBC from a Servlet JSP: Overview Implicit Objects Scripting Standard Actions Directives. Total: 45 TEXT BOOK: 1. H.M.Deitel ,P.J.Deitel & A.B.Goldberg , Internet and world wide web How to Program, Pearson Education Asia, 2006. REFERENCES: 1. Eric Ladd, Jim O Donnel, Using HTML 4, XML and JAVA, Prentice Hall of India QUE, 1999. 2. Rajkamal, Web Technology, Tata McGraw-Hill, 2001.
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ANE519
MOBILE COMPUTING
3003
UNIT I INTRODUCTION 9 Medium Access Control : Motivation for Specialized MAC- SDMA- FDMA- TDMACDMA- Comparison of Access mechanisms Tele communications : GSM- DECTTETRA UMTS- IMT-200 Satellite Systems: Basics- Routing- LocalizationHandover- Broadcast Systems: Overview Cyclic Repetition of Data- Digital Audio Broadcasting Digital Video Broadcasting UNIT II WIRELESS NETWORKS 9 Wireless LAN: Infrared Vs Radio Transmission Infrastructure Networks- Ad hoc Networks- IEEE 802.11 HIPERLAN Bluetooth- Wireless ATM: Working GroupServices- Reference Model Functions Radio Access Layer Handover- Location Management- Addressing Mobile Quality of Service- Access Point Control Protocol UNIT III MOBILE NETWORK LAYER 9 Mobile IP : Goals Assumptions and Requirement Entities IP packet DeliveryAgent Advertisement and Discovery Registration Tunneling and Encapsulation Optimization Reverse Tunneling IPv6 DHCP- Ad hoc Networks UNIT IV MOBILE TRANSPORT LAYER 9 Traditional TCP- Indirect TCP- Snooping TCP- Mobile TCP- Fast retransmit/ Fast Recovery- Transmission/ Timeout Freezing Selective Retransmission- Transaction Oriented TCP UNIT V WAP 9 Architecture Datagram Protocol- Transport Layer Security- Transaction ProtocolSession Protocol- Application Environment-Wireless Telephony Application Total : 45 TEXT BOOK: 1. J.Schiller, Mobile Communication, Addison Wesley, 2000. REFERENCES: 1. William Stallings, Wireless Communication and Networks, Pearson Education, 2003. 2. William C.Y.Lee, Mobile Communication Design Fundamentals, John Wiley, 1993. 3. Singhal, WAP-Wireless Application Protocol, Pearson Education, 2003.
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ANE520
CELLULAR AND MOBILE COMMUNICATION
3 0 03
UNIT I INTRODUCTION TO WIRELESS MOBILE COMMUNICATIONS 9 History and evolution of mobile radio systems. Types of mobile wireless services / systems - Cellular, WLL, Paging, Satellite systems, Standards, Future trends in personal wireless systems. UNIT II CELLULAR CONCEPT AND SYSTEM DESIGN FUNDAMENTALS 9 Cellular concept and frequency reuse, Multiple Access Schemes, Channel assignment and handoff, Interference and system capacity, Trunking and Erlang capacity calculations. UNIT III MOBILE RADIO PROPAGATION 9 Radio wave propagation issues in personal wireless systems, Propagation models, Multipath fading and base band impulse response models, Parameters of mobile multipath channels, Antenna systems in mobile radio. UNIT IV MODULATIONS AND SIGNAL PROCESSING 9 Analog and digital modulation techniques, Performance of various modulation techniques Spectral efficiency, Error-rate, Power Amplification, Equalization Rake receiver concepts, Diversity and space-time processing, Speech coding and channel coding. UNIT V SYSTEM EXAMPLES AND DESIGN ISSUES 9 Multiple Access Techniques FDMA, TDMA and CDMA systems, Operational systems, Wireless networking, design issues in personal wireless systems. Total : 45 TEXT BOOK: 1. Feher K., Wireless digital communications, PHI, New Delhi, 1995. REFERENCES: 1. Rappaport T.S., Wireless Communications; Principles and Practice, Prentice Hall, NJ, 1996. 2. Lee W.C.Y., Mobile Communications Engineering: Theory and Applications, Second Edition, McGraw-Hill, New York, 1998. 3. Schiller, Mobile Communications, Pearson Education Asia Ltd., 2000.
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ANE521
E-COMMERCE TECHNOLOGY
3 0 0 3
UNIT I INTRODUCTION 9 Infrastructure for Electronic Commerce - Networks - Packet Switched Networks - TCP/IP Internet protocol - Domain name Services - Web Service Protocols - Internet applications - Utility programs - Markup Languages - Web Clients and Servers - Intranets and Extranets - Virtual private Network. UNIT II CORE TECHNOLOGY 9 Electronic Commerce Models - Shopping Cart Technology - Data Mining Intelligent Agents Internet Marketing - XML and E-Commerce UNIT III ELECTRONIC PAYMENT SYSTEMS 9 Real world Payment Systems - Electronic Funds Transfer - Digital Payment -Internet Payment Systems Micro Payments - Credit Card Transactions - Case Studies. UNIT IV SECURITY 9 Threats to Network Security - Public Key Cryptography - Secured Sockets Layer Secure Electronic Transaction - Network Security Solutions - Firewalls. UNIT V INTER/INTRA ORGANIZATIONS ELECTRONIC COMMERCE 9 EDI - EDI application in business - legal, Security and Privacy issues - EDI and Electronic commerce - Standards - Internal Information Systems - Macro forces - Internal commerce - Workflow Automation and Coordination - Customization and Internal commerce - Supply chain Management. Total : 45 TEXT BOOK: 1. Ravi Kalakota and Andrew B Whinston , Frontiers of Electronic commerce, Addison Wesley, 1996 REFERENCES: 1. Pete Loshin, Paul A Murphy, Electronic Commerce, 2nd Edition, Jaico Publishers 1996. 2. David Whiteley, e - Commerce: Strategy, Technologies and Applications - McGraw Hill 2000.
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ANE522
REAL TIME AND EMBEDDED SYSTEMS
3003
UNIT I INTRODUCTION 9 Introduction to Embedded systems Processor and memory organization-Devices and buses for Device Networks Device drivers and Interrupt servicing mechanism. UNIT II RTOS 9 RTOS Programming tools Case studies- Hardware- software Code design in an Embedded system UNIT III REAL TIME SYSTEMS 9 Basic Real time concepts Computer hardware Language issues Software life Cycle UNIT IV REAL TIME SPECIFICATIONS 9 Design techniques Real-time kernels Intertask communication and synchronization Real time memory management UNIT V MULTIPROCESSING SYSTEMS 9 Multiprocessing Systems - Hardware/Software integration- Real time Applications Total : 45 TEXT BOOK: 1. Raj Kamal, Embedded Systems Architecture, Programming and Design, Tata McGraw-Hill, 2003 REFERENCES: 1. Phillip A.Laplante, Real Time Systems Design and Analysis, An Engineers Handbook, Prentice-Hall of India, 2002 2. R.J.A.Buhr, D.L.Bailey, An Introduction to Real Time Systems: Design to networking with C/C++, Prentice- Hall, International, 1999. 3. Grehan Moore and Cyliax, Real Time Programming: A guide to 32 Bit Embedded Development Reading: Addison- Wisley-Longman, 1998. 4. Haeth, Steve, Embedded systems Design, Newnes, 1997.
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ANE523
VISUALIZATION TECHNIQUES
3003
UNIT I FOUNDATIONS FOR DATA VISUALIZATION 9 Visualization Stages-Experimental Semiotics based on Perception Gibsons Affordance theory A Model of Perceptual Processing Types of Data. UNIT II COMPUTER VISUALIZATION 9 Non-Computer Visualization-Computer Visualization - Exploring Complex Information Spaces Fisheye Views Applications Comprehensible Fisheye views Fisheye views for 3D data Non Linear Magnification Comparing Visualization of Information Spaces- Abstraction in computer Graphics- Abstraction in user interfaces. UNIT III MULTIDIMENSIONAL VISUALIZATION 9 1D-2D-3D- Multiple Dimensions-trees-web Works Data Mapping: Document Visualization Workspaces. UNIT IV TEXTUAL METHODS OF ABSTRACTION 9 From Graphics to pure Text- Figure Captions in Visual Interfaces Interactive 3D illustrations with images and text Related Work- Consistency of rendered images and their textual labels- Architecture- Zoom techniques for illustration purpose- Interactive handling of images and text. UNIT V 9 Animating non Photo realistic Computer Graphics Interaction Facilities and High Level Support for Animation Design Zoom Navigation in User Interfaces Interactive Medical Illustrations Rendering Gestural Expressions Animating design for Simulation Tactile Maps for Blind people Synthetic Holography Abstraction Versus Realism Integrating Spatial and Non Spatial Data. Total : 45 TEXT BOOKS: 1. Colin Ware, Morgen Kaufmen, Information Visualization Perception for Design, 2nd Edition, Morgan Kaufmann, 2004. 2. Stuart.K.Card, Jock.D.Mackinley and Ben Shneiderman, Readings in Information Visualization Using Vision to Think, Morgan Kaufmann Publishers, 1999. REFERENCE: 1. Thomas Strothotte, Computer Visualization Graphics Interactivity, Springer Verlag Berlin Heiderberg 1998.
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Signature of The Chairman BOS M.E (AE) : KCT-M.E (AE) - I To IV Semester Curriculum and Syllabus R - 2009

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Signature of The Chairman BOS M.E (AE) : KCT-M.E (AE) - I To IV Semester Curriculum and Syllabus R - 2009

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KUMARAGURU COLLEGE OF TECHNOLOGY, COIMBATORE-6 (An Autonomous College Affiliated to Anna University, Coimbatore) M.E.

KCT- M.E [AE] I to IV Semester Curriculum and Syllabus R 2009