IC Tech

<1> Chapter 1: IC Overview
IC Technology Overview
1. Why learn IC
2. History and trends
3. Economy
4. Materials
5. Semiconductor basic physics
6. Process overview
Sources and References:
1. Slides from Prof. Jaeger, Auburn University
2. IC Technology open course materials, MIT
<2> Chapter 1: IC Overview UTD | EE 4330: IC Technology -Dr. W. Hu |
Why Learn IC Fab?
Most important technology
In the coming decade?
IEEE Spectrum 2004 November
Most important technology
In the last 40 years?
Integrated Circuits
Nano; Bio
Internet
Wireless
Integrated circuits were an essential breakthrough in electronics -- allowing a large amount of circuitry to
be mass-produced in reusable components with high levels of functionality.
Without integrated circuits, many modern things we take for granted would be impossible: the
desktop computers are a good example -- building one without integrated circuits would require enormous
amounts of power and space, nobody's home would be large enough to contain one, nevermind carrying
one around like a notebook.
Before IC is invented
UTD | EE 4330: IC Technology -Dr. W. Hu |
ENIAC or Electronic Numerical Integrator And Computer, 1946
Besides its speed, the most remarkable thing about ENIAC was its size and complexity. ENIAC contained
17,468 vacuum tubes, 7,200 crystal diodes, 1,500 relays, 70,000 resistors, 10,000 capacitors and around 5
million hand-soldered joints. It weighed 30 short tons (27 t), was roughly 8.5 feet by 3 feet by 80 feet (2.6 m
by 0.9 m by 26 m), took up 680 square feet (63 m), and consumed 150 kWof power.
First Transistor
3 inventors (John
Bardeen, Walter
Brattain, and
William Shockley) share
Nobel prize
1947
1st transistor
AT&T Bell Lab
Sources: http://roiconnect.com/transistor.htm
http://www.pbs.org/transistor/science/events/silicont1.html
1st commercially
successful TR
Raytheon CK722,
1953
Ge-based pnp low
power TR
Source: http://www.lucent.com/minds/transistor/
1st Si transistor
made by Gordon
Teal at TI in
1954
Integrated Circuit Inventors
1958, Jack Kilby,
Texas Instrument
Nobel Prize in Physics in 2000
Integrated Circuit (IC):
a large number of individual components
(transistors, resistors, capacitors, etc.)
fabricated side by side on a common
substrate and wired together to perform a
particular circuit function.
Sources: http://www.ti.com/corp/docs/kilbyctr/jackbuilt.shtml;
http://www.maxmon.com/1926ad.htm; Intel
In 1962, Steven Hofstein and Fredric Heiman at the
RCA research laboratory in Princeton, New Jersey,
invented a new family of devices called metal-oxide
semiconductor field-effect transistors (MOS FETs for
short). Although these transistors were somewhat
slower than bipolar transistors, they were cheaper,
smaller and used less power. Also of interest was the
fact that modified metal-oxide semiconductor
structures could be made to act as capacitors or
resistors.
Andy Grove,
Robert Noyce,
and Gordon
Moore with
Intel 8080 layout.
Semiconductor Industry Roadmap
Each new process generation doubles chip density by scaling feature size by 0.7.
ITRS Link: http://public.itrs.net/
Moores Law
Source: Intel, Gordon Moore, presentation at ISSC 2003
Moores Law
The number of transistors per square inch
on integrated circuits doubles every year,
later every 1.5 year.
IC Manufacturing Cost
100 nano$ per transistor!
IC Market
IC Technology Market
MOS
BJT
Compound
Digital MOS
Analog MOS
Memories
MPU
ASICs
Misc.
CMOS
TTL
Analog BJT
NMOS
GaAs
ECL
BiCMOS
How the IC Fabricated?
http://www.necel.com/en/cprofile/fab/index.html
Planar Fabrication Process
Periodic Table
Source: http://www.pmel.org/HandBook/PeriodicTable/periodic.htm
Properties of Semiconductors
From Appendix III, Streetman and Banerjee
Lattice a Density Bandgap Eg n p
[] [g/cm^3] style [eV] [cm^2/V-s] [cm^2/V-s]
Si Diamond 5.43 2.33 indirect 1.11 1350 480
Ge Diamond 5.65 5.32 indirect 0.67 3900 1900
GaAs Zincblende 5.65 5.31 direct 1.43 8500 400
InP Zincblende 5.87 4.79 direct 1.35 4000 100
GaN Z,W 4.5 6.1 direct 3.4 380
CdS Z,W 4.137 4.82 direct 2.42 250 15
InSb Zincblende 6.48 5.78 direct 0.18 10^5 1700
Si
crystal
Why Si in IC?
Germanium was used as the original semiconductor material. Later, silicon
became the material of choice for ICs.
Why Si?
Band gap (>> operating temperature)
Si (1.12 eV), Ge (0.66 eV)
Si can be operated up to ~ 150 C while Ge can be operated up to ~ 100 C.
Ease of fabrication of passivation layer
GeO
2
Difficult to form, water soluble, dissociates at 800 C.
SiO
2
Easy to form, chemically stable
Cost
Si
Abundant, cheap (~ 10 times cheaper than Ge)
Si: facts
From Latin word silex or silicis that means flint
Si is the 2
nd
most abundant (25.7% by weight) on earths crust (1
st
: oxygen)
Why Compound Semiconductors?
Uniqueness of compound semiconductors
Band gap engineering
Heterostructure devices
Hg
1-x
Cd
x
Te : -0.25 ~ 1.6 eV
Al
x
Ga
1-x
As :
AlAs : 2.16 eV, indirect
GaAs : 1.43 eV, direct
Larger electron and/or hole mobility
Good for high speed (high frequency) devices
Direct band gap materials
Optoelectronic devices (lasers, LEDs)
Compound semiconductor processing
Cost
Compound material growth is not cheap.
Difficulty of fabrication (example: GaAs)
Doping
Some dopants are amphoteric. (Donor in the Ga site and acceptor in the As site).
Oxidation
Ge
2
O
3
and As
2
O
3
: oxidation rates are different.
Si Covalent Bond
Near absolute zero, all bonds are complete.
Each Si atom contributes one electron to
each of the four bond pairs.
Increasing temperature adds energy to the
system and breaks bonds in the lattice,
generating electron-hole pairs.
Intrinsic conductivity: 10
10
cm
-3
at 23C
Band Gap and Fermi Level
UTD | Fall 2007|EE/MSEN 6322 Semiconductor Processing Technology
-Dr. W. Hu
] / ) exp[(
2
*
2
c F
3/2
2
kT E E
kT m
n
e
|
.
|
\
|
=
t
] / ) exp[(
2
*
2
F v
3/2
2
h
kT E E
kT m
p |
.
|
\
|
=
t
Intrinsic Carrier Concentration
The density of carriers in a semiconductor as a function of
temperature and material properties is:
E
G
= semiconductor bandgap energy in eV (electron volts)
k = Boltzmanns constant, 8.62 x 10
-5
eV/K
T = absolute temperature, K
B = material-dependent parameter, 1.08 x 10
31
K
-3
cm
-6
for Si
Bandgap energy is the minimum energy needed to free an electron
by breaking a covalent bond in the semiconductor crystal.
6 -
G
i
cm
kT
E
exp BT n
|
.
|
\
|
=
3 2
Intrinsic Carrier Concentration
Electron density is
n (electrons/cm
3
)
and n
i
for intrinsic
material n = n
i
.
Intrinsic refers to
properties of pure
materials.
n
i
10
10
cm
-3
for Si
Electron-Hole Concentrations
A vacancy is left when a covalent bond is broken.
The vacancy is called a hole.
A hole moves when the vacancy is filled by an electron
from a nearby broken bond (hole current).
Hole density is represented by p.
For intrinsic silicon, n = n
i
= p.
The product of electron and hole concentrations is pn =
n
i
2
.
The pn product above holds when a semiconductor is
in thermal equilibrium (not with an external voltage
applied).
Drift Current
Electrical resistivity and its reciprocal, conductivity o,
characterize current flow in a material when an electric field is
applied.
Charged particles move or drift under the influence of the
applied field.
The resulting current is called drift current.
Drift current density is
j = Qv (C/cm
3
)(cm/s) = A/cm
2
j = current density, (Coulomb charge moving through a unit area)
Q = charge density, (Charge in a unit volume)
v = velocity of charge in an electric field.
Note that density may mean area or volumetric density,
depending on the context.
Mobility
At low fields, carrier drift velocity v (cm/s) is proportional
to electric field E (V/cm). The constant of proportionality
is the mobility, :
v
n
= -
n
E and v
p
=
p
E , where
v
n
and v
p
= electron and hole velocity (cm/s),

n
and
p
= electron and hole mobility (cm
2
/Vs)
Hole mobility is less than electron since hole current is
the result of multiple covalent bond disruptions, while
electrons can move freely about the crystal.
Velocity Saturation
At high fields, carrier
velocity saturates
and places upper
limits on the speed
of solid-state devices.
As the applied electric field increases from that point, the carrier velocity no
longer increases because the carriers lose energy by emitting phonons as
soon as the carrier energy is large enough to do so
Intrinsic Silicon Resistivity
Given drift current and mobility, we can calculate resistivity:
j
n
drift
= Q
n
v
n
= (-qn)(-
n
E) = + qn
n
E A/cm
2
j
p
drift
= Q
p
v
p
= ( qp)(
p
E) = + qp
p
E A/cm
2
j
T
drift =
j
n
+ j
p
= q(n
n
+ p
p
)E = oE
Defines electrical conductivity:
o = q(n
n
+ p
p
) (Ocm)
-1
Resistivity is the reciprocal of conductivity:
= 1/o (Ocm)
Resistivity of Intrinsic Silicon
o = (1.60 x 10
-10
)[(10
10
)(1350) + (10
10
)(500)] (C)(cm
-3
)(cm
2
/Vs)
o = 2.96 x 10
-6
(Ocm)
-1
= 1/o = 3.38 x 10
5
Ocm
Intrinsic silicon is near the low end of the insulator
resistivity range - a poor insulator
Semiconductor Doping
Doping is the process of adding very small well
controlled amounts of impurities into a
semiconductor.
Doping enables the control of the resistivity and
other properties over a wide range of values.
For silicon, impurities are from columns III and V
of the periodic table.
Useful Dopants in Silicon
Donors - Column V
Phosphorus P
Arsenic As
Antimony Sb
Acceptors - Column III
Boron B
(Aluminum Al)
Fit in Lattice Relatively
Well
Donor Impurities in Silicon
Phosphorous (or other column
V element) atom replaces
silicon atom in crystal lattice.
Since phosphorous has five
outer shell electrons, there is
now an extra electron in the
structure.
Material is still charge neutral,
but very little energy is
required to free the electron for
conduction since it is not
participating in a bond.
Acceptor Impurities in Silicon
Boron (column III element) has
been added to silicon.
There is now an incomplete
bond pair, creating a vacancy
for an electron.
Little energy is required to
move a nearby electron into
the vacancy.
As the hole propagates,
charge is moved across the
silicon.
Acceptor Impurities in Silicon
Hole is propagating through the silicon.
Carrier Concentrations
If n > p, the material is n-type.
If p > n, the material is p-type.
The carrier with the largest concentration is the majority
carrier, the smaller is the minority carrier.
N
D
= donor impurity concentration atoms/cm
3
N
A
= acceptor impurity concentration atoms/cm
3
Charge neutrality requires q(N
D
+ p - N
A
- n) = 0
It can also be shown that pn = n
i
2
, even for doped
semiconductors in thermal equilibrium.
n-Type Material
Substituting p = n
i
2
/n into q(N
D
+ p - N
A
- n) = 0
yields n
2
- (N
D
- N
A
)n - n
i
2
= 0.
Solving for n
For (N
D
- N
A
) >> 2n
i
, n ~ (N
D
- N
A
)
P-type Materials:
For (N
A
- N
D
) >> 2n
i
, p ~ (N
A
- N
D
).
n
n
p and
n ) N N ( ) N N (
n
i
i A D A D
2
2 2
2
4
=
+
=
Practical Doping Levels
Majority carrier concentrations are established at
manufacturing time and are independent of temperature
(over practical temp. ranges).
However, minority carrier concentrations are proportional
to n
i
2
, a highly temperature dependent term.
For practical doping levels, n ~ (N
D
- N
A
) for n-type and
p ~ (N
A
- N
D
) for p-type material.
Typical doping ranges are 10
14
/cm
3
to 10
21
/cm
3
.
Mobility and Resistivity
Mobility is a function of
Doping in Semiconductors
Impurities Disrupt the
Periodic Lattice Structure
Diffusion Current
Second Mechanism to Produce Current in
Semiconductors
In practical semiconductors, it is quite useful to create
carrier concentration gradients by varying the dopant
concentration and/or the dopant type across a region of
semiconductor.
This gives rise to a diffusion current resulting from the
natural tendency of carriers to move from high
concentration regions to low concentration regions.
Diffusion current is analogous to a gas moving across a
room to evenly distribute itself across the volume.
Diffusion Current (cont.)
Carriers move toward regions of
lower concentration, so diffusion
current densities are proportional
to the negative of the carrier
gradient.
Diffusion currents in the
presence of a
concentration gradient.
2
n n
diff
n
2
p p
diff
p
A/cm
x
n
qD
x
p
D ) q ( j
A/cm
x
p
qD
x
p
D ) q ( j
c
c
c
c
c
c
c
c
+ =
|
|
.
|
\
|
=
=
|
|
.
|
\
|
+ =
Diffusion current density equations
Total Current in Semiconductor
Total current is the sum of drift and diffusion current:

x
p
qD pE q j

x
n
qD nE q j
p p
T
p
n n
T
n
c
c
c
c
=
+ =
Semiconductor Devices
MOSFET
CMOS
http://jas.eng.buffalo.edu
/education/mos/mosfet/m
osfet.html
Bipolar Junction Transistor
(BJT)
Emitter
Base
Collector
Isolation Isolation
PN Diodes
n-type
silicon
p-type
silicon
anode cathode
pn Junction
p-type Si
Al Al
n-type Si
http://jas.eng.buffalo.ed
u/education/pn/biasedP
N/index.html
CMOS Inverter
CMOS Fab Example: Inverter
Typically use p-type substrate for nMOS
transistor
Requires n-well for body of pMOS transistors
Several alternatives: SOI, twin-tub, etc.
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
SiO
2
n+ diffusion
p+ diffusion
polysilicon
metal1
nMOS transistor pMOS transistor
Well and Substrate Taps
Substrate must be tied to GND and n-well to V
DD
Metal to lightly-doped semiconductor forms poor connection called
Shottky Diode
Use heavily doped well and substrate contacts / taps
n+
p substrate
p+
n well
A
Y
GND
V
DD
n+ p+
substrate tap well tap
n+ p+
<43> Chapter 1: IC Overview Fabrication and Layout
Inverter Mask Set
Transistors and wires are defined by masks
Cross-section taken along dashed line
GND V
DD
Y
A
substrate tap
well tap
nMOS transistor pMOS transistor
Detailed Mask Views
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Metal
Polysilicon
Contact
n+ Diffusion
p+ Diffusion
n well
Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO
2
(oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO
2
p substrate
Oxidation
Grow SiO
2
on top of Si wafer
900 1200 C with H
2
O or O
2
in oxidation furnace
p substrate
SiO
2
Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light
p substrate
SiO
2
Photoresist
Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist
p substrate
SiO
2
Photoresist
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty
stuff!!!
Only attacks oxide where resist has been
exposed
p substrate
SiO
2
Photoresist
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next
step
p substrate
SiO
2
n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO
2
, only enter exposed Si
n well
SiO
2
Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of
steps
p substrate
n well
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of
silicon layer
Place wafer in furnace with Silane gas (SiH
4
)
Forms many small crystals called polysilicon
Heavily doped to be good conductor
Thin gate oxide
Polysilicon
p substrate
n well
Polysilicon Patterning
Use same lithography process to pattern
polysilicon
Polysilicon
p substrate
Thin gate oxide
Polysilicon
n well
Self-Aligned Process
Use oxide and masking to expose where
n+ dopants should be diffused or
implanted
N-diffusion forms nMOS source, drain, and
n-well contact
p substrate
n well
N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates because it
doesnt melt during later processing
p substrate
n well
n+ Diffusion
N-diffusion
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion
n well
p substrate
n+ n+ n+
N-diffusion
Strip off oxide to complete patterning step
n well
p substrate
n+ n+ n+
P-Diffusion
Similar set of steps form p+ diffusion
regions for pMOS source and drain and
substrate contact
p+ Diffusion
p substrate
n well
n+ n+ n+ p+ p+ p+
Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed
p substrate
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Contact
Metallization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires
p substrate
Metal
Thick field oxide
n well
n+ n+ n+ p+ p+ p+
Metal
NMOS Transistor
N-Channel Metal-Oxide
Semiconductor Transistor
n- and p-type semiconductor
regions
Thick and thin oxides
Etching Openings
Polysilicon gate
Metal (Al) Interconnections
Conducting
Channel
Region
Basic NMOS Process
Oxidation
Photolithography
Implantation
Diffusion
Etching
Film Deposition
CMOS Technology
Complementary Metal-Oxide
Semiconductor Technology
Dominant Technology in
Integrated Circuits Today!
Requires both NMOS and
PMOS Transistors
Oxidation
Photolithography
Implantation
Diffusion
Etching
Film Deposition
Bipolar Transistor
Bipolar Junction Transistor
(BJT)
Standard Buried Collector
Process (SBC)
n- and p-type semiconductor
regions
Thick and thin oxides
Etching Openings
Metal (Al) Interconnections
Active
Transistor
Region
SBC Process
Oxidation
Photolithography
Implantation
Diffusion
Etching
Film Deposition
Homework
Text book questions
Extra Reading Jack Kilby Nobel Lecture
and answer questions
1) Describe the monolithic semiconductor approach to make
integrated circuits.
2) What are the major criticism and objections to the IC idea of
Kilby?
3) What have you learned from Kilbys story
UTD | EE 4330: IC Technology -Dr. W. Hu |

IC Tech

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

IC Tech

Uploaded by

Copyright:

Available Formats

<1> Chapter 1: IC Overview

You might also like