CAN Signal Integrity Design

CAN Bus Signal Integrity Design

Mike Donnelly
Mentor Graphics

w w w. m e n t o r. c o m / s y s t e m v i s i o n

INTRODUCTION The IEEE Standard 1076.1 (VHDL-AMS) provides hardware modeling capabilities that are well suited for Controller Area Network (CAN) signal integrity analysis. This includes modeling the analog, digital and mixed-signal aspects of the transceivers, as well as the behavior of twisted-pair transmission lines, connectors and other components of the CAN Physical Layer. SystemVision, a virtual prototyping and design analysis environment from Mentor Graphics, supports both VHDL-AMS as well as traditional Spice modeling methods. SystemVision provides comprehensive graphical design capture and simulation control, as well as waveform display, measurement and post-processing analysis capabilities. This paper presents various modeling approaches applicable to the key hardware components of a CAN bus. It also provides examples of simulation-based techniques for CAN signal integrity design, including: Analyzing static and dynamic features of transceivers, lines and other components Examining termination strategies Characterizing data delay vs. intermediate-node stub-length Assessing Electrostatic Discharge (ESD) protection capability of Transient Voltage Suppression (TVS) components CAN BUS MODEL A schematic model representing a typical 4-node CAN bus is shown in Figure 1. The network interconnect is modeled using 6 transmission lines, 4 that compose the main bus path between the two terminating nodes (node-1 on the far left and node-4 on the far right), and two stub lines to the intermediate nodes 2 and 3.

Termination

Stimulus

Termination Connector

Node-4

Node-1 Transmission Lines Node-2 Node-3

Figure 1 CAN bus model and simulation test-bench

The base transmission line model, written in VHDLAMS, represents a two-conductor, symmetric lossless line. This model is suitable to represent twisted-pair cables used at the moderate data rates and lengths specified for CAN-C. The user can independently specify the odd and even mode impedances, as well as the signal propagation delay. Propagation delay is proportional to line's physical length. The interconnect model also includes the effects of a connector in the main bus path. The VHDL-AMS connector model has electrical characteristics that are computed from user-specified physical parameters of pin length, radius and spacing. The internal calculations, to convert these geometric values to the key electrical characteristics of self- and mutual-inductance, are based on equations provided in [1]. The CAN bus model incorporates three different transceiver model formats, to show the range of modeling methods available in SystemVision. Transceiver 1 (node-1) is a "structural" VHDL-AMS model. The word structural refers to a modeling approach in which primitive elements are assembled or connected in a circuit, to describe the behavior of the higher level component. The sub-schematic representing Transceiver 1 is shown in Figure 2. The primitives include digital elements (inverter, "AND" gate), analog elements (capacitors), and "mixed-signal" elements (digitally controlled switch, differential A/D). All of

CAN Bus Signal Integrity Design

Positive (Supply) Ref.

Switch (H) Differential 1-bit A/D with Hysteresis Tx Enable CAN-H

Rx Data

Tx Data (0 dominant) CAN-L

Switch (L) Parasitic Capacitance Negative (Ground) Ref.

The transceiver model for node-4 is a SPICE circuit. The BJT's, resistors, capacitors and voltage sources are all SPICE primitive elements. This circuit could also have been provided as a SPICE sub-circuit file, perhaps from a vendor that routinely supplies SPICE models of components. SystemVision provides support for SPICE primitives and sub-circuits, along with advanced analog, digital and mixed-signal models in the IEEE Standard VHDL-AMS format. The last element of the CAN bus test-bench is the stimulus control block, which generates a pseudo-random bit stream (PRBS) and the transceiver-enable control sequence. This block allows the user to control which of the 4 transceivers is transmitting at any time, and the number of bits sent during its active period. The user can also specify the number of recessive bits between active node transitions. SIMULATION-BASED PERFORMANCE ANALYSIS BASIC OPERATION The CAN bus model and test-bench were simulated and some of the key signals are shown in Figure 3. During the 50 s simulation run, each of the 4 nodes sequentially transmits for 10 s (= 10 bits, at 1 Mbps rate), with a 2 s recessive period in between (i.e. paused, no transmission).
Enable

Figure 2: Structural transceiver model

the components can be tuned by the user to represent transmit and receive characteristics of a particular transceiver. This includes the switching speed, the drive source impedance and the receiver logic hysteresis threshold voltages. The structural transceiver model also includes terminals to connect to an external supply rail and ground. These terminals can be connected to power and ground circuits that include non-ideal ground offset voltage, parasitic supply rail inductance and noise disturbance effects. These characteristics may be important factors for the overall CAN bus signal integrity. The transceivers at node-2 and node-3 are modeled with a "behavioral" VHDL-AMS description. They provide nearly identical electrical behavior and userspecified parameters as the structural version, but internally all of the voltage, current and logical signal relationships are described directly using the VHDLAMS language. One notable feature is that this model provides user settable reference voltage levels as constants, rather then as electrical connections to external circuits. This is more convenient if power and ground disturbance analysis is not needed.

Rx Data

Diff Rx 1

Diff Rx 2

Diff Rx 3

Diff Rx 4

Figure 3: Digital and analog CAN bus signals

CAN Bus Signal Integrity Design

The digital enable signals for each of the 4 nodes are shown at the top of the display window. Below these is the digital PRBS data source signal, which is distributed to all of the nodes and is used as the common transmit data stream. The next 4 digital waveforms are the 4 nodes' received data signals. Note the edge disturbance or "widening" on some edge transitions, but generally all of the nodes receive a copy of the PRBS data that is being transmitted, regardless of which node is actively transmitting. The four analog waveforms of Figure 3 are the received differential voltages (= CAN_H - CAN_L) at nodes 1, 2, 3 and 4. Note the differences in the drive amplitude, depending on which node is transmitting. Also note that logic '0' is dominant, and produces a positive differential voltage value. There is considerable overshoot and ringing observed in the analog waveforms, due to reflections from the impedance discontinuities along the bus. Note that better signal quality is observed at the other nodes when node-4 is actively transmitting (from 36 s to 46 s). This is the result of the much slower switching speed of transceiver 4. For the particular SPICE transistor models chosen for use in transceiver 4, the effective rising and falling edge times are 15 ns and 75 ns, respectively. For the other transceivers, these transition times are approximately 0.5 ns. In the VHDL-AMS transceiver models, these edge rates can easily be modified by the user, to explore the effect of switching speed on signal quality. Figure 4 is a "zoomed-in" view of select signals from Figure 3. The digital signals include, from the top: the transmit enable logic '1' to node-3; the PRBS transmitted data signal; and the received data at node-2. The analog signal is the differential voltage at node-2.

Diff Rx 2

Figure 4: Zoomed view of node-2 signals (with node-3 transmitting)

This zoom view shows a single ('1') bit of data on the bus, including the '0' to '1' transition followed by the '1' to '0' transition. The data was transmitted by node3, but this highlights the view of the signal arriving at node-2. Note the transmission delay as well as the logical "glitches" on the leading edge of the received digital data signal. These glitches are the result of the differential voltage ringing above and below the hysteresis logic thresholds of the receiver. The amount of ringing depends on the entire configuration of the CAN bus, including: the overall bus and stub lengths; the impedance of the terminations, transmission lines and transceivers; and the transmitter edge rates, as discussed previously. EMI CHARACTERIZATION Another important aspect of CAN bus design is EMI assessment. A circuit simulation model that includes the drive characteristics of the transceivers as well as the transmission lines and other component effects (e.g. connectors, filters, etc.), provides valuable information on the transmission lines' current amplitude and rate of change. This type of characterization data is needed to assess radiated emissions levels.

CAN Bus Signal Integrity Design

For example, Figure 5 shows the node-4 CAN-H and CAN-L voltages during a dominant bit transmission. Note that due to circuit asymmetry, the upper transistor turns off faster than the lower transistor, at the transition from the dominant to the recessive state. This results in a transient offset in the "common" voltage level (i.e. a change in the "average" voltage seen on the CAN-H and CAN-L lines). This common voltage appears as a large, negative, "even-mode" current pulse on the transmission line TL3a. TL3a is a long line, to the immediate right of the connector in Figure 1. This even-mode wave is traveling from right to left along the CAN bus. Even-mode currents present a high risk for radiated emissions, as they are not mitigated by the twisted-pair construction of the line.

Common-mode Choke

Figure 6: Addition of common-mode choke for EMI reduction

CAN_H

The benefit of the choke is clearly illustrated in Figure 7, as the even-mode transmission line current pulse is significantly reduced after a 10uH choke is added. Other choke inductance values may provide even further improvements, but the effect on differential signal quality would also need to be considered. This type of design trade-off analysis should be performed as part of an overall EMI assessment for any proposed CAN bus configuration.

CAN_L

Choked

Even-mode Current

Un-Choked

Figure 5: Node-4 transmitter drive (CAN-H and CAN-L) and even-mode transmission line current

A component that can help reduce even-mode currents is known as a "common-mode choke". This is a transformer placed in series with the bus, as shown in Figure 6. The current in each wire of the CAN bus goes through one of the windings. The mutual inductive coupling between the windings attenuates common currents, while allowing differential currents to pass [2].

Figure 7: Effect of the common-mode choke on transmission line even-mode current

PARAMETRIC ANALYSIS - STUB LENGTH The SystemVision design environment provides automated parametric analysis capabilities, such as Sensitivity, Monte Carlo (Statistical), and Parameter Sweeping. This automation includes running the multiple simulations required to generate the often large "virtual" experimental data set. It also includes per-

CAN Bus Signal Integrity Design

forming the post-processing waveform measurements that are necessary to extract the important system parameter dependences. An example will illustrate how parametric design analysis helps extract the most value from a good simulation model. The CAN bus design question that needs to be answered: How long can intermediate node stub lines be? There are CAN design guidelines that specify the maximum length, but certain vehicle configurations could benefit from some flexibility in these rules. With the power of parametric analysis, design engineers can assess the impact of "bending the rules", to see if a more cost effective configuration is technically acceptable. Figure 8 shows the raw simulation results for a parameter sweep of the propagation delay of the stub transmission line, between the main bus and node-2 (refer to Figure 1). Three values of delay were used: 5 ns, 10 ns and 15 ns. These correspond approximately to 1, 2 and 3 meters length, respectively; at the typical wave propagation value 5 ns per meter.

waveforms at the receiving node-4, at the opposite end of the bus, are also shown. The marker indicates a delay of 50.543 ns between the first members of each of these waveform sets, corresponding to the 5 ns value of propagation delay on the stub line. For the other two members, the voltage plateaus well above the logic threshold level for a substantial time, so switching is significantly delayed. Note that the line length being swept is not in the direct path between the transmitting and receiving nodes, but still has a significant effect on the delay of the receiver's voltage threshold crossing. The correlation between the node-2 stub propagation delay, and the switching delay from node-1 to node-4, is shown in Figure 9. This plot shows that as the stub delay is increased from 5 ns to 15 ns (a difference of 10 ns), the switching delay is increased from 50.5 ns to 71.0 ns (approximately 20 ns, or by a factor of twoto-one)!

Data Delay vs. Stub Length (propagation delay)

Diff Tx 1

Diff Rx 4

Figure 9: Parametric switching delay, from node-1 to node-4, vs. node-2 stub propagation delay Figure 8: Node-1 transmitting and node-4 receiving voltages, sweeping stub line length at node-2

Three overlaid differential voltage waveforms at transmitting node-1, one for each of three stub-line delay values, are shown. Three overlaid differential voltage

This is because the energy required for the data logic transition, which is traveling from node-1 to node-4, splits at the junction of node-2. It must travel the length of the stub line toward the passive node-2, and then reflect off of its high impedance and traverse the

CAN Bus Signal Integrity Design

stub length (again), to return to the main bus path. When the reflected wave finally arrives at node-4, the switching process is completed. But it is of course delayed by twice the propagation delay of the stub. It is interesting to note that in some common printed circuit board interconnect applications (e.g. PCI bus), the specific design intent is that the switching process completes only after the reflected energy arrives at the receiver. This is known as reflected-wave switching. DESIGN FOR ESD PROTECTION One of the values of virtual prototyping is the ability to verify the design's operation in extreme environmental conditions. The following example illustrates this capability for analyzing the effects of ElectroStatic Discharge (ESD) and the performance of circuit protection devices. The ESD test-bench shown in Figure 10 has only two nodes. In between the two transmission lines that connect these nodes, the standard Human Body Model (HBM) circuit is placed [2]. It consists of a 100pF capacitor, with an initial voltage of 16 kV, and a 1500 Ohm resistor. The energy stored on the capacitor is injected onto either the CAN-H or the CAN-L bus wire (or both) through the ideal switches, to represent an ESD event.
Human Body ESD Model

In addition to the CAN termination circuits at the ends of the bus, there are also zener diode pairs arranged back-to-back, to act as Transient Voltage Suppressors (TVS). These protection devices have a zener voltage of 33V, so they do not conduct during normal operation of the bus. They have no functional role in signaling. Rather, they operate during high voltage transients, to both protect the transceivers and to minimize data-errors following the ESD event. The test bench allows the design engineer to easily control the configuration and operational conditions that define the ESD modes and effects. Either transceiver can be enabled, and can be transmitting either a '0' or a '1' at the moment the selected ESD switch is closed. Figure 11 shows the results of running two ESD events under different conditions.

CAN_L

CAN_H

CAN_H

CAN_L

Figure 11: Simulation results from two ESD test scenarios

Node-2

Node-1

TVS devices

TVS devices

Figure 10: Test-bench for ESD/TVS design verification

At the top of the Figure 11, the first digital waveform is a constant logic '0' (dominant) signal being transmitted from node-1. The second digital waveform is the logic signal received at node-2. This logic state changes to an incorrect logic '1' value immediately following the ESD event that occurs at time 2 s. This is followed by a brief burst of logic "glitches" before the receiver logic settles down to the correct logic '0' value

CAN Bus Signal Integrity Design

again, 0.5 s after the ESD event. The corresponding analog waveforms are the CAN-H voltage and the noisy CAN-L voltage, both observed at node-2. The noise is the result of ESD energy injected into the CAN-L conductor. The TVS devices are seen to be effectively limiting the noise voltage to just over the zener level; the transient voltage would be much higher without them. In the lower half of Figure 11, the same waveforms are shown, but this time the circuit operating mode is changed. Node-1 is transmitting a logic '1' (recessive) signal, and the ESD energy is now injected into the CAN-H conductor. Therefore, the noise voltage transient is observed on the CAN-H waveform. The peak voltage amplitude is the same as the previous configuration, but the duration of the ESD noise transient is much longer. The total time of the incorrect logic '0' state received at node-2 is just over 1 s. This would certainly result in a data bit-error, as the duration exceeds the unit interval (UI = 1 s, at 1 Mbps data rate). The reason for the difference in the error duration, for these two bus conditions, is that when the transceiver is in the dominant state, the drive transistors are active and can drive the bus voltage to the desired level. But in the recessive state, the bus termination resistors alone must absorb the ESD energy remaining on the bus, after the voltage drops below the TVS clamping level.

SUMMARY This paper has demonstrated a wide range of modeling, simulation and analysis capabilities that are applicable to CAN Bus Physical Layer design. The IEEE Standard 1076.1 (VHDL-AMS) hardware description language provides a solid foundation for building models at the right level of detail for design verification, parametric trade-off analysis, and EMI/ESD assessment. This includes modeling of the analog, digital and mixed-signal aspects of components. Legacy SPICE models can also be incorporated, using the SystemVision virtual prototyping environment. REFERENCES [1] Hall, S.H., Hall, G.W., McCall, J.A., "High-Speed Digital System Design", John Wiley and Sons, Inc., 2000 [2] Lepkowski, J., Wolfe, B., Lepkowski, W., "EMI/ESD Solutions for the CAN Network", ON Semiconductor and University of Arizona, IEEE 2005

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