ComprehensiveVerilogCourse LabManualv2.0 Conductedby: Preparedby: SohaibAyyazQazi/WaqarNabi Dr.

WaqarNabi/NidaRasheed

Session1: ThislabsessionisdesignedtofamiliarizeyouwiththeuseoftheXilinxISE10.1.Afterthislab youshouldbeabletodesignaverilogmodule,synthesizeitandsimulateinXilinxISE10.1. Exercise1.1:GettingStarted In this exercise you are going to start using Xilinx ISE 10.1. The top level modules and the testbenchforexercise1.1areprovidedsothatyoucaneasilyexploretheXilinxtool. counter.visatoplevelmodule,itisa4bitcounterthatcountsfrom0to15andgoesbackto zero.testbench_counter.visatestbenchtotestthecounter. Exercise1.2:DesignHalfAdder Completethefollowingsteps 1. Complete/writethehalfaddermodulethatwasdescribedinthelecture.Thediagram ofhalfadderisshowninfigure1.1.

Figure1.1:HalfAdder

2. Writeatestbenchforthehalfadder. 3. Checkandverifytheresultsforthecounter.

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Session2: Inthissessionyouwillcovermoduleandports,primitivesandgatelevelmodeling,testbench, datatypesandhierarchy. Exercise2.1:Multiplexer4to1 1. Completethe4to1multiplexermodulethatwasdescribedinthelecture.Thediagram ofmultiplexerisshowninfigure2.1.

s1 s0

data_1 32 data_2 32 data_3 32 data_4 32

sum

Mux32_4_1
32 c_out

c_out

Figure2.1:Multiplexer4to1

2. Writethetestbenchforthemultiplexer. 3. Checkandverifytheresultsforthemultiplexer. Exercise2.2:4bitRippleCarryAdder Designa4bitripplecarryadderaccordingtotheconditionsspecifiedinfigure2.2.

Figure2.2:4bitRippleCarryAdder
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Exercise2.3:2bitbinarycompa arator comparator compares t two bit bina words, A and B, and asserts ou ary A utputs indic cating A 2bit c whetherthedecimalequivalentofwordAis slessthan,g greaterthan n,orequalto othatofwo ordB. ethefollowingsteps Complete

gure2.3:2b bitBinaryCo omparator Fig 1. W Writethecod defor2bit comparator rusinggate levelmodeling,blockd diagramissh hown in nfigure2.3. 2. W Writethetestbenchfort thetoplevel lmoduleand dverifytheresults.

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Session3: Inthissessionyouwilllearnsimulationcontrol,behavioralmodelingusingcontinuous assignment,andproceduralblocksforcombinationallogic. Exercise3.1:Behavioralmodelsof4to1Multiplexer As you have completed the lab exercise 2.1 now you have to design same 4to1 multiplexer usingthebehavioralmodeling.Completethefollowingsteps 1. Design4to1multiplexerusingcontinuousassignmentstatements. 2. Design4to1multiplexerusingalways@module. 3. Testandverifytheresultsofbothmodulesusingthetestbenchofexercise2.1. Exercise3.2:FullSubtractorusingBooleanEquations A full subtractor has three 1bit inputs x, y, and z (previous borrow) and two 1bit outputs D (difference)andB(borrow).ThelogicequationsforDandBareasfollows:

D=x'.y'.z+x'.y.z'+x.y'.z'+x.y.z B=x'.y+x'.z+y.z

1. WritethefullVerilogdescriptionofthefullsubtractormodule,includingI/Oports. 2. Instantiate the full subtractor inside a stimulus and test all possible inputs and verify themfromthetable3.1. Table3.1:Truthtableforfullsubtractor

x
0 0 0 0 1 1 1 1

y
0 0 1 1 0 0 1 1

z
0 1 0 1 0 1 0 1

B
0 1 1 1 0 0 0 1

D
0 1 1 0 1 0 0 1

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Exercise3.3:4bitAdderusingdataflowoperators. Inthislabyouwilldesignthedataflowdescriptionofthe4bitadder. 1. Writetheverilogcodefor4bitfulladderusingdataflowoperators. 2. Writethetestbenchfortheverilogmodule. 3. Verifytheresults. Exercise3.4:1to4demultiplexer. Youhavedesignedthemultiplexerinexercise2.1.NowyouhavetoDeMultiplexthedata.Ittakes

asingleinputandtwoselectioninputsandsendstheinputdatatoasinglelinedependingofthevalues oftheselectioninputs. 1. WriteverilogcodefortheDemultiplexerusingassignstatements. 2. WriteverilogcodefortheDemultiplexerusingalways.

Figure3.1:1to4DeMultiplexer Exercise3.5:testbenchfor1to4demultiplexer Inthisexerciseyouhavetowriteatestbenchfortheverilogcodewritteninexercise3.4.Verify theresultsusingthetestbenchyouhavewritten.

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Session4: Afterthissessionyoushouldbeabletodotimebasedandeventbasedcontrol,synchronous sequentiallogic,blockingandnonblockingassignments,tasksandfunctions. Exercise4.1:clockgenerationusingalways All behavioral statements inside an always statement constitute an always block. The always statementstartsattime0andexecutesthestatementsinthealwaysblockcontinuouslyina looping fashion. This statement is used to model a block of activity that is repeated continuouslyinadigitalcircuit. Designaclockgeneratorthatdoesnthaveanyinputandasingleoutputi.e.clock. Exercise4.2:+veandveclockedflipflops There is only one way to model either a positive edgetriggered flipflop or negative edge triggered flipflop. In this lab you have to model two flipflops one with positive edgetrigger andtheotherwithnegativeedgetrigger. 1. Writethecodeforthediagramshowninfigure4.1.
A0 D0 8 Q Y1

Clock Q

A1 D1 8 Q Y2

Figure4.1:PositiveandNegativeedgetriggeredflipflops 2. Writetestbenchandalsoverifytheresults.

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Exercise4.3:Synchronousreset,ASynchronousresetandenable Write a code to show the diagram as shown in figure 4.2. Also check the behavior of Synchronousreset,Asynchronousresetandenablesignals.Followthestepsgivenbelow 1. WriteverilogcodeforSynchronousreset. 2. WriteverilogcodeforAsynchronousreset. 3. Addenablesignalinthemodule.

Figure4.2:TimingdiagramofSynchronousandAsynchronousreset 4. Addastimulustoshowthediagramssimilar(inbehavior)tothefigure4.2. Exercise4.4:Behavioral4bitcounter Bycompletingthestepsgivenbelowdesigna4bitcounterusingbehavioralstatements. 1. Writeverilogcodeforthebehavioral4bitcounterwithfollowingportconnections Asingle4bitcounteroutputsignal. Clockandaresetasinputsignals. 2. Writeatestbenchtoverifytheoutputofthecounter.

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Exercise4.5:BehaviorofBlockingandnonBlockingStatements After this lab exercise you should be able to understand the behavior of blocking and non blockingstatements. Writeaverilogcodeforthediagramgivenbelowandcheckthebehaviorofblockingandnon blockingstatementsusingstimulus.
1
Data_in
D Q

1
internal
D D Q

Data_out Clock
Q Q

Figure4.3:Blockingandnonblockingbehavior You have to notice the behavior of both environments blocking and nonblocking. Notice the changeofdataatoutputaccordingtotheinputchanged.

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 5: Session5 Inthislab byouwillde esignusingc conditionals statements,loops,mode elingmuxes, , encoders s/decoders. Exercise5.1:Priority yEncoder 1. W Writeacodeforpriority encodershowninfigur re5.1.Youc canuseifstatementsor ralso th hecasexstat tements. Note that the con nditional (if) statements have an im ) mpliedprior of execu rity ution, andthatthe casexstatementscomb binedwithx xinthecase eitemsimpl liedpriority also. atements ignores x and z in bits of the case it d f tem and the are treate as ey ed The casex sta dontcares.

Figure5.1 1:PriorityEn ncoder Writeastimu ulustocheck kyourresult ts. 2. W Exercise5.2:BCDtosevensegm mentdisplay The sevensegment lightemitt t ting diode (LED) display is a ve useful circuit in m ery many applicatio onsusingpr rototypingboards.

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Yourmoduleshouldtake4bitBCDinputandgivea7bitoutputtodisplayadigitontheseven segment.AssignyouroutputsforthesevensegmentLEDdisplaywhichisshowninfigure5.2.

Figure5.2:SevenSegmentLEDDisplay

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Session6 6: Inthisse essionofthelabyouwill ldesignafin nitestatema achine.Youwillmodelc countersand dalso shiftregisters. Exercise6.1:Univers salShiftReg gister rsalshiftreg gisterwithfo ollowingfeat tures Designa4bitUniver 1. 2. 3. 4. 5. 6. 7. Sy ynchronousreset. Parallelinput ts. uts. Paralleloutpu de. BidirectionalserialinputfromLSBsid BidirectionalserialinputfromMSBside. utfromLSBs side. Bidirectionalserialoutpu utfromMSBside. Bidirectionalserialoutpu

UniversalSh hiftRegister r Figure6.3:U

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 Statemachin ne(CarSpee edControl) Exercise6.2:FiniteS Designastatemachi ineofcarsp peedcontrollercorrespo ondingtothe estatemach hineinfigure e6.1. Alsowrit teatestbenc chforthisFS SM.

Figure6.1 1:Statediag gramforcar rspeedcont troller Exercise6.3:3bitup p/downcou unter Designa3bitcounte erasshowninfigure6.2 2.Thecountershouldincludefollow wingfeatures s 1. It tshouldcountinbothdi irectionsi.e. .up/down. 2. It tshouldload dsomedatatostartcou untingfromt thatvalue.

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Data a_in

Fi igure6.2:3 bitup/downcounter 3. Enablepinsh houldbeadd dedtoturnthecountero on/off. Asignalshouldbeaddedtoresetthe ecounter. 4. A

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Session7: Thisisaverysmallsessiontoallowyoutocompleteearlierexercisesandleavemoretimefor thenextsession. Exercise7.1:ASMDcounter Seeexample13whichisanASMDcounter.Convertittoacountdowncounter.Notehowyou onlyneedtochangethefuncitoninthedatapathandtherestofthecircuitremainsthesame.

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Session8: ThissessionisovertheRISCcontrollerfromCilettisbook,thatwasdiscussedinclass. Exercise8.1:TheRISCprocessor Firstofall,opentheRISCexample,runityourselfandseethatyouhaveatleastareasonably goodideaofhowitworks.(Atthispointthereisntenoughtimetolookateachandeveryline ofcode,butthatwouldbeagoodexerciseforlater) Exercise8.2:CarryflagintheRISCprocessor Now modify the design so that the Processors ALU creates a carry flag, asserted when the resultofanadditionoperationhasacarryout. YouwillneedtoaddaLoadsignalthatiscreatedinControl_Unit,andisinputtotheProcessor. Youwillneedtocreatacarrysignal,thatiscreatedinALU,loadedinaRegisterinProcessor, andfedtotheControlUnit. Note:thatalladditionsinthecodeforthiscarryflagwilllookverysimilartothewaytheZero flagisimplemented,soyoucanusethatasareference. Changethetestbenchtoensurethatduringtheprogramexecution,thecarryflagistested.

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Session9: Nonewexercisesinthissession;pleaseensureyoucompleteallpreviousexercises. Afterthat,open,runandsynthesizethetwodifferentversionsofthehalftoneimageconverter. Youshouldatleastfullyunderstandthefirst(combinatorial)implementation.Thendepending ontime,seewhatyoucanmakeoftheconcurrentimplementation.

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Session10: Exercise10.1:TheRMMguidelines Openadesignfilethatyouhaveseeninthisworkshop.IrecommendtheControl_Unitofthe RISCprocessorbutyoucanchosesomethingsmallerifyouplease. Nowlookatthechapter5ofReuseMethodologyManual.Updatethisdesigntoconformto therulesandguidelinesofRMM.

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