Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-1

LECTURE 420 COMPENSATION OF OP AMPS-I

(READING: Text-Sec. 9.2, 9.3, 9.4) INTRODUCTION The objective of this presentation is to present the principles of compensating two-stage op amps. Outline Compensation of Op Amps General principles Miller, Nulling Miller Self-compensation Feedforward Summary

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-2

GENERAL PRINCIPLES OF OP AMP COMPENSATION Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp. Types of Compensation 1. Miller - Use of a capacitor feeding back around a high-gain, inverting stage. Miller capacitor only Miller capacitor with an unity-gain buffer to block the forward path through the compensation capacitor. Can eliminate the RHP zero. Miller with a nulling resistor. Similar to Miller but with an added series resistance to gain control over the RHP zero. 2. Feedforward - Bypassing a positive gain amplifier resulting in phase lead. Gain can be less than unity. 3. Self compensating - Load capacitor compensates the op amp.

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-3

Single-Loop, Negative Feedback Systems F(s) Block diagram: A(s) = differential-mode voltage gain of the op amp Vin(s) A(s) + F(s) = feedback transfer function from the output of op amp back to the input. Definitions: Open-loop gain = L(s) = -A(s)F(s) Vout(s) A(s) Closed-loop gain = Vin(s) = 1+A(s)F(s) Stability Requirements: The requirements for stability for a single-loop, negative feedback system is, | A(j0)F(j0)| = | L(j0)| < 1 where 0 is defined as Arg[A(j0)F(j0)] = Arg[L(j0)] = 0 Another convenient way to express this requirement is Arg[A(j0dB)F(j0dB)] = Arg[L(j0dB)] > 0 where 0dB is defined as | A(j0dB)F(j0dB)| = | L(j0dB)| = 1
ECE 4430 - Analog Integrated Circuits and Systems

Vout(s)
Fig. 420-01

P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-4

Illustration of the Stability Requirement using Bode Plots

|A(j)F(j)|

-20dB/decade 0dB -40dB/decade

Arg[-A(j)F(j)]

180 135 90 45 0 M 0dB Frequency (rads/sec.)

Fig. Fig. 420-02

A measure of stability is given by the phase when |A(j)F(j)| = 1. This phase is called phase margin. Phase margin = M = Arg[-A(j0dB)F(j0dB)] = Arg[L(j0dB)]
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-5

Why Do We Want Good Stability? Consider the step response of second-order system which closely models the closed-loop gain of the op amp.
1.4 1.2 1.0 vout(t) 0.8 Av0 0.6 0.4 0.2 0 0 5 10 ot = nt (sec.) 15 Fig. 420-03 60 65 70 45 50 55

A good step response is one that quickly reaches its final value. Therefore, we see that phase margin should be at least 45 and preferably 60 or larger. (A rule of thumb for satisfactory stability is that there should be less than three rings.)
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-6

Uncompensated Frequency Response of Two-Stage Op Amps Two-Stage Op Amps:

VDD VCC

M3 M4

M6
vout vin +

Q3

Q4

Q6
vout

vin +

M1 M2

Q1

Q2

+ VBias -

M5 VSS

M7

+ VBias -

Q5 VEE

Q7
Fig. 420-04

Small-Signal Model:
D1, D3 (C1, C3) + g v gm1vin v1 m2 in R1 C1 2 2 D2, D4 (C2, C4) R2 C2 + v2 - gm6v2 D6, D7 (C6, C7) + R3 C3 vout Fig. 420-05

gm4v1

Note that this model neglects the base-collector and gate-drain capacitances for purposes of simplification.
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-7

Uncompensated Frequency Response of Two-Stage Op Amps - Continued For the MOS two-stage op amp: 1 1 R1 gm3 ||rds3||rds1 gm3 R2 = rds2|| rds4 and R3 = rds6|| rds7 C1 = Cgs3+Cgs4+Cbd1+Cbd3 C2 = Cgs6+Cbd2+Cbd4 and C3 = CL +Cbd6+Cbd7 For the BJT two-stage op amp: 1 1 R1 = gm3 ||r3||r4||ro3 gm3 R2 = r6|| ro2|| ro4 r6 and R3 = ro6|| ro7 C1 = C3+C4+Ccs1+Ccs3 C2 = C6+Ccs2+Ccs4 and C3 = CL+Ccs6+Ccs7 Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives,
gm1vin R2 C2 + v2 - gm6v2 + R3 C3 vout gm1Vin RI CI + VI - gmIIVI RII CII + Vout Fig. 420-06

The locations for the two poles are given by the following equations 1 1 p1 = RICI and p2 = RIICII where RI (RII) is the resistance to ground seen from the output of the first (second) stage and CI (CII) is the capacitance to ground seen from the output of the first (second) stage.
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-8

Uncompensated Frequency Response of an Op Amp

Avd(0) dB -20dB/decade

|A(j)|

GB 0dB Phase Shift -45/decade 180 log10() -40dB/decade

Arg[-A(j)]

135 90 45 0 |p1'|

-45/decade

|p2'| 0dB

log10()
Fig. 420-07

If we assume that F(s) = 1 (this is the worst case for stability considerations), then the above plot is the same as the loop gain. Note that the phase margin is much less than 45. Therefore, the op amp must be compensated before using it in a closed-loop configuration.
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-9

MILLER COMPENSATION Two-Stage Op Amp

VDD M3
CM Cc vin +

VCC

M4 M6
vout CII vin +

Q3

Q4 CM
Cc

Q6
vout CII

M1

M2
CI

Q1

Q2
CI

+ VBias -

M5 VSS

M7

+ VBias -

Q5 VEE

Q7
Fig. 420-08

The various capacitors are: Cc = accomplishes the Miller compensation CM = capacitance associated with the first-stage mirror (mirror pole) CI = output capacitance to ground of the first-stage CII = output capacitance to ground of the second-stage
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-10

Compensated Two-Stage, Small-Signal Frequency Response Model Simplified Use the CMOS op amp to illustrate: 1.) Assume that gm3 >> gds3 + gds1 gm3 2.) Assume that CM >> GB Therefore,
v1 -gm1vin
2

v2 gm2vin
2

Cc + vout -

1 rds1||rds3 CM gm3

gm4v1 C1 rds2||rds4 gm6v2

rds6||rds7 CL

v2 + vin gm1vin CI rds2||rds4

Cc CII + vout Fig. 420-09

gm6v2

rds6||rds7

Same circuit holds for the BJT op amp with different component relationships.
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-11

General Two-Stage Frequency Response Analysis Cc where V2 + + gmI = gm1 = gm2, RI = rds2||rds4, CI = C1 Vin gmIVin Vout RI gmIIV2 RII CII and CI gmII = gm6, RII = rds6||rds7, CII = C2 = CL Fig.420-10 Nodal Equations: -gmIVin = [GI + s(CI + Cc)]V2 - [sCc]Vout and 0 = [gmII - sCc]V2 + [GII + sCII + sCc]Vout Solving using Cramers rule gives, Vout(s) gmI(gmII- sCc) Vin(s) = GIGII+s [GII(CI+CII)+GI(CII+Cc)+gmIICc]+s2[CICII+CcCI+CcCII] Ao[1- s (Cc/gmII)] = 1+s [R (C +C )+R (C +C )+g R R C ]+s2[R R (C C +C C +C C )] I I II II 2 c mII 1 II c I II I II c I c II where, Ao = gmIgmIIRIRII 1 1 s s s2 s s2 In general, D(s) = 1-p1 1-p2 = 1-s p1+p2+p1p2 D(s) 1-p1 + p1p2 , if |p2|>>|p1| gmII -1 -1 p1 = RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc gmIIR1RIICc , z = Cc -[RI(CI+CII)+RII(CII+Cc)+gmIIR1RIICc] -gmIICc -gmII p2 = CICII+CcCI+CcCII CII , CII > Cc > CI RIRII(CICII+CcCI+CcCII)
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-12

Summary of Results for Miller Compensation of the Two-Stage Op Amp There are three roots of importance: 1.) Right-half plane zero: gmII gm6 z1= Cc = Cc This root is very undesirable- it boosts the magnitude while decreasing the phase. 2.) Dominant left-half plane pole (the Miller pole): -(gds2+gds4)(gds6+gds7) -1 p1 gmIIRIRIICc = gm6Cc This root accomplishes the desired compensation. 3.) Left-half plane output pole: -gmII -gm6 p2 CII CL This pole must be unity-gainbandwidth or the phase margin will not be satisfied. Root locus plot of the Miller compensation:
Closed-loop poles, Cc0 j Open-loop poles Cc=0 p2
ECE 4430 - Analog Integrated Circuits and Systems

p2'

p1'

p1

z1

Fig. 420-11

P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-13

Compensated Open-Loop Frequency Response of the Two-Stage Op Amp

|A(j)F(j)|

Avd(0) dB

Uncompensated -20dB/decade Compensated GB

0dB Phase Shift Uncompensated

Arg[-A(j)F(j)|

log10() -40dB/decade -45/decade -45/decade Compensated |p1| No phase margin |p2'| |p2| |p1'| Phase Margin log10()
Fig. 420-12

180 135 90 45 0

Note that the unity-gainbandwidth, GB, is gmI gm1 gm2 1 GB = Avd(0)|p1| = (gmIgmIIRIRII)gmIIRIRIICc = Cc = Cc = Cc
ECE 4430 - Analog Integrated Circuits and Systems P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-14

Conceptually, where do these roots come from? 1.) The Miller pole: 1 |p1| RI(gm6RIICc)
vI RI

VDD Cc RII vout M6

gm6RIICc
Fig. 420-13

2.) The left-half plane output pole:

VDD Cc RII vout M6 CII

VDD RII vout

gm6 |p2| CII

1 GBCc 0

M6

CII
Fig. 420-14

3.) Right-half plane zero (Zeros always arise from multiple paths from the input to output): g m6 -RIIsCc - 1 -gm6RII(1/sCc) RII vout = RII + 1/sCc v + RII + 1/sCc v = RII + 1/sCc v where v = v = v.
ECE 4430 - Analog Integrated Circuits and Systems

VDD Cc RII vout v'' M6 v'

Fig. 420-15

P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-15

Influence of the Mirror Pole Up to this point, we have neglected the influence of the pole, p3, associated with the current mirror of the input stage. If |p2| |p3|, we have problems in compensation. This pole is given approximately as -gm3 p3 CM
F=1 Avd(0) dB Cc = 0 -6dB/octave Cc 0 GB 0dB Phase Shift 0 45 90 135 180 |p1| Cc 0 Roll-off due to p3 log10() -12dB/octave -p2 Closed-loop poles -p3 -p Open-loop poles 1 z1 j

Cc = 0 -45/decade Cc 0 -45/decade Cc = 0 Phase margin due to p3 Phase Margin log10() Excess Phase due to p3
Fig. Fig. 420-16

|p3| |p2|

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2001

Lecture 420 Compensation of Op Amps-I (12/10/01)

Page 420-16

SUMMARY Compensation Designed so that the op amp with unity gain feedback (buffer) is stable Types - Miller - Miller with nulling resistors - Self Compensating - Feedforward

ECE 4430 - Analog Integrated Circuits and Systems

P.E. Allen - 2001