DESIGN AND MODELING OF DEEP-SUBMICROMETER MOSFETS

by Min-Chie Jeng

Memorandum No. UCB/ERL M90190 October 2,1990

DESIGN AND MODELING OF DEEP-SUBMICROMETER MOSFETS

by Min-Chie Jeng

Memorandum No. UCBERL M90/90

2 October 1990

ELECTRONICS RESEARCH LABORATORY

College of Engineering University of California, Berkeley 94720

Design and Modeling of Deep-Submicrometer MOSFETs

PhcD

Min-Chie Jeng

ABSTRACT
A photoresist ashing technique has been developed which, when used i conjunction with n conventional optical lithography, permits controlled definition of the gate of deep
submicrometer MOSFETs. 'Ihis technique can also be extended to other lithographic

processes, such as e - b and x-ray. Comprehensive studies based on the pedormance and
hotelectron reliability hwe shown that the basic physics d a t e d with deepsubmi-

devices is similar to that of their longer<hannel mmkprts. 'Iherefoxe, existing device

design guidelines and models can still be used with minor modifications. A set of design
curves has been generated based on experimental d t s With various mechauisms under COD

sideration. W h these design curves, the t r & d s i t

between dewice dimensions and power sup

ply for a particular technology am be cbsemed. 'Ihe relative importance of each mechaaism
can also be identified.

A semi-empirical MOSFET drain cwrent model BcwBtc down to quarter-micron thaneels, suitable for digital as well
LIS

analog qqAidons has been developed. Both the drain

currenf and the output reshnce am accurately modeled. 'Ihe first derivative of the drain
ament equation i Continuous s

hm the subthreshold region to the Strong-iWerSiOn region and

from the linear region to the s a t u d o n region. for d b a e . 'Ibis model has b e a implb l iss

mented i SpIcE3. A parameter extraction system dedicated to the model was also developed. n

ii

iii

ACKNOWLEDGEMENTS
Fm of all, I would like to express my deepest apprcciarions t my ltseaTch advisor Prof. o
Ping K KO. This dissertation would not have been possible without his guidance and support. .

I also would like to thank my ca-advisor Prof. Chcnming Hu for his helpful discussion
and valuable comments throughout t i w k hs o

I would like to t a k Prof. Charles I. Stone of Statistics Departmau for W i g a member hn

of my qualifying exam and for providing me basic statistical background which is very helpful
in extracting model parameters in this work

I would like to thank Prof. David A. Hodges for his continuous encouragement and s p u
port of the BSIM project I am grateful to Prof. Sing J. S k u of USC and Tony Fung for their kind help in the
early stage of this work. I thank D. Albert T Wu, James Chung, James E Moon, Kataline r . .

Voros, M r l n Kushner, Robin R Rude& and Tom Booth for -theirassistaaCe in fabricating aiy
deepsubmicrometer devices.

I also would like to thank my officemate, P e r M. Lee and Jon S Duster, for providing .
me a friendly working environment and for proofreading this dissertation. I really enjoyed working with them.
Fnly I am indebted t my parents who always provide me ial, o
strtngth

and faith at the

right time, and my beloved wife, Ya-Lte, for hex patience and sacrifice during my graduate

study at Berkeley.

This research was funded by the Semiconductor Research Corporation, the California
State MICRO

program and JSEP under contract F49620-84-c-0067.

Table of Contents
Chapter 1 INTRODUCTION :
1.1.

.................. ...............................................L...-. ...... ......

...............................................................

design

...

n.... ....n....n... .. .. .. .. ..n.n.n.n...-. ....n.... ..... .-.n.n.n.n.n.. .. .. .. .. .-..

2
4 5
7

............. 1 .atline ..... 3 ..... ............ ..................... .................. .........-. . 1.4. References .................................................................. ......................................... ....
12 Device mod$ing

Chapter 2 DEVICE FABRICATION :

....... .................................................................... 2.1. Fabrication process ........................................................................................ ......... 2 2 .Photoresist-ashing technique .......................................................................... ......... 22.1. Wder ppati0a ................................................ .................. .................. ..... 2 2 2.EtchiDg process .............
U

1 1

1 1

12
14
14

.....................................................................

...._.............. ............................................................... ... .. 23.Device chamAenstics ....................................... .................................................. . .. 2.4. References ............... .................... . ....................................... .... ...._ ....................... .
2 2 3 l3primataI results

15
23
27

Chapter 3 PERFORMANCE AND HOT-ELECTRON RELIABILITY OF :

DEEP-SUBMICROMETER M O M

..........

............................. ......................

28
29 37 28

3 2 2 Subthreshold swing

........................................................... . ..

.........

48
48

3 3.CmeQt driving capability

.......................................................................................

vi

52

52

53
58
61

61

69
73
Chapter 4: DEEP-SUBMICROMETERMOSFET DESIGN

........................................ 4.1. Device limitations .................... ........................................................... ................... 4.1.1. 'Ihreshold voltage shift . . . . . . . . . . . . . .......................................................... . 4.1 2.a-state leakage CUUW ................. ............................................. 4.13. Hotelectron reliability ............................ ... ..................: ... ............. ...................
n
n...-...n..

79

80 80 80
85
85

... 4.15. Tidependent-clieldc b r e a k h ...... ..... ................ ........ . 4 2 .P r o m n e constraints ....................................................................... efrac . ................. 42.1. Chrrat-driviqg capability ............... ........ ....... .................................................. 4 2 2 .Voltage gain .......................... ......... . ..... ................. ................. ......... 4 2 3 .s i w* speed ..............-.. ................... .............. ............. ....... 4 3 .W i n g u i & h ................ ....................... ................................................... ....... t h i c k vusus c h d length ... 43.1. 4 3 2 .Power supply versus channd leagth ......... ...... .................................... . 4 3 3.Power supply vezsus oxide thickness .... .................................................. "....... 43.4. Junction depth ............ ................................................................ . ...................
4.1.4. Breakdown voltcrge

................

. n -

85

89 89
89
89

. H

94
95
97

. -. n .. -. .a .. .n. .n .. .n .

97
97

"

4 3 5 OttKt puwa Supply and devioe dmadoas

.... ...

. . . . . . . . . . . . . . . . . . . . . . . .

100

.................-................... ....... 4.4. RefCnaas . . . . . . . . . . . . . . . . . . . . . . . . . ........................

4 . other techwlogies .......................... 36
Chapter 5: A DEEP-SUBMICROMETER MOSFE3I' MODEL FOR

100
102

ANALOGDIGITAL CIRCUIT SIMULATIONS

.... ..................... ........................ 104 ........ .................-.. 105 5.1. General properties of MOSFET modcliqg ................... 5.1.1. Semi-emphkaI nature .................................................... .............. ".. 105 5.12. Accuracy ................................................................. ................... 105 5.13. compltational efficiency .................................................................... .............. 106 5 1 4 Ease of parameter extraction ................................................................. ... ...".. 106 52.BSIM.Berkeaq Short-chmd IcaFm Model ..... ....................................... ...".. 107 52.1. ?he BSIM agpIoach ....................................... ......................................... ......... 107 522.BSTMl revim ....... ................. .. ............. ............ ....."....... 107 53.?he BSIM;! moQl .............. ....................................... ................ .............. 110 . 53.1. Physical effects included ................ ......................... ......... 110 . .
" " "
n........"...n..

"

"

"

"

.................................................................................... 113 533.Subthreshold region .................. ............... ................................. .... 128 . 53.4. Transition e o n . . . . . . . . . . . . ............................................................. .....".. 130 535.c)utpt resistance modeling .......................................................... ........"...".. 137 53.6. Biasdependeat paremerers .......... ................... ............... .............._..148 . 53.7. S h i n d e p d e a t pammtas ........................................................................ ".. 149 5.4. Parameter extraction for WIM2 ...... ..... ................. ".............".. 151 5.4.1. Automated parameter extraction system ..... ................................ ".. 151 .
532. Strong-inversion region
" "

5.42.

@orithaas

."...............

.. -. .. n. .. n. .. .. .n . .

152

Chapter 1

INTRODUCTION
In t e last decade, MOS devices have been miniamid t acbieve higher packing h o
derp

sity, higher integration levels, and higher current drive. R c n advances in process technology eet (1.1-1.71 have made deepsubmicrometer MOSFETs potential candidares for next generation

ULSI designs. However, by demasing channel length while maintaining the current power
supply voltage, the electric fields in the device will m e r increase, causing the device characteristics to deviate from the long-channel behavior and also creating reliability problems.

ot The two high-field effects m s pronounced on device performance are the mobility
degradation due to vertical-field [1.8-1.111 and the carrier velocity saturation [1.12,1.13]. Both effects cause the MOSFET drain current drive to increase at a slower rate than that predicted

by simple scaling theories. The threshold voltage shifiand subthreshold swing

IVC

also larger

at shorter channel lengths and high drain voltages [1.14-1.20) which make short-channel MOS
transistors more difficult t turn off. Such parameter variations have a severe impact on worst o
case circuit design rules and pose serious problems in VLSI proccss control.

More consequences of the high electric fields in submicrometer devices are the hot-

o electron effects [1.21,1.22) due t impact ionization in the velocity saturation (piich-oft)
region. The injection of energetic electrons released by impact ionization into the Si-SO, interface generates interface traps that degrade the device characteristics, and results in longterm reliability problems [123-1.27]. TIe substrate current, which is composed of impactionization-generated holes, can overload the substrate-bias generator and causes snap-back and

CMOS latch-up [1.28,129]. In addition to t e performance and hotclcctron reliability, which h

arc two major concern for the feasibility of deepsubmicrometer MOSFETs in circuit applica-

tions, the increasing complexity in circuit designs and fabrication processes is another subject

t consider in developing VLSUULSI systems. o

chap.1

-2-

Hotclectron effects and their related reliability issues together with thc rlnady complicatcd short-channd effects make deepsubmicrometer MOS device design much more difficult

than ever. From a device design point of view, fabricating devices with optimal perfomanx
and n l i a b i i requires a comprehensive understanding of tbe trade-off& among many

facoors

such as device dimensions, device performance, parameter variations, and process complexity.

From a circuit design point of view, to expedite M S I system design and to reduce development overhead, it is necessary to stii~the circuit dqign in the M y stages of technology development and to predict the circuit behavior as accurate as possible before the circuit is actually fabricated. However, previous reports on deepsubmicrometer devices have f d on how to fabricate these devices without formulating any design guidelines, which makes
optimal device design almost impossible. For circuit simulations, m s existing MOSFET ot

models axe not accurate enough for the deepsubmicrometer regime.

This dissertation provides a unified understanding of deepsubmicrometer devices through

experimental study of basic device charactc&ics and hot-clactron effects. By investigating the effects of device parameter variations on various design constraints, different types of device design cwves are obtained. An accurate MOSFET model is also developed based on an improved physical understanding of deepsubmicrometer transistors.

11 Device design .
Traditional electrostatic approaches to scaled device designs have been based on generic guidelines known as constant-field (1.301, constant-voltage, and quasiconstant-voltage r1.311
scaling laws.

A summary of these scaling laws and the results are given in Table 1.1 [1.32].

' Wnstant-field (CE)scaling law was W prop~sed Denarrd. According to this Scaling h by

ht law, all the device parameters and the power supply are scaled by the same factor k so t a the
internal electric field strength and patterns arc unchanged after scaling. However, because the

CE

scaling also proportionally

duces the power supply, it lacks T % compatibility and also I

reduces the device current driving capability and signal-to-noise ratio.

T avoid the 'ITL compa!ibility pmblans, the wnstant-voltage (CV)and quasiconstamo

voltage (QCV) Seatings w a e proposed. Under these scaling laws, tfre device dimensions are
also scaled by the same factor k as in thc CE case, but thc power supply i kept constant (CV) s

or scaled down by a factor of

(QCV). Although these nonconstant field scaling l w are as

mon practical and result in better device and circuit performance, thc bot-clectron effects am much more severe because the channel electric field in the velocity saturation region i incnass

h rapidly as the device channel length is reduced. .For this reason, it has been generally g
recognized that as long as the power supply remains high for practical considerations, some
type of hotelectron-resistant smcture, like LDD, is needed for submicrometer MOS transis-

tors.

In reality, however, some device parameters, such as the source and drain junction
depths, are relatively unscalable for most technologies, and the power supply can not be easily scaled. All of these scaling laws are difficult to apply in practice. They a~ only used as conceptual guidelines for minimizing the short-channel andlor hot-clectron effects. Practical scaling approaches should be developed based on device performance limitations and constraints as proposed by Masuda (1.331, Bnws [1.34], and Shichijo [1.35] for near-micron devices. Because of technology advances, these design curves and conclusions are not applicable in the deepsubmicrometer regime. More recent studies for 0.5p.m devices were reported by Takeda [1.36] and Kakumu [1.37]. However, these studies are incomplete as only few design constraints were considered. For deepsubrnicromekr devices, more physical effects are becoming

important and should be taken into considerations when developing design guidelines.

In the first part of this report, a comprehensive study of the performance and reliabiity constraints on the device dimensions and power supply of deepsubmicrometer MOSFJTs is
presented. A set of design cuwes, extracted from experimental results, are developed based on

the following considerations: shortchannel and drain-induced-barrier-loweringeffects, off-state

leakage current, hot-electron reliability, timedependent dielectric breakdown, cumnt driving

capability, voltage gain, and switching speed. Although these design curves are only for n-

chap.1

channel nan-LDD devices, dre same methodology can still be applied to other technologies including pchannel and LDD devices.

12 Device Modeling .
With increasing system complexity due to high-level integration, an efficient circuit simu-

lator with accurate device models becomes an indispuwbre toot in VLsVULsI designs. A
complete device model must be capable of pndicting device characteristics for all operating modes over a wide range of device dimensions. S i models with underlying equations derived from semiconductor physics are more extendible to include new physics and suitable

for process control and diagnosis, most early MOSFET models an physics-based models.
However, with the ever decreasing device dimensions, an accurate model based fully on device physics is impossible t develop due t the 3-dimensional nature of small-geometry devices o o

and other high-field effects. Even if it were feasible, the complicated equation forms involved
in a fully physical model would have prohibited its usage for circuit simulation purposes.
Furthermore, a fully physics-oriented modeling approach usually makes the parameter extraction very difficult 'Ihe desire t achieve mom accurate modeling and alleviate o difficulties in parameter extraction created the need to add empirically-based parameters to the existing physical parameters. 'This type of model i categorized as a semicmpirical model. s

The semi-empirical model retains the basic funcdonal form of fully physics-based models while
Feplacing sophisticated equations by empirical equations with f t i g parameters to account for itn

oes small-geometry effects and minor process variations. Since semi-empirical m d l have the
advantages of simplicity and computational efficiency, all models in circuit simulations to date,

t a certain extent, have been semiempirical models. o

It has been shown that properly designed deepsubmicron MOSFETs exhibit device characteristics s m l r to those of their longer-channel counterparts [1.38], but significant iia

second-order effects due t pnviously negligible physical phenomena make existing drain o
current models unsatisfactory. Furthcnnore, many of t e drain current models used for circuit h

simulations are inadequate in m d l n the output nesistuKx tnb the weak-inversion characoeig tenstics, which are very important for analog applications. Since decpsubmiaon devices typi-

Cany have ti gate oxides, the inversion-layer capadtancc becomes comparable t the gate hn o
capacitance, which is an important factor to Consider m circuit simulations. In order to bridge

the gap between deepsubmicrometer devices and circuit simulatia& 1 MOSFEI' drain cumnt
model accurate down t quarter-micron channel kngths, suitable for digital as well as analog o
applications has been developed bascd on an improved physical understanding of dcep

submicrometer MOS transistors.

13 Outline .
Chapter 2 describes the fabrication process and some of the characterization procedures for the deep-submicrometer MOSFETs used in this study. Chapter 3 describes some device characterization methods important t thc short-channel o devices. Chapter 4 presents a set of design cufves derived from experimental results based on a wide range of design considerations. These design curves provide comprehensive design guidelines for deepsubmicrometer devices. The relative importance of various mechanisms is
also identified.

Chapter 5 describes a deepsubmicrometer MOSFET drain current model suitable for both digital and analog simulations. The basic algorithm and theory for parameter extraction are
also briefly described.

Chapter 6 concludes this dissertation.

Power supply ( d V
Gate oxide ( , TJ
Channel length (L)

1/k

l/JE
ltk

l k
Ilk

1bE

ltk
1/k

ltk
I/k

Channel width (W) Junction depth (xi) Doping concentration ( m N ) Threshold voltage (VJ Saturation current (IDSAT) Transconductance (&d
Output resistance (%113

Ilk

Ilk

l/k

l/k

k
l/JE
1
I

Ilk
Ilk
1 1

*
JE

JE
1 ~ 4

Power density ( m P )
Subthreshold Swing (S)
I
I

P
1

P
1

as Table 1.1 Results of various scaling l w .

1.4 References

W. Wchtner, RK. Watts, D.B. Fraser, R.L. Johnston, and S.M. Sze, "0.15 pm
channel-bgth MOSFETs Fabricated Using Epp.272-725, 1982.
W. Hchtner, EN. Fuls, R.L. Johnstoa, RK Warts, and W.W. Weick, "optimized Lithomy," IEDM Tech Dig.,

MOSFETs with Subquartermicron Channel Leqtb," IEDM T c Mg., pp.384-387, ah

1983.

T. Kobayashi, S. Horiguchi, and K. Kiuchi, "Deepsubmicron MOSFET Characteristics w t 5nm Gate Oxide," IEDM Tech. Dig., pp.414417, 1984. ih

S. Horiguchi, T Kobayashi, M. Oda, and K. Kiuchi, "Extremely High Transwnduc.

tance (Above SOOmSEhnm) MOSFET with 2.5m Gate Oxide," IEDM tech. Dig.,
pp.761-763, 1985.

S.Y.Chou, H.I. Smith, and D.A. Antoniadis, "SublOO-mChannel-Length Transistors

Fabricated Using X-Ray Lithography," J. of Vacuum Science Tech. B, vol. 4, no. 1,

pp.253-255, Jan/Feb 1986.

J. Chung, M.4. Jeng, JE. Moon, AT. Wu,T Y Chan, P.K. KO, and C. Hu, "Deep ..
Submicrometer MOS Device Fabrication Using a Photoresist-Ashing Technique," IEEE
Electron Device LeUers, voL 9, no. 4, pp.186-188, April 1988.
G.A. Sai-Hdasz, M.R. Wordeman, D.P. Kem, E Ganin, S. Rishton, D.S. Zicherman,

H. Schmid, M.R. Polcari, ICY. Ng, P.J. Restle, T.H.P. Chang, and R.H. D e d ,

"Design and Experimental Technology for 0.1 pm Gate-Length Low-Temperature

Operation FET's," lEEE Electron Device Letters,voL EDL-8, no. 10, Oct., 1987.
S.C. Sun and J.D. Plummcr, "Electron Mblt in Inversion and Accumulation Layers oiiy

on Thewally O i i e Silicon Surfaces, " IEEE Tran. on Electron Devices, voL EDxdzd

27, p.1497, August, 1980.

(1.91

A.G. Sabnis and J.T. Clanam,

"characterization of the Elemon Mobility in thc

Inverted ~ 1 0 0Si S d m " IEDM Tech Dig., ~p.18-21,1979 , (1.101 M-S. Liang, JY Chi,P.K. KO,and C. Hu. "Inversion-Layer Capadtam and Mobil..
ity Of VCXY Thin Gate-OxMe MOSFET'S," IEEE Tan.

Electron Devi=, VOL ED-

33, p.409, March, 1986. f1.11) S. Takagi, M. Iwase, and A Toriumi, On the Universality of Inversion-Layer Mobility in N-and P-Channcl MOSFET's," EDM T c Dig., pp.398401.1988. eh (1.121 R.W. Coen and RS.Muller, "Velocity of Surface Crir in Inversion Layers on Siares

con," Solid-stateElectronics, vol. 23,p.35, 1980.

(1.131 J.-P. Leburton and G.E. D o h , "v-E Dependence in Small-SizedMOS Transistors,"

IEEE Trim on Electron Devices, vol. ED-29, no. 8, Aug. 1982.

(1.141 H.S.Lee, "An Analysis of the Threshold Voltage for Short-Channel IGFET's," SolidState Ele~tronic~, 16, p~.1407-1417,1973. VOL

(1.151 L D Yau, "A Simple Theory t Predict the Threshold Voltage of Short-Channel .. o

IGFET's," Solid-Stae ElectrOnic~, VOL 17, ~.1059-1063,1974.

(1.161 T. Toyabe and S. Asai, "Analytical Models of Threshold Voltage and Breakdown Voltage of Short-Channel MOSFET's Derived f o Two-Dimensional Analysis," IEEE J. rm Solid-state Circuits, VOL SC-14, p.375, April, 1979. [1.17] K N Ratnakumar and J D Meindl, "Shon-Channel MOST Threshold Voltage Model," .. ..

IEEE J. Solid-state Circuits, vat. SC-17, p.937, O a , 1982.

[1.18] H C Pa0 and C.T. Sah, "Effects of Diffusion Current on Characteristics of Metal.. Oxide (Insulator) Semiconductor Transistors, "Solid-state Electronics, voL 9, p.927, 1966.

n [1.19] R.M. Swanson and J.D. Meindl, "Ion-Implanted Complementary MOS Transistor i
Low Voltage Circuits," IEEE J. Soilid-State Circuits, vol. SC-7, p.146, April, 1972.

chap.1

-9-

r1-20]

.. R R Troutman and S.N. chalrravarti, "Subb&OldQlaraaefisbcs of I.mulated-Gate ..

Rdd
Tansistoft," IEEE ?"ran.
OLI

Cirarit T ~ O I Y , m2 , p.659, Nov., VOL - 0

1973.
[1.21] T.H. Nmg, P.W. cook, RH.Dennard, C.M. Osbum, S.E. Schuster, and IN. u " 1 Y,

p MOSFE" VLSI T c n l g , Parr IV. Hot-Elmn Design Constmins," IEEE ehooy

Tran. on Electron Devices, voL ED-26, pp.346-353,1979.
[1.221 C. Hu, "Hot-ElectronEffects i MOSFT's," n [1.231

IEDM Tech Dig., pp.176-181, 1983.

H Gesch, J.P. LebuRon, and GB. Donla, "Generation of Interface States by Hot.
Electron Injection," IEEE Tran. on Elcctron Devices, VOL ED-29, p.913,1982.

[1.24] E. Takeda and N. Suzuki, "An Empirical Model for Device Degradation due t Hoto Carrier Injection," IEEE Electron Device Letters, vol. EDL-4, pp.111-113, 1983.
[1.251 E.

T k d , A. Shimizu, and T Hagiwara, "Role of Hot-Hole Injection in H o t - M e r aea .

Efects and the Small Degraded Channel k a o n in MOSFET's," IEEE Electron Device

Letters, vol.EDL4, no. 9, Sep, 1983.

[1.261

F C Hsu and S. Tam. "Relationship between MOSFET Degradation and Hot-Electron ..

Induced Interface-State-Generation," IFlEE Elecmn Device Letters, voL EDL-5, p.50,
1984.

.. fet (1.271 K-L. Chen, S.A. Saller, I.A. Groves, and D B Swtt, "Reliability E f c s on MOS
Transistors due to Hot-Mer ~p.386-393,1985.
[1.281

IEEET a .on Electron Devices, voL ED-32, rn

Y.W. Sing and B. Sudlow, "Modeling and VLSI Design Constraints of Substrate
Cumnt," IEDM T c .Dig., p.31, 1975. eh

[1.29) J. Matsunaga,

"Characterization of Two Step Impaa Ionization and It's M u m a on

NMOS and PMOS VLSI's," IEDM Tech Dig., p.736, 1980.

.. (1.301 R.H. Dennard, F.H. Gaensslen, H.-N. Yu, V L Rideuit, E. Bassous, and AS.
LcBIanc, "Design of Ion-Implamtcd MOSFET's with Very Small Physical Dimen-

sions," IEEE J. Sdid-State Circuits, Vd SC-9, m. 5, Oct, 1934.

[1.31] PX. 5tCajce. WR. Hunter, T C Hollowry, md Y T Lin, "][he Impact of Scaling .. ..

Laws on the Qloice of n-Clmnel or pchawel for MOS VLSX,"IEEE Elecawr Device Letters,w EDL-1, no. 10, Oct, 1980. L
[1.32]

CX. W n ,"Switched Capacitor Signal F9ocahg Circuits i Scaled Tcchmlogits," ag n

PhD Dissertation, Univ. of California, Berkeley, 1986.

(1.331 H. Masuda, M N U , and M. Kubo, "Charactc~Wcs Limitation of Scaled-Down and MOSFET's Due to Two-Dimensional Field Ef "IEEE Tran on Electron Devices, fm
VO~. ED-26, pp.980-986, Jw,

1979.

[1.34] JR. Brews. W. Rchtner, E.H. Nimllian, and SM. Sa,"Generalized Guide for MOSFET Miniaturization," IEEE Electron Device Letters, vol. EDL-1, no. 1, Jan., 1980.

[1.35] H. Shichijo. "A Re-examination of Practical Performance Limits of Scaled n-Channel and pchannel MOS Devices for -1," ~p.969-986,1983. [1.361 E. Takeda, G.A.C. Jones, and H. b e d , "constraints on the Application of 0 . 5 - p MOSFET's t ULSI Systems," IEEE Tran. on Elecoon Devices, vol. ED-32,no. 2, o Solid-state Electronics, voL 26, no. 10,

Feb., 1985.
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"Performance and Hot-EIectron Reliability of DtcgSubmicrometer MOSFETs," IEDM

Tech Digs., pp.710-713, 1987.

-1 1-

Chapter 2

DEVICE FABRICATION
The devices used in this study we= n-chand mn-LDD transistars fabricated using an

NMOS technology with a photoresist-ashing technique l2.1) t define the o

gates

of deep

submicrometer devices. Since most steps of t i p r o p s arc common to those of standard hs fabrication processes, only the major procedulles are described. A complete process flow is given in Appendix A.

2.1 Fabrication process

The starting wafers have p y e substrates with 15-30 S2pm bulk resistivity. A blanket tp

boron (B 11) implant of 1.5 x lo'* cme2 at 70 KeV was used for both field and punchthmugh
controls. The active area was defined using LQCOS. The field oxide thickness of 2800

was grown in wet oxygen at 95OoC and annealed in nitrogen for 20 minutes at the same tcmperature. The enhancement thmhold implant dose (B11 at 30KeV) were chosen to yield a
longchannel threshold voltage around 0.65V for all gate oxide thicknesses. An array of deple-

h tion implant dose (As, 50KeV) wen used for these wafers because of t e difficulty in determ n n the threshold voltage due to seven shortchannel effeds in depletion-mode devices. iig
Various gate oxide thicknesses, 3.6,5.6, 7.2, 8.6, and 15.6nm, wen grown in dry oxygen

a 800-900"C, depending on the oxide thickness. Immediately after the gate oxidation, a layer t
of 2500 ds, phosphorusdoped polysilicon was deposited using LPCVD. After the gate
definition, which will be described in more detail in next section, the n+ sourcddrain regions
were implanted

(As,3 x lOI5 ern-', SOKcV) with 8 inclination to avoid asymmetric device

undo@ LTO was deposited at 450C and

characteristics [2.2]. Then, a layer of 3OOO

densified at 900 "C for 20 minutes in dry oxygen. After etching the contact hole, 2500

51

chap2

-12-

ptmsphorus-cioped polysilicon was deposited at 6 5 0 " ~mi u3ivrted i nitmgcn at 9 0 0 " ~for n

c d 15 m n t s This po1ysilicon m as iue.

1M

e r layer t prevent rhunium from spiking o

through the soumidrain region i t the substrate. FinaUy, the conaxing metal (Al with 2% no

S ) was sputtered and d e W , followed by an e& of the plysilicon outside the amtact uu. i t
In order t minimize the junction depth, all of b e subsequent thermal cycles after the o
source/drain implantation wen l m t d t 900C or below, and tbe t t l amount of time iie o oa

required by these thermal cycles was less than 60 minutes. 'Ihe junction depth was determined
to be 0.18p from spreading resistance technique. The lateral diffusion was estimated to be

about 0.025p.m from SEM pictures.

2.2 Photoresist-ashing technique

Because of the limited resolution of conventional optical lithography, e-beam d Writi m
ing and X-ray lithography have been the principal techniques used to fabricate deep submicrometer devices [2.3,2.4]. However, both techniques an complicated and expensive. In addition, their irnpact on the long-term device reliability as a result of exposing the device t o high-energy radiation has yet to be fully charaucriztd

In this study, a photoresist-ashing technique has been developed which, when used in
conjunction with conventional g-line optical lithography, permits the controlled definition of the gates of deepsubmicrometer devices. Although this ttchnique dots not help to improve tbe circuit layout design rules, it does provide an alternative, economical,and efficient means for

s device-level studies of deepsubmicrometer MOSFETs. When this technique i applied to an

existing p , it will improve the circuit performance because of the enhanced device

current drive due t smaller channel length beyond lithography limits. Since most polymero
based resist m t r a s are ashable with oxygen plasma, this photoresist-ashing technique can aeil

also be extended to supplement other lithographic process, such as those of e-beam and X-ray.

-13-

oxygen plasma

polysilicon

polysiIicon

The basic idea of this photoresist-ashing technique is very Simple as is

2.1. First, photo-

fig.

with near-micron sizc was defined using conventional opcicrir lithography

and developed (Fig. 2 h . Tbcn the wafers an isompically etched in oxygen plasma at a cali.)
brated mte until the designated pattern size is achieved (Fig. 2.lb). Since the kft and right
sides of the photoresist arc etched at the same time, the horizontal dimension is etched at t i e wc

the rate of the vertical dimension. Tht photoresist after etching has an ultra-fine pattern but still with enough thickness to define the polysilicon gates.
2.2.1 Wafer preparation

Kodak 820 photoresist was spun at 4600 rpm for 25 seconds and soft-baked for 1 minute
at 100C, resulting in a photoresist thickness of 1.1 pm before etching. Transistors gates wt ih mask-level lengths ranging from 0.5 t 1.6 p,with 0.1 pm increment., wen defined using o
GCA 6200 1OX wafer stepper (g-line, 1 = 436~11).developed, and hard-baked at 12OoC for 15 minutes. Since the resolution of g-line optical lithography is only about l p , the pho-

toresist pattern with lengths less than 1p would not have sharp edges under nominal focus and exposure. To obtain consistent photoresist profiles and step coverage for all mask-level dimen-

sions, a focus-exposure test using specially designed test pattern was performed on GCA 6200
wafer stepper before the wafers we= exposed. By examining t h a photoresist test pattern

using various focusexposun combinations, optimal values were determined. This calibration
ih procedure was the most critical step in the process Depending on the condition of the l g t
source, the optimal exposure and focus deviated as much as S % %%, respectively, from O and

their nominal values.

2 2 Etching process .3
Although this photoresist ashing process could have been done in any oxygen plasma etching system, the Technics-C plasma etcher was used in this study because it has been used

in descuming the photoresist in the Micro-Elecuonics Fabrication Laboratory. The optimal

etching wndition for this purpose is still u t o however, it was found that high conmllan m l n

QW.2

-1s-

bility and uniformity could be achieved at an oxygen pnssure of 300 mTorr and an RF power

of SOW. A horizontal etch rate (per &be) of O.O35cLm/min rrnd vertical etch ntt of O.WCl/min
under these etching conditions wen obsewed. The diffehg etch rates wen due t 1 slight o anisotropy of the systan.
22.3 Experimental results

Fig. 2.2 shows SEM-measured gate length (LSBM) versus ashing time for four different mask-level gate lengths

The lateral etching rate was calculated from the slopes of

a these lines and the vertical etching rate w s calculated h a the photomist thicknesses before
and after etching using an Alpha-Step profiler. These parallel lines indicate that the etching rate
was relatively constant during the process and is independent of the initial photoresist size and

profile. In preparing these samples, an exposure about 15% under nominal exposure w s a determined to be the optimal exposure value. This under exposure explains why the pho-

toresist lengrh ka is slightly larger than the mask-level length

time = 0 min) in Fig. 2.2.

before ashing (ashing

Due to the s o etch rate, this ashing process was easily controlled and reproduced. The lw

integrity of the photoresist profile was also preserved throughout the ashing process. Fig. 2 3 .
displays the effective channel length

as a W o n of & for two different ashing t m s ie.

These parallel lines suggest a consistent photoresist profile for all mask-level channel lengths
that

is independent of ashing time, which demonstrates that the correct focus and cxposurt

values were used. The effective channel lengths, h, extracted using a capacitance techwere
nique [2.5]. Another independent method to derive Lcff which measures the resistance of the gate polysilicon l i s also confirms the d t s in F g . 2.2 and 23 is ..

-0

10

12

Ashing Time [ min ]

Fig. 2.2
SEM measured gate length versus ashing time for various mask-level channel

lengths.
1.6

1.4 1.2

" I

I,
A

-0

. 2

.4

.6

Lad
Fig. 2 3 .
after the photoresist-ashingprocess.

-'
1.2

1.4

1.6

1.8

Tasso effective channel kngth versus mask-levelchannel length before and rnitr

-2

-17-

The uniformity of the effective charmcl length of h e tratlsistols across the wafer can be
observed in Fig. 2.4 which s o the StatiSical spred hw
Of

AL ( m k - b )

O f two wlfers,

one before and one after the ashing p~oass. 'Ihe standard deviations of AL for both cases
were roughly the same, O.Mpm, revealing t a this photoresist ashing technique did not introht duce additional channel length variations to t e process. It is believed that t e mnuniformity h h

in
ing P .-

was inherent to the optical lithogmphy systcm rather than being introduced by the ash-

Fig. 2.5 shows an SEh4 picture of the cross-section of a photoresist l n after 8 minutes ie of ashing. The line width was originally 1 pm and reduced to 0.45 pm after ashing. Since the effective horizontal etch rate is higher than the vertical etch rate, the aspect ratio of the photoresist profile increases as the ashing process continues until the size of the photoresist reduces to about 0 . 2 p , which is roughly equal t the difference between the top and base o width of the pmfile. Fig. 2.6 is an SEM picture of a photoresist-covered plysilicon line lying over alternated field and active regions showning the step coverage of the photoresist along the boundary of these two regions. In order to get a 0.65V longchannel threshold voltage,,V for all oxide thiclmesss,

different implant doses were used. Fig. 2.7 shows measured Vm versus implant dose for several oxide thicknesses. The symbols represent measured data and the curyes arc calculahed

f o the well-known expression for long-channel threshold voltage. rm

where V m has an empirical value of -0.7!W, 0s is the surface potential, Nm is the average

rm channel doping concentration derived f o the substrate-bias effect. Fig. 2.8 shows a typical
channel doping profile for this process. The depth of t e channel implant is about 0.15pm. h The experimental relationship between NsuB and the implant dose D is shown i Fig. 2.9, n

-18-

AL

18

2
16

Fig. 2.4

Statistical spread of the effective channel length on a wafer, (a) without ashing,

(b) with 8 minutes of ashing.

Fg 25 i.

SEM picture of the cross-section of a photo~esist after 8 minutes of ashing. line

Fig. 2.6

SEM picture of a photoresistcovered plysilicon line lying over alternated field

and active regions.

1.4

T . = lSm o

19

Tor = 8.6nm

2 !
0

8 -J zi >o

E
0.8.
0.6.

Y
0.4

To== 3 . 6 ~ 1

09

.
d

0.0 1

Fig. 2.7

Measured long-channel threshold voltage versus enhancement implant dose for

various oxide thiclmcsser.

-21-

10'8
m i

v
or(

io",

r:

E
W 0

uo
. ( r

bD

E;
0.0 0.2
0.4

0.6

0.8

1.o

Depth (pm)

Fig. 2.8

Typical channel doping profile of lilis p

0.0

2.0

4.0

6.0

8.0

10.0

12.0

Implant Dose (xld*cm-*)

Fig. 2.9

Channel doping ColKxnoratioIl vexsus enhancement implant dose.

-2

-23-

where the symbols are measured data and the solid line i an empirical equation given by s

Nsm 12x1OI6 +4.1XlO'*D

0

(22)

where D is t implant dose in k

Wh Figs. 27 and 2.9 or equations (2.1) and (22). i t thc

enhancement implant dose for any oxide thickness and any threshold voltage can be determined
using this process.

23 Device characteristics
This photoresist-ashing technique has been successfully employed t fabricate n-channel o
non-LDD MOS transistors with effective channel length as small as 0.15p.m. Excellent device characteristics were observed. Fig. 2.10 shows an SEh4 picture of a transistor cross Section
with 0.22

pm effective channel length This transistor would have a 0 . 8 effective channel ~

length if the ashing process was not used. The junction depth is about 0.18pm measured from spreading resistance method and the lateral diffusion is about 0.05 p. The strong-inversion gate and subthreshold characteristics of a transistor with 3.6~1 oxide and 0,15peffective chan-

h nel length are shown in Fig. 2.11. T e transconductance of this device is about 6SOmS/mm,
which is among the highest reported at mom temperahlre More characteristics are shown in later chapters. The output waveform of a 101-stage mhancement/depletion-typering oscillator with one fan-in and one fan-out is shown in Fig. 2.12. This ring oscillator has 7.2m gate oxide and
0 . 2 p effective channel length. The delay time is about 22pdstage at a power supply of 3V

which is also one of the fastest ever reported at room tetnperature for MOS technology.

-24-

Fig. 2.10

SEM piof a transistor cross Section with 0 . 2 2 effective channel length. ~ The junction depth is 0 . 1 8 ~ the source/drain lateral diffusion is about and
0.05Jm

-25-

1 v 5

tv

03 v
0.0
0.6

1.2

1.8

24

3.0

Drain Current (mA)

(a1

v,-3v

N-Channd MOSFm
W ,

= 2.2 p m = 0.IS p m

v,-ov
-0.2
0

0.2

0.4

0.6

0.8

Gate Voltage (v)

(b)

Fig. 2.11

Characteristics of a transistor with , = 3.6nm and T inversion, (b) subthreshold

= 0.15p. (a) strong-

Fan-in- 1 Fan-out = 1
7delay = 21 pshtage

Fig. 2.12

Output Waveform of an NMOS 101-stage enhancementldepletion type ring oscillator.

-27-

2.4 References

(2.11

J. Chung,M.-C. Jeng, JE. M o ,AT. Wu,T.Y. Qlan, P K KO,and C. Hu, Deep on ..

Submicrometer MOS Device Fabrication U i g a Photoresist-Ashing Teclmiqu~, sn IEEE Electron Device Letters,voL 9,no. 4, pp.186-188,April, 1988. (2.21 T.Y. Chan, AT. Wu,P.K. KO,C H ,and R Razoulr, Asymmetrical Characteristics u

i LDD and Minimum-Overlap MOSFETs, IEEE Electron Device Letters, voL EDLn
7, No. 1, pp.1619, Jan. 1986.

[2.3]

W. Fichtner, R.K. W t s D.B. Fraser, R.L. Johnston, and S.M.Sze, 0.15 pm at,

Channel-Length MOSFETs Fabricated U i g E-Beam Lithography, IEDM Tech. Dig., sn pp.272-725, 1982. [2.4]
S.Y. Chou, H I Smith, and D.A. Antoniadis, Sub-100-nm Channel-Length Transistors ..

Fabricated Using X-Ray Lithography, J. of Vacuum Science Tech. B, vol. 4, m. 1, pp.253-255, Jan/Feb 1986. [25]
B.J. Sheu and P.K. KO,A Capacitance Method t Determine Channel Lengths for o

Conventional and LDD MOSFETs, IEEE Electron Device Letters, voL EDL-5, no.
11, N v , 1984. o.

Qlap.3

-28-

Chapter 3

PERFORMANCE AND HOT-ELECTRON RELIABILITY OF DEEP-SUBMICROMETER MOSFETS

Recent advances i process tezhnology (3.1-3.7) have made deepsubmimmekr MOSn

FETs potential candidates for next generation ULSI dqsigns. However, the emphases of most
previous reports have been to demonstrate the feasibility of fabricating these devices with l t l ite discussion of the physics. It is still unclear whether the basic physics associated wt deepih submicrometer devices is the same as that of their longer-channel counterparts. The lack of physical understanding is one of the reasons preventing deepsubmicrometer devices f o rm being used in current VLSI system designs. One of the goals of this study is t establish an o improved understanding of deepsubmicrometer devices and to provide a basis for device
design guidelines. Since performance and hot-electron r t l i a b i i are the two major concerns in

deepsubmicrometer device designs, they arc carefully studied in this chapter. More device characteristics are presented in the next chapter. The effective channel length,

h, probably the most important parameter among all is

MOSFE" parameters. Since the device characteristics and even some other device Parameters,
.e.g the threshold voltage, are sensitive functions of the channel length, Ld has been commonly used t identify a technology. In the deepsubmicrometer regime, accurate determinao

o tion of Ld is more crucial, because i n c o w determination of L,.J~may lead t wrong conclusion or interpretation of a physical phenomenon such as velocity overshoot. From a circuit designer's point of view, using incorrect channel lengths in simulation may cause large errors

hs between simulation results and actual circuit performance. Therefore, the first section of t i
chapter will be devoted t discussions of the various methods for extracting La in this study. o Another important subject that should be included in deepsubmicrometer study is the source/drain parasitic resistance Rm effect The voltage drop across Rm effectively reduces

-29supply voltages and degrades the current driving capability of scaled devicts. It was Claimed
one time that the parasitic
posed a limit in MOSFET scaling, but

w s prwen wrong a

recently. Previous results based on near-micron technologies tend to oveFtstimatc thc RSD effect in t e deepsubmicrometer regime. In d o n 3.4, experimental studies of the parasitic h resistance effect on deepsubmicrometer device characteristics and circuit performance axe presented. T i updated results of thc Rsr, effect can help judge the costlperfoxmance factor m hs MOSFET scaling and also provides some guidetines t technology developnents. o

3.1 Effective channel length (width) determination

Existing methods for determining MOSFET effective channel lengths can be divided into

two categories: the resistance approach [3.8-3.141 and the capacitance approach [3.15-3.171.
The basic theory behind the resistance approach is based on the IDS

- Vw relationship.

Depending on the extraction procedures. some methods are sensitive to the parasitic resistance variations between devices [3.9] and some arc sensitive t the I-V model used [3.10]. The o capacitance approach is based on the measurement of the net capacitance under the inversion-

o layer region. The capacitance approach is more accurate because it is insensitive t RSD and
does not require an I-V model. However, the accuracy of capacitance methods diminishes when the gate area is reduced as in small-geometry devices, because the stray capacitance is

o comparable t the gate capacitance unless high resolution instruments are used. Most of these methods have been demonstrated on devices with channel length longer than 1 p,but no
study has been reported about their validity in the deepsubmicrometer regime. In this section,
two resistance methods and one capacitance method are examined and compared.

(A)Channel-resistance method
The channel-resistance method (3.8.3.91 is the m s commonly used method in determinot

ing Ld because of its simplicity and its ability to separate Rm from the intrinsic channel resis-

tance. The principle of this method is briefly described below. When an MOSFET is biased

in the linear region with a small drain voltage (e.g. O.lV), the intrinsic channel redstance, &, is given by
(3.1)

w e e p is the d e r mobility, W = Whm AW,and hr ,

The measured device nsistaace I ? , -

-AL

is equal t o

Therefore, plotting R-,

'

against Lrn set of transistors wt the same Wa and same for a ih

VGs-Vtb results i a straight line, assuming p is not channel length dependent. The slope of n the line is inversely proportional t Va-V,. o

Al the lines with different Va-V, l

values

wl intersect at the same point as shown in Fig. 3.1. The x- and y-coordinate of the intersecil
tion give AL and RsD, respectively. T e accuracy of this method relies on the assumption t a h ht

RSD is the same for all devices w t the same channel width. In reality, RSD values may vary ih
slightly between devices either due to process aon-uniformity or introduced by Contacting probes during measurement, but this assumption is still good as long as the RSD variation is
small compared to

RQ. Therefore, when applying this method to the deepsubmicrometer

Egime, special care should be taken in probing devices (on-wafer measurements) or using devices wt small channel widths. Running the device under high c u m t levels for a couple of ih

seconds before taking data usually can minimize RSD variations. Since & is a function of
Va-V,, the linearity of these straight lines, which determines the quality of the intersection value

point (how close these lines i t r e t , is also highly dependent on the same Va-V, nesc)

o , for every device. T minimize the effect of the uncertainty in V between devices, the
minimum applied gate voltage should be 0.W to 1V higher than V . ,

When all these con-

siderations are taken cares of, this method can be extended to extract & down to 0 . 2 or ~ smaller as illustrated in Fig. 3.1.

w . 3

-31-

1500 1200

900
600
300
0 0.0

15v
2v 2sv 3v

03 .2

0.64

0.96

1.28

1.6

Drawn Channel Length (elm)

0.4

0.44

0.48

0.52

0.56

0.6

DrawnChannelLRngth (pm)

(a) M a u e channel resistance versus drawn channel length for various gate esrd
voltages, (b) enlarged area near the intersection.

Qlap.3

-32-

As for the channel width determinaticm, a s m l r channel-rtsistanoe rpproach does not iia work well as was pointed out by Ma [3.18], b e c a u s e Rm varies with thc channtl width. However, it should be noted t a the reciprocal of the slopes Gi (= pC=W&a-Vd) ht of the lines Thenfon, AW

in Fig. 3.1 are linearly dependent on the channel width b r a given, V

-, V

can still be extracted by plotting G as a functionof, i ,W

as illustrated inFig. 32. .Each line

in Fig. 3 2 corresponds t a particular Va-V,,, value and the x-intercept gives AW. Because o
of the bird's beak at the edge of the active region, the, effecdve channel width i i general 8 s n function of the gate voltage. This result is reflect by the different intercepts for differart

VGS-V,,, values in Fig. 3.2. Since AW for each VOScan be obtained, the gate-voltage dependence of AW can also be obtained. The functional form of AW depends on the isolation technology used. The insen in Fig. 3.2 shows the extracted AW

- Vm-V,

result for a LOCOS

process.

z
m
X

= l

V,-V,(V)

//

-1

1 1

Drawn Channel Width ( ) p

Fig. 3.2 Intxinsic channel conductivity (the reciprocal of the slopes in Fig. 3.1) versus

drawn channel width. The insert shows the extracted AW as a function of

v, , v

chap.3
(B) Medified SUC~U'S method

-33-

Unlike the channel-nsistance method, this method is insensitive to the p a d t i c resistance

of individual device, but an I-V model is nquind. The accwacy of this method is affected by

t e I-V model used. Since the mobiity model used in the original method proposed by Such h
(3.101 is too crude t be applied to deepsubmicrometer devices that typically have o

thin gate

oxides, an improved I-V model is used. The basic theory of this modified method is d e s c n i

blw eo.
The drain current of a MOSFET with R s effect included can be expressed as ~

where

(3.6)
Rs is Le parasitic resistance on the source sL. an(

- are coefficients of the mobility

is small, Eq. (3.3) can be

reduction due to vertical field. Note that the Ub t r in (3.3) is the modified mobility t r . em em The meanings of U and U, are explained in chapter 5. When V, , simplified and re-arranged as

Va= 1
where VG,= V a V , . R s ~ + u & ,and
ub

-+(Rs* +-)Va+ u .
Bo Bo

-va 2 U b
Bo

(3.7)

S n e (3.7) has the form of "y = a + b x + c x2", the coefficients ic

for each device can be extracted by fitting (3.7) through a kast-squafe fit is propor-

routine. This fitting procedure is similar t that shown in section 5.4.3. Since o

tional to Wd/La, AL, can be obtained from the x-intercept in the plot of l& versus Ldnm for

fixed channel width as shown in Fig. 3.3. Similarly,

AW can be obtained from Bo versus

Qlap.3

-34-

,W ,

plots, but AW's extracted from this method represtnts m "8vcraged" value that does
~ r gate-voltage * & . y I=
VCISUS

mt show

when rll
I&

ut ~xtracttd,Rm

ud U an be ,
o l l ~identical

obtained by plo#ing RsD+U&

The devi-

uscd in Fig. 3.3

those used in Fig. 3.1. The ALb derived f o both methods an very similar. rm

0.0

0.32

0.64

0.96

1.28

1.6

Drawn Channel Lcngth (pm)

Fig. 3.3

Reciprocal of the channel conductance versus drawn channel length

Qlap.3

-35-

(C) Capacitance method

For longer channel devices, the capacitinct method is the most accurate method among
all methods, but the measurement instruments Fequired an not widely available in typical
automated characterization systems. Finthennore, the parasitic resistance can not be extracted.

Therefore, the capacitance method is a good means t justiQ t e accuracy of a resistance o h

method and is often used when high accuracy in

is r e q u i d In this study, t e capacitance h

method is also used to confirm the nsults of the two resistance methods. A schematic diagram

of the capacitance method is shown in Fig. 3.4. The device is first biased in the accumulation
region and the sourcedrain to gate capacitance, C8&,is measured. This capacitance (indicated by C1 in Fig. 3.4) is composed of the overlap capacitance and any stray capacitance of the system. Then, the device is driven into the stronginversion region and C1h is measured again (indicated by Q. C2 is larger than C1 by C,(W,,-AW)
(Ldnwn-AL). plotting the By

difference between C1 and C, against bnwn or Whm, AL and AW can be extracted from the x-intercept as shown in Fig. 3.5, where t e same devices in Wg. 3.1 and 3.3 are used again. h Generally speaking, the resistance methods require simpler equipment and work better for narrower channel width and thicker gate oxide devices and the capacitance method works better for wider channel width and thinner gate oxide devices. These two types of methods

serve as complementary to each other. If can is taken, all three methods discussed here can
be applied to the deepsubmicrometer regime and the extracted AL's agree within 0.01p. In
this study, most of the effective channel lengths were simultaneously determined by the two
resistance methods and were frequently checked by the capacitance method to ensure high

accuracy and high confidence.

-36-

BSUB

Gate Voltage

Fig. 3.4

(a) A schematic diagram of the measurement setup for the capacitance method
(b) measurcd C@ versus gate voltage.

0 . 3

-37-

52

39

-26

13

0
0.0

0.32

0.64

0.96

1.28

1.6

Drawn Channel Length

Measwed net channel capacitance versus drawn channel length.

32 Short-channel effect .
The short-channel effect is one of the major c o ~ m MOSFET scaling, because devin

ice parameter variations caused by the shortchannel effect poses difficultyin both process control and circuit design. In this section, two most short-channel-sensitive parameters, threshold voltage and subthreshold swing, art examined.
32.1 Threshold voltage

Threshold voltage shift A , due to source/drain charge sharing and drain-induced-Wr V lowering (DIBL) is the most commonly observed shortchannel effect in MOSFETs and has

been widely used as an indicator for measuring the extent of the shortchannel effect for a

chap3

-38-

given technology. Therefore, a compreherrsive study of the short-channel effect on threshold voltage is a ntcessary step t optimal device designs. However, a complete chrvacterization of o

the thxeshold voltage over 8 wide range of technologies rtquireS a huge amount of devices and
measurements. Various threshold voltage models were developed t supplcmaU this study in o predicting f

u technologies and an used in circuit simulations. ~

Three approaches have been generally adopted in modeling the short-channel thnsbold
voltage, namely, the charge partitioning (3.193.20], numerical analysis (3.211, and the 2-D

analytical approach [3.22-3.251. Recently, threshold voltage models derived from 2-D analytical solutions of Poisson's equation in the depletion ngion have become more favorable since AVh expressions obtained from this approach show an exponential dependence on

which

agrees better with experimental results. However, because of the different appmximations used

for the boundary conditions in deriving the models, the model parameter values vary from
paper to paper. U u l y parameter values can only be obtained from characterization of physisal
cal devices. Furthermore, these simple exponential V,,, models fail to explain the accelerated

V,,, reduction at shorter channel lengths and tend to underestimate the short-channel e f f a

In this section, a short-channel threshold voltage model is derived based on a quasi twodimensional approach, which has been successfully applied to model the MOSFET substrate current and other hotelectron phenomena (3.26-3.281. When the device channel length is much longer than the characteristic length (defined later), this model agrees in functional form
with those i [3.22-3.251. At shorter c h m l lengths, this model predicts a faster increast i n n

AV, and art more accurate than other models.

(A)the model
Applying Gauss's law t a rectangular box of height X+ and length Ay in the depletion o region as illustrated in Fig. 3 6 . E . ( . ) can be derived [3.26-3.281. .a q 38

-39-

&\
v .

ry

""Ai""'

OS

ov
long-channel

....... .....
~

E .36 g .

(a) AMOSmcross d o n showiqg the depletion region and the Gaussian box. The depletion region is assumedto beunifom cross the &d. @)The energy diagram o the surface potential -the f sauccto the drain forboth a longdamel and a short&vice.

where r6,is the depletion layer thickness equal to

0s is the surface potential at which the threshold voltage is defined, and E,&), V,Q) arc the
lateral electric field and the channel potential at the Si-Si% interface, nspactively: The fixst

term on the left-hand side of (3.8) is equal t the lateat ekctric field in the channel, EJx,y), o
htepted over the vertical dde of the box

(see Rg.3.6a). The non-uniform distribution of

E,,(x,y) along the xdirection is taken into account by a fitting parameter r\ [3.27). The second term is equal to the vertical electric field at position y on the top side of the box and the term on t e right-hand side of (3.8) is equal to the depletion charge density in the box. The solution h
to (3.8) under the boundary conditions: V ( ) = Vs a the source and ,O t

V ( ) = VDs+Vbi the ,L at

drain, is given by (3.10)

where D = VGS-VM+OS, Vw .is the textbook long-channel threshold voltage given by

VFB+@S+qNSUBX~Coa, is the built-in potential between t soureldrain junction and Vbi h the substrate, and I is the characteristic length defined as (3.11)

q has an empirical value between'O5and 1.5 depending on the device structure and process
technology. For most technologies, L >> 1 and (3.10) can be approximated as
V,Q) =D +( , V

+Vm -Dk-''~fl +(Vb-D 7 k'

(3.12)

T e channel potential V,(y) has a minimum az h

(3.13)

and the minimum channel potential V* ,

is given by

chap3

-41-

The channel potentials for a long- and a short-channel device for a given gate and drain vol-

h tages an plotted in Fig. 3.6b. As the channel length is reduced, t e minimum channel potential decreases as shown in Fig. 3.6b. when the minimum channel potential is equal to OS, the corresponding gate voltage, which is de6ned as the threshold voltage V,(L) can be calculated

where R = V b - 4 ~ . For Vm << R, Eq. (3.15) reduces to

When L > 51, the second exponential tern in (3.16) can be neglected and (3.16) reduces to a

form similar to those given in [3.22,3.23]. For very short channel lengths, the accelerated Vb
reduction can be explained by t e second exponential tern in (3.16). h
(B) experimental results

Fig. 3.7 shows threshold voltage versus effcctive channel length at several drain and sub-

esrd strate biases. The symbols are m a u e data and the curves

= the model. In general, dev-

ices w t thicker gate oxide and high substrate bias exhibit more threshold reduction due to ih
larger characteristic length 1 according to (3.11). The accelerated V, reduction phenomenon at
shorter chaMel length can be observed i Fig. 3.8 where AVth is plotted against La in logan

rithmic scale. N t that the measured data deviates f o the simple exponential expression oe rm when

is smaller than about 51 which translates t AV* = 0.W. Since most AVb data are o

taken around O.lV, this slope-increasing behavior at shorter channel length is important in accurately modeling V,. Without taking i t account this accelerated V, reduction at shorter no

channel length, it would lead t an underestimation of the shonchannel effect or result in o

incorrect extraction of 1.

42-

05

0.0

0.0

A .

1 3 1s ' u Ellcctive Channel Length Qm)

Fig. 3.7

'Ihreshdd vdtalge versus dTective channel length ab various drain md substrade biases for scpefal techndogies. The symbols are measured data and the ms c
arcthemodel.

43

10

P
0

F b
e

I
0.1

1 F

0.01

0.001 0.0
Effectlve Channel Length

w)

Fig. 3 8

'Ihresbdd vdtage reduction (V,)versus effective channel leagth i loge A,, n xithmic d e . At short channel leogths AV* deviates from the simple cxpona~ tial function (LS seen by the superlinear behavior. 'Ibe symbds am measured data and the curves are the m>dd.

w . 3

44-

Although I calculated from (3.11) has the comct order of magnitude, exact values of 1

Ilccd to be charaaerized from physical devices because of the unknown paramaer q.

Extracted I versus the depletion layer thickness for several Werent technalogies uc shown m Fig. 3.9. Thc d S e m Xdcps Fig. 3.9 for a given technotogy corresponding to different in

substrate biases. These straight Lines with s m l r slopes suggests that 1 is proportional to iia
relatively independent of technologies. Both this model and those from 2-D analysis indicate that the sourcddrain charge-sharing and the DIBL effects are basically caused by the same mechanism,namely the channel potenrial lowering, however, these two effects are usually distinguished for easy explanation. The

h source/drain charge-sharing usually refers to t e AVh measured at low drain voltage while

V DIBL refers to the A , induced by the drain voltage only. Fig. 3.10 plots V b versus Vm for
various channel lengths to show the DIBL effect. In other models the DIBL effect is usually

o ,, approximated by a linear function of VDs, but the linear model fails t explain the faster V,
miuction at low VDS as shown in Fig. 3.10. T i phenomenon was also observed in (3.23hs

,, 325.3.291. But this non-linear V, Vm behavior can still be predicted by this model as
shown by the solid m e s in Fig. 3.10. At large Vm,this model approaches to a linear function of VDs, while at low Vm it approximately n d u c a to a square-root function according to (3.16).

Masuda [3.29] found empirically that, for longer channel lengths, the measured V, Vm ,,
curves all intercept at the same point, but not for shorter channel lengths. This observation can

also be qualitatively explained by this model if we draw straight lines to best fit the culycs in
Fig. 3.10 as illustrated by the dashed lines. For longer channel lengths, the V ,

- VDs curves
-, V
ms c

can be well approximated by straight lines and the x-intercept of these asymptotes can be
derived from (3.15) But for for smaller channel lengths, a large portion of the V ,

are not straight. Therefore, tryins to draw lines to best fit t e a w e s (or data) for short chanh

nel lengths would result in l i e s steeper than their asymptotes.

chap3

45-

The same approach can also be applied t LDD structures, but the boundary COnditiOIls o

should be modified to be suitable for the n-4 junctions. Since the built-in potendal of an n-h

junction is smaller than that of an n'h, LDD devices generally show less V shWt than m,
LDD devices. The voltage drop am t n region also decreases t effective drain voltage c k ' h
applied to the channel and reduces the DIBL e

Kg. 3 9

Measured cbara%edstic length versus depletion layer thichess for &exeat technologies.

w . 3

'

3.

Drain Voltage (V)

l3g. 3.10

h h o l d voltage ve~susdrain voltage. 'Ihe symbols am meLLsurcd Anta the sdid curves me the model, and the dashed l n s are the best Linear fit t the ie o
CuIyCs.

'

47-

"1
1 s

V,=O.lV

rn
110

100

90

8 m

vm = 3 v

36-

H .3.11 g

(a) , V

Subthreshold swing versus effective channel length for four oxi& thiclmessts. O.lV, (b) Vm 3V.

0 . 3

48-

32.2 Subthreshold swing

The increase of subthnshold swing, S,a shorter channel lengths I3.301 is another factor t
causing shortJlanne1 devices to be more difficult t turn off. Therefore, the subtluesbld o swing also serves as an altcmative way to m n t r the extent of short-channcl effects. 'Ibe oio subthreshold swing versus

for this process at a low and Ihigh drain voltage ut shown i n

Fig. 3.11a and 3.llb, nspectively. U l k the threshold voltage, s u m l d swing is fairly nie
constant even when

A , ,starts t show up, but suddeply increases to a large value when the V, o

device is near punchthrough. Also, the s u m l d swing is less sensitive to the drain voltage
than V,. Theoretical value of the subthreshold swing is given by
[3.17]

where CD is the depletion-layer capacitance. The subthreshold swing decreases as the gate oxide thickness is reduced as predicted by (3.17). For thin gate oxides, higher channel doping concentrations are required t maintain a 0.65V threshold voltage which also o
inclrcases C,

This explain why the longchannel subthreshold swings for 3.6nm and 5.6m gate oxide devices are very close.

3.3 Current driving capability

The improved current drive of short channel devices i one of the motivations for MOSs

FET scaling. Because of the d e r velocity saturation effect, draii saturation current increases
only s u b l i i l y with l/r, in the submicrometer regime but the design and fabrication overheads increase drastically with ducing the channel length. Therefore, a quantitative study of the current driving capability of deepsubmicrometer devices is another important procedure in optimal device designs. When the channel length is smaller than 0 . 2 and the power supply ~

is not proportionally scaled (3V or higher), the velocity saturation region extends into a s b u
stantial fraction of

the channel and a considerable portion of electrons in the velocity saturation

chap.3

4%

q i o n move with a velocity higher than the SatuzBtion velocity Y ,

It was claimed that the

current driving capability of deepsubmicrometer devices would be enhanced by this velocity-

o overshoot effect [3.31,3.32]. A straight forward way t examine whether the current driving
capability of deepsubmicromem devices is enhanced or affected by new carrier transport mechanisms is t compare experimental data with existing physical models. Tbc drain cwmt o model used here was developed by KO [3.33], improved by Toh [3.34], and has been success-

futly applied t devices with channel length longer than 1p.m. Some of the model equations o

are listed below.

(3.18)
and

(3.19)
where g

is the saturation transconductance,

(3.20)

E,= 2v, k

(3.21)

and & is the effective vertical field in the channel that can be approximated by

(3.23)

QB is the depletion bulk charge, I = 0.67MV/an, n = 1.6, p = 670cm2/V & ,

8~lO'~cm/sec.

stc, and v,

The measured drain saturation current INAT, saturation transconductance , g

and t e h

model for an array of devices with channel length down to 0 . 1 S p are shown in Fig. 3.12.

The same model parameters wen used f r all device dimensions and oxide thicknesses. The o

symbols in Fig. 3.12 are measured data and the solid curves arc the model. The data shown m

Fig. 3.12 have been comcted b the sourWdrain parasitic &stance r

(=uM/side). A

comprehensive study of the souWdrain parasitic resistance effect on device performance is given in the next section. The inversion-layer capacitance effect [3.35], which i mon impors tant for thin-oxide devices at low gate bias, w s also not included in these equations. a
The well-behaved trends of
and

and.-

good agreement between measured

data and the model indicate that the basic physics of deepsubmicrometer devices is rather wl el undemood. Although Monte Carlo simulations show the existence of velocity overshoot in the velocity saturation region, it has little effect on the MOSFET current driving capability, at least
d- .el length. This observation also coincides with the conclusion of another down to 0 . 1 5 ~

independent study L3.363, which used an improved mobility model (extended driftdiffusion model) to simulate the velocity overshoot effect in the velocity saturation region. According to their simulations, the velocity overshoot effect is of little importance to the MOSFET curcnt driving capability for devices with channel length longer than 0 . 0 6 ~ . Since the basic physics in deep-submicmmeter devices is essentially unchanged, the basic framework of most existing drain current models can be kept without major modifications.

hs The drain current model used in t i section, while simplistic in formulation, still provides
good physical as well as quantitative understanding of the current performance of

MOS devicts

down to the deepsubmicrometer regime and can serve as a means for process conml and diagnosis.

-5 1-

.1

9 3 .4 S .

.6

.7

d J

1 1.1 1 1 13 14 .

Effective Channel Length 1pm-1

Fig. 3 1 .2

o n currtnt d Va-V, versus effective c h d length for v ~ o u s oxide thicknesses, (b) meawed transcoaductance v ~ f l u effective channel length. 'Ihe data have been corre&xi, t the first orda, for o the pamitic Ilshmce &at
(a) Measured drain d

32-

3.4 Sourcddrain parasitic resistance effect

lhe parasitic sourcddrain resistance is one of the device parameters mat can not be proportionally scaled. As MOSFET channel lengrhs are scaled down to the deepsubmicrometcr regime, device performance reduction due to parasitic source/drain resistance (RJ bccomts an important factor to consider in MOSFET scaling r3.37-3.401. A quantitative study of & effects is essential, since it can provide guidelines for both MOSFJT scaling and contact technology development. It was claimed that as the device channel length is scaled below 0.5 pm, the cumnt drive and transconductance starts to decrease rather than increase with the reduction of the channel length [3.38] implying that the parasitic resistance poses a limit on MOSFET scalability. But

this statement has been shown to be incornct because of the recent improvements in device
technology. Previous reports [3.37-3.391 on this subject, based on near-micron technologies,
also may not be applicable to the deepsubmicrometer regime.

M r mently, Ng and Lynch oe

[3.40], using computer simulations, studied the R,,, effects in the deepsubmicrometer regime

but with only little experimental results. In this section, experimental studies of the R,,, effects on deepsubmicrometer n-channel non-LDD MOSFETs is presented. Thc reduction in drain currents and ring oscillator speed for various channel lengths and & values is examined. n# effect of salicide technologies on device performance is also discussed and projections of the ultimate achievable device performance are givm
3.4.1 Experimental procedure

Intrinsic Device Performance Measurement Procedure: In order t determine the o amount of performance reduction due t o

b* following calibration procedure the

w s pera

formed. me drain cuknt in tht linear ID^) and saturation (IDSAT) regions and the maximum
J ,, saturation transconductance @

were measured. In Fig. 3.13 the measured I

~ is T plotted

against RSD; different RSD values were achieved by attaching external resistors (%3, equdy

chap.3

-53-

divided between the source and drain, to tach device, Le. Rm = Rsw

+ &.

The circles indi-

cate meaSund data. Tbc solid lines represent the simple physical drain current modcl
described in section 33 A calibration constant (in the range between 1 0 to 11 for all dev.. . . ices) is multiplied to the model t best fit the measured data for each channel length. T obtain o o higher accuracy, parasitic resistance effects were included in the drain current model through iteration; parasitic resistance-induced body effect, which was neglected in (3.401, was also included in the calculation. The theoretical drain cunyts at RSD = 0 are taken as the inuinsic current ( ID,^ and
I ~ A ). The T ~

percent drain c u m t reduction from the intrinsic value as a

function of RSD is given by the alternated curves.

3.4.2 Experimental results

(A) Saturation region: Fig. 3 1 shows IDSAT versus .4

& for a power supply of 3.3V.

The symbols indicate measured data; the curves are the calculated intrinsic (RSD= 0) drain current obtained in the manner shown in Fig. 3.13 and the corresponding current derating,
Idu,/Iw

Because of the slightly different parasitic resistance between wafers, RSD values

were adjusted to be about 600Rpm for a l oxide thickmsses using external resistors. S m l r l iia

results were also obtained for the transconductance We observed that the current (transconductance) derating decreases as La and/or T, decreases because the debiasing (source follower) effect of
RSD

is stronger as IDS (,, g J

increases. However, the derating is still about

87% even at & = 0.2pm, if & is kept at 6OORpn.

(B) Linear region: Fig. 3.15 shows IDm versus Ld at

VDS = 0.1V and VGS = 3.3V.

The drain current derating in t e linear region is significantly lower than that in the saturation h

& region. The derating can be as low as 50% at L = 0 . 2 ~ .This is because in the linear
region & reduces the current through both the effective VGs and , V region it only reduces the current through the effective, .V while in the saturation

Also, the current derating is less

sensitive t TOx o than in the saturation region. T i is because IDm less sensitive t T, due hs is o to the transverse-field-induced mobility reduction than IDSAT, which is mainly determined by

hq3.3

-54-

d e r saturation velocity that is insensitive t the transverse field. o

800

TOx 8.6nm =

Leff = 0.3pm .. ,

*z 200

Ei

0
0.0
1Ooo.o

2000.0

30. 000

4OOO.O

Parasitic resistance (Rpm)

Fig. 3 1 .3

Drain saturation current versus parasitic resistance. The circles axe d data and the sdid m e are the results of the calibrated model. Ihe dashed h e s indicate the percentage drain curreat reduction.

-5s-

Tox

Data Model 0 ........... 5.6nm

1200

8.6nm 15.6nm

lo00

800

600

400

200

vcs = 3.3v VDS = 3.3v

0 0.0
I

0.2

0.4

0.6

0.8

1.o

1.2

1.4

Effective channel length (pm)

Fig. 3.14(a)
Drain saturation ament and the &rating versus dective channel leagth. 'Ihe symbols are m a u e drain CuITent and the curves 81t thek corresponding esrd intrinsic values md d e d n g s .

\ \\

Tox= 15.6~1

0.0

0.2

0.4

0.6

0.8

1.o

1.2

1.4

Effective channel length (pm)

Fig. 3.14(b)

Saturation transconductEncc and the derating versus effective channd length. 'Ihe symbols a -dataandthe n cwves are their corresponding inlxjnsic

-57-

Tox

Data
0 0

5.6m
200

8.6~1

15.6nm

150

100

50

0
0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

Effective channel length (pm)

Fig. 3.15

Linear region drab curzent and the derading vems effective channel length. Ihe symbols are measured data d t h e cwes are their c o m q o d q intrinsic values and derapings.

chaP.3

-58-

(C)Switching Speed: Depending on the circuit configuration, the circuit speed derating
should lie between the derating O f I D m and I A shorn in Fig. 3.14 and Fig. 3.15. Fig. 3.16 mT shows SPICE simulated delay time
(7) per

stage of CMOS ring oscillators versus RsD for T -

= 8.6nm. The widths of the n- and pchannel devices are 15pn and 30p. resptctively. The
loading capacitance is 0.1pF on each stage. T e simulation d t s show that h
7

increases

mughly as a linear funaion of Q with a slope about 10 4 % per kQun for T between 0 ,

5.6m and 15.6nm, and La between 0.25pn and 1Jp. At 600 R p and for T, = 8.6mn,

t e speed derating is about 60% for & = 0 . 2 and 85%for L,tr = 1 p . Om m s conclude h ~ ut
that the speed derating is closer to the ID^ derating than the I ~ A derating. This conclusion T

rm differs f o that drawn in (3.401.

3.43 Discussion
R ~ D usually divided i t four components, namely, the contact (RJ, is no
sheet &,), the spreading

the diffusion

w,and the accumulation &)

resistances as shown in Fig. 3.17

[3.40]. In this study, there is a polysilicon film between A and Si, and RSD is typically 500 l
600

R p . The contact-to-gate spacing i about 0.7 pm. With Similar contact-to-gate spacing, s

an RSD value of 300Rpm (%, = 100, & = 50, R1p + & = 150) can be achieved with conventional contact technologies [3.40]. This R ~ value corresponds t 95% IDSATderating, 79% D o

IDLPJ derating, and 85% speed derating for

& = 0 . 3 and Ta = 8.6m (see Fig. 3.18). ~

Because of the hot-canier effects, LDD sv~cturewill likely be used in scaled MOSFETs and
could introduce an additional 100 400 R p n of & depending on the device design and bias condition [3.41]. This LDD resistance would further derate I ~ A by about 2-59, I b by 9T
179, and the speed by 5-159. Fmally, the maximum benefit of employing a salicide technol-

ogy can be estimated by assuming that t e salicide technology totally eliminates R and RSD. h , ,
This would increase IDSAT,

ID^ and the speed by about 2.5%. 12% and 7.5 for both the LDD

and non-LDD devices.

-59-

TOx 8.6nrn = C = 0.1pF ,

wN --

15pm Wp - 30pm

1.Opm

0.7pm

0.0

1000.0

2000.0

30. 000

4000.0

5000.0

Parasitic resistance (Qpm)

Fig. 3.16

SPICE s b l a t d d seveaal channel l e .

riag oscillator delay timc versus parasitic resistance for

Fig. 3.17

A schematic diagran showing

tmce.
100

the various components o the parasitic nsisf

#)

e.- r u

a
0.0 100.0

m0 .

#w10

400 0.

m0 .

600.0

R (Rpm) ,

+ non-sallcided non-LDD +
+ saliclded non-LDD -w
+ non-sallcided LDD +

+ salclded LDD+
Fig. 3.18

Deraeing versus parasitic nxistance. The projected parasitic resistance effect 00 vadous ~ O g i e areiodicatbd s

chaP.3

-61-

3.5 Hot-electron effects

It is well known that the h o t c l m n induced device degradation poses Circuit dhbility problems. Therefore, device degradation is the m s discussed topic among all hot-clcctm ot effects. Because of the extremely high electric 6led in the channel due t the unscaled power o supply, hotelectron effects arc more severe in deepsubmicrometer devices and have gained more attention than ever in MOS scaling. In this section, the substrate m n t and the device lifetime are discussed.
35.1 Substrate current

When camers pass through the velocity saturation region, electron-hole pairs are generated by impact ionization. The holes are collected by the substrate and constitutes the substrate current Ism. Since many hot-electron phenomena, including device degradation, have close comlations with Ism, the substrate current is widely used to monitor the hot-electron effects. In Section 3.3, we have shown that the basic physics of deepsubmicrometer devices is unchanged. In this section, this statement will be demonstrated again fn#n the hot-electron point of view. A commonly used substrate current model (3.421 in the literature is used for

this purpose. The model equations are summarized below.

(3.24)
where

o+ and pi are impact ionization coefficients whose typical values are 2E6cm-l and 1.7E7V/cm,
respectively (1E7cm-' and 3.7E6V/cm for PMOS). For long channel and thick gate oxide dev-

ices, an empirical expression for 1 has been observed l3.43.3.441.

I =o.22T2xjlJ3

(3.26)

0 . 3

-62-

10-81 0

Effective Channel'kngth ~m 1.

os m

1m

1.5

Fig. 3 1 .9

Peak substrate current veasus

oxide thiclmesses.

effective c h d

length rt , V

- 3V

for four

.
2

.
3 '

.
4

.
S
6 .

F .320 q

Substrade m n t charaderistics for different c W lengths. As &e c h d length decreases,the gate voltage mtrol w d the substrate ament reduces. e

chap.3

Gate

3
Velocity -Saturated Region

Drain

Short Channel

Qn

Thin Oxide hallow Junction Long Channel

eep Junction

Q Thick Oxide ,

/
I
1
LD

c -

E = E d + AE ,

Effective Lateral Electric Field Length Effective Non-Overlap Length

Schematic diagram showiag thc cuaeat-cmding bdxxd weak gade contrd effect 13.481. (a) cross section of a MOS transistor, @) mobile charge density as a function of the channd position, (c) the e l e d c fidd 85 a fuoctim of the channd positioa

Rg. 321

when Taaand Xj arc in centimeters.

The peak substrate c u m versus effective channel length at V B = 3V for several oxide

n i. thicknesses is shown i F g 3.19. 'Ihe substrate cuncnt peak is higher for a device with
shorter channel length and thinner gate oxide as predicted by (3.24H3.26). Fig. 3.20 shows

I m

- VGS characteristics for T , ,

> I.-),

= 8.6nm at various channel lengths. At longer channel

lengths

the shape of the Ism characteristics can be modeled. However, as the

channel length is reduced, the substrate current becomes less sensitive to the gate voltage that
can not be explained by the model

to Several modifications [3.45-3.47) the Ism model have been proposed to describe the deviation of measured Ism from the simple theory. These modifications are usually implemented by making the impact ionization coefficients functions of applied voltages through some empirical expressions. The physical basis for them is the non-local impact ionization effect and the non-equilibrium conditions in the high-field region near the drain. Another proposal is the s o d e d "cunent-cmwding induced weak gate control" 1 . 8 34) which can be schematically explained in Fig. 3 2 , where the cross section and the doping .1

ml, profile of the drain of a MOSFET are shown. When the drain current is s a l as in long and
thick gate oxide devices, the mobile charge density required to cany the drain current in the
velocity saturation region is negligible compared to the drain doping concentration. Therefore, the boundary of the velocity saturation region is very close to the edge of the drain junction The peak channel elecuic field is inside the velocity saturation region and can be approximated

32) h by ( . 4 . For shortchannel and thin gate oxide devices, the drain current is large and t e
mobile charge density in the velocity saturation region is comparable to the doping concentration of the drain region. Therefore, the velocity saturation region extends into the drain and

the peak channel electric field also occurs inside the drain. As a result of the extra depletion
region in the drain, the peak electric field is higher than that given in ( . 4 by AE. 32)
LD qlDS AE=-(--ND) ~d Xjvm

(3.27)

Qlap.3

-66-

where ND is the average drain doping concentratiai,

is the length of the weak gate-

controued ngion. The magnihde of Lo d e w on the drain struchm, usually in the range of
0

- 10nm.

Detailed description of h i s cumntcrowding induced weak gatecontrol cau be

found in r3.48).

More informative figurcs of 1s-

an ISV$IM vcrsus l/(VB-VmT) plots as shown i n

Fig. 3.22. The straight lines in Fig. 322 suggests that the basic physical mechanism for'hotelectron effects still pnvail in deepsubmicrometer devices. According t the hot-eltctron o

i. model, the slopes of the lines (= I) in F g 3.22 an independent of the channel length and
have a one-third power dependence on gate oxide thickness. However, it is found that when
the effective channel length is smaller than about 0.5p.the slope (1) decreases w t L a (see ih

Fig.3.22a). We suspect this channel length dependence of 1 have to do with the encroachment

of the linear region into the velocity saturation region as tht channel length decnascs. It is
also found that, when the gate oxide thickness is smaller than about l S m , 1 is very weakly

T dependent on , (see Fig. 3.22b). One explanation to this weak gate oxide dependence of I is
the finite depth of the current path in the velocity saturation region. In deriving (3.21)-(3.23),
it is assumed that the impact ionization occurs at the Si-Si02 interface. In the velocity saturation region, the actual drain current path, and thereby the peak impact ionization, is at about IO-3Onm below the interface. Therefore, an effective gate oxide thickness Tk. which consists

of T and the cunent depth should be used in (3.23). When the gate oxide thickness is com,
parable to or smaller than the cumnt deph, Tk is limited by the current depth and I becomes
a weaker function of . , T

An empirical e x p s i o n for 1 is determined t be o

I =1.7~10-T mXjm m 2,
where all quantities have the units of cm.

for Ldfi<OJp and T,c lSnm

(3.28)

-67-

Fig. 322(a)

log(lsv$r,) versus lWm--VmT) plots for & 03pm and four oxide thicknesses. 'Ihe slopes o these lines are ploportional t the impad ionization f o
coefficient.

-68-

-2.0
n
. I

ToX BSA =

c n

CI

-3.0

>" I

4.0

> e e .n
\

ij
a
a

-5.0

v) L I
d

LI

cb 0

4.0

-7.0

Fq.3 2 ( b )

log(Isu$lrs) vusus w m - V ~ T plots for , = 8511mand several channd ) T lengths. "he slopes of these lints arc pmpoxtiond t the ;mpact ionization o
CotffiCialL

Qlap-3

-69-

35.2 Device lifetime

A detrimental effect of the high channel elcuric deld is t injection of cneqctic eleck

trons i t the Si-Si% interface that generates interface traps and results in device degradation no
[3.49,350]. How to reduce hot-electron device degradation has been the goal of many hot-

electron studies. A common quantity to measure the immunity of a device t the hotclectmn o effect is the device lifetime, which is usually defined as 3% (sometimes 10%) forward drain current change in the linear region afkr hot-elecuon stress t3.421. Previous studies on nearmicron devices showed that the device degradation is technology dependent and is relatively independent of the channel length under the same stress conditions (3.511. However, in the submicrometer regime, the effect of device degradation on the device performance is more prominent as indicated by the strong channel-length-dependentdevice lifetime shown in Fig.

3.23 t3.521. Similar results are also observed for other oxide thicknesses. This channel length
dependence of lifetime can be qualitatively explained in Fig. 3.24. If we assume that the hotelectron created damage (the dark region) is independent of the channel length for the same

* amount of stress ( I ~ B time = constant), then the ratio of the damaged interface area to the
total channel area increases as the channel length is reduced and the device lifetime decreases because the relative amount of degradation increases.
A useful variation of

Fig. 3.24 which provides direct device design guidelines is shown

o in Fig. 3.25, where the extrapolated maximum supply voltage t ensure a 10-year device lifetime for 8.6nm gate oxide is plotted against the channel length. As a result of shorter lifetimes, the maximum supply voltage is smaller for short channel devices. For a quarter-micron

device with 8.6m gate oxide, the maximum supply voltage is about 2.5V, suggesting t a ht

some kind of hot-elecmn-resistant structures arc

lowered to 3.3V.

still

needed even if the power supply is

-71-

Substrate

Long Channel

Substrate

Short Channel

-n-

s.5

25

-0

, I - - - - ' - - - - ' - - - - ' - - - -

Effective Channel Length [ Cm 1 c

.5

1.5

Maximum supply voltage t ensun a 10-year device lifetime vemu effective o channel length for 8.6nm gate oxide. "he devioe lifetime i defined s 3% ftm s ward drain aurrnt degraaatioa i the linearregioa n

-3

-73-

36 References .
W. Fichtncr, RK Watts, D.B. Fraser, R L Johnston, and S.M. Sze, "0.15 pan
--Length

MOSFEI'S Fabricated Using E B C ~ Lsthography," IEDM Tcch Dig.,

~p.272-725,1982. W. Fichtncr, EN. PI&, R.L. Johnston, RK. Watts, and W.W. Wcick, "Optimized
MOSFETs with Subquartexmicron Channel &@E,"

EDM Tech. Dig., pp.384-387,

1983.
T. Kobayashi, S. Horiguchi, and K Kiuchi, "DeepSubmicron MOSFET Characteris.

tics with 5nm Gate Oxide," IEDM Tech Dig., pp.414417, 1984.

S. Horiguchi, T. Kobayashi, M. Oda, and K. Kiuchi, "Extremely High Transconductance (Above SOOmS/mm) MOSFET with 2 . 5 ~ 1 Gate Oxide," IEDM tech Dig.,

pp.761-763, 1985.

S.Y.Chou, H.I. Smith,and D.A. Antoniadis, "SublOo-nm Channel-Length T a s s o s rnitr

Fabricated Using X-Ray Lithography," J. of Vacuum Science Tech. B, vol. 4, m. 1, pp.253-255, Jan/Feb 1986.

J. Chung, M.-C. Jeng, J E Moon, A.T. Wu, T Y Chan, P.K. KO,and C. Hu, "Deep .. ..
Submicrometer MOS Devict Fabrication Using a Photoresist-Ashing Technique," IEEE Electron Device Letters,vol. 9, no. 4, pp.186-188, April, 1988. G.A. Sai-Halasz, M R Wordeman, D.P. Kern, E Ganin, S. Rishton, D S Zicherman, .. . ..

.. H. Schmid, M R Pol&,

H Y Ng, P.J. Restte, T.H.P. Chang, and R.H. Dennard, ..

"Design and Experimental Technology for 0.1 pm Gate-Length Low-Temperature

Operation FET's," IEEE Electron Device Lettcrs, voL EDL-8, no. 10, W, 1987.
K. Terada and H. Muta, "A New Method t Determine Effective MOSFET channel o
Length," Japanese J. Applied Phys., vol. 18, no. 5, pp.953-959, May, 1979. J.G.J. Chem, P. Vhang, RE M o a and N. Godinho, "A New Method to Detemim

cm.3

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MOSFET Qlanncl Length" IEEE Electron Device Laters, VOL EDL-1, no. 9, pp.170173, Sep., 1980. [3.10] P.I. Suds and R L J ~ h t ~"EXperim~~A t~a Derivltioa of the Source md Drain Rtsistan= of MOS Transistom."

IEEE Tan. on Eaectron Devices, voL -27,

m. 9,

p.1846, Sep., 1980. (3.111 K L Peng and M.A. Afromowitz, "An Improved M t o to Determine MOSFET Chanehd

nel Length," IEEE Electron Device Letters, vot' -3,

no. 12, p.360, Dec., 1982.

[3.12] K L Peng, S.-Y. h M.A. Afrornowitz, and J.L. M l ,"Basic Parameter Measurement .. O, ol
and Channel Broadening Effect in the Submicmmetcr MOSFET," EEE Electron Dev-

ice Letters, vol. EDL-5, no. 11, p.473, Nov., 1984. (3.131 J. Whitfield, "A Modification on *An Improved Method to Determine MOSFEI' Channel Length'," IEEE Electron Device Letters,vol. EDL-6, no. 3, p.109, M r h 1985. ac, (3.14) M J Thoma and CR. Wcstgate, "A New AC M a u e e t Technique to Accurately .. esrmn Determine MOSFET Constants," IEEE Tran. on Electron Devices, vol. ED-31, no. 9, p.1113, Sep., 1984. [3.15] E.J. Korma, K. Visscr, J. Snuder, and J.F. Verwey, "Fast Determination of the

Effective Channel Length and the Gate O i e Thickness in Polycrystalline Silicon xd

MOSFET's," IEEE Electron Device Letters,vol. EDL-5, no. 9, p.368, Sep., 1984.
[3.16] BJ. Sheu and P.K. KO, "A Capacitance Method t Determine C h m l Lengths for o Conventional and LD MOSFET's" IEEE Elecvon Device Letters, vol. EDL-5, no. 11, p.491, Nov., 1984. (3.171 J. Scsrpulla, T.C. Mele, and J.P. Kn~sius,"Accurate Criterion for MOSFEI' Effective Gate Length Extraction Using the Capacitance Method," IEDM Tech. Dig., pp.722725, 1987.

ehd o [3.18] Y.-RMa and IC-L. Wang, "A New M t o t Electrically Determine Effective MOS-

FET Channel W d h "IEEE Tan. on Electron Devices. vol. ED-29, no. 12, p.1825, it,

m . 3

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Dec., 1982.
(3.191 HS. Lee, "An Analysis of the Threshold Voltage for Short-Channel IGFET's," SolidState E l ~ ~ t r o n i ~ ~ , ~p.1407-1417,1973. VOL 16,

(3.201 L.D. Yau, "A Simple Theory to Predict the nYeshold Voltage of Short-Chamd
IGFET's," Solid-Stae ElectrOni~r,VOL 17, ~.1059-1063,1974.

(3.21) J.A. Greenfield and R.W. Dutton. "Nonplanar VLSI Device Analysis Using the Solution of Poisson's Equation," IEEE T a . on*Elecmn Devices, vol. ED-27, no. 8, rn

pp.1520-1532, Aug. 1980. [3.22] T.Toyabe and S. A b , "Analytical Models of Threshold Voltage and Breakdown Voltage of Short-Channel M0SFEI"s Derived fiom Two-Dimensional Analysis," IEEE J. Solid-state Circuits, vol. SC-14, p.375, April, 1979.

[3.23] K.N. Rarnakumar and J D Meindl, "Short-Channel MOST Threshold Voltage Model," .. IEEE J. Solid-state Circuits, vol. SC-17, p.937, Ou.,1982. [3.24] D.R Poole and DL Kwong, "Two-Dimensional Analysis Modeling of Threshold Voltage of Short-Channel MOSFET's" IEEE Electron Device Letters, vol. EDL-5,

pp.44346, Nov. 1984. [3.25] J.D. Kendall and A.R Boothroyd, "A Two-Dimensional Analysis Threshold Voltage
Model for MOSFET's" with Arbitrary Doped Substrate," IEEE Electron Device Letters, vol. EDL-7, pp.401-403, July 1986.

(3.261 Y.A. El-Mansy and AR. Boothroyd, "A simple two-dimensional model for I G m

operation in the saturation region," IEEE T a .Electron Devices, vol. ED-24, p. 254, rn

M r 1977. a.
(3.271 T Y Chan, P.K. KO, and C. Hu, "Dependence of channel electric field on device s a .. cl
ing," I E Electron Device h m s , vol. EDL-6, p. 551, Ou. 1985. EE

(3.28) K W T e d , C. Hu, and P K KO,"An analytical model for the channel elecvic field .. ..
in MOSFET with gradeddrain structure," IEEE Electron Device Letters, vol. EDL-5,

-76

p. 4 0 Nov. 1984. 4,

. aa, 13.291 H Masuda, M.N k i and M. K u b ,

V O ~ .ED-26, p.105,

"

m and 'cs

Lirnitaticms of Scaled-Down

MOSFET's Due t "weDimensional Field Effect," IEEE Tnm. on E l a m n Dcviccs, o

J~ne 1979.

(3.301 RR. Troutman and S N Cbakravarti, "Subthreshold Characteristics of Insulated-Gate .. Field Effect Transistors," IEEE Tran. on Circuit Theory, voL a2 p.659, Nov., - 0 ,

1973.
13.311 SB.Law and M.V.Fischet& "Monte-Carlo Simulation of Submicrometer Si-n MOS-

FET at 77 and 300 I, IEEE Electron Dcvice Letters,vol. EDL-9, p.467, 1988. C"
L3.321 G.A. Sai-Halasz, MR Wordeman, D.P. Kem, S. Rishton, and E Ganin, " i hT a . Hg rn sconductance and Velocity Overshoot in NMOS Devices at the 0.1-pm Gate Length Level," IEEE Electron Device Letters, vol. EDL-9, p.464, 1988.

fet f3.331 P.K. KO,"Hot-Electron E f c s in MOSFETs," PhD Dissertation, Univ. of California

Berkeley, 1982.
(3.341 ICY. Toh, P.K. KO,and

RG.Meyer,

"An engineering model for short-chanml MOS

devices," IEEE Jour. of Solid-state Circuits, p.950, Aug. 1988.

. (3.351 G. Baccarani, M R Wordeman, and R.H. Dennard, "Generalized Scaling Theory and
Its Application t a 1/4 Micmmettr MOSFET Design," XEEE T a . on Electron Devo rn ices, vol. ED-31,no. 4, pp.45242, April 1984.

. 13.361 W.Hansch and H Jacobs, "Enbanced Transconductance in DeepSubmicrometcr MOSFET," IEEE Electron Dcvice Letters, vol. EDL-IO, no. 7, p.285, July 1989. 13.371 Y. El-Mansy, "MOS device and technology constraints in VLSI, "IEEE Tran. on El=m n Devices, vol. -29,

no. 4, p. 567, 1982.

utr .. I3.381 P.K. Chatterjec, W.R H n e ,T.C Holloway, and Y T Lin, "The impact of scaling
laws on the choice of n-channel or p-channel for MOS VLSI," IEEE Electron Device

W , EDL-I, r)~). 10, p. 220,1980. VOL

chap3

-np-channcl MOS devices for VLSI," Solid-state Elearon, voL 26, m. 10, p. 969,1983.

[3.39] H Shicbijo, "A re-examination of practical performance limits of scaled n-channel and .

(3.401

KK Ng and W.T. Lynch,'The impact of intrinsic series mistance on MOSF'ET scaling," IEEE T m on Electron Device, vol ED-34, 3, p. 503,1987. m.

(3.411 K.Mayaram, J. Lee, and C. Hu,"A model for t e electric field in lightly doped drain h

structures," IEEE Tran. on Electron Devices, ED-34, 7, p. 1509,1987 voL

(3.421 C. Hu, S. Tam, E-C. Hsu, P K KO, T.Y. Chan, and K.W. T e d , "Hot-Electron..

rn Induced MOSFET Degradation Model, Monitor, and Improvement," IEEE T a . on

Electron Devices, voL ED-32, p.375, Feb. 1985. [3.43] T.Y. Chan, Electron Device Letters,vol. EDL-6, p.551, Oct 1985. [3.44] M.Kakumu, IEDM Tech Digs., p.399, 1986. [3.45] C.G. Hwang, RW. Dutton, J.M. Higman, and K. Has, "Accurate Modeling of Impact Ionization Effect in Submicron MOSFET," IEEE Tran. on Electron Devices, vol. ED-

34,no. 11, p.2385, Nov. 1987.

[3.46] B. Meinenhagen and WL. En@, "The Influence of the Thermal Equilibrium Approximation on the Accuracy of Classical Two-Dimensional Numerical Modeling of Silicon Submicrometer MOS Transistors," IEEE Tran. on Electron Devices, vol ED-35, no. 5, pp.689-697, May 1988. [3.47] M. Tomizawa, K Yokoyama, and A. Yoshii, "Nonstationary Carrier Dynamics in . Quarter-Micron Si MOSFET's," IEEE Tran on Computer-Aided Design, vol. CAD-7, no. 2, pp.254-258, 1988. (3.481 J. Chung, M.-C. Jeng, G. May, P.K. KO,and C Hu, "Hot-Electron Currents in Deep . Submicrometer MOSFETs," IEDM Tech Digs., p.200, 1988. (3.491 F.C.Hsu and S. Tam, "Relationship between MOSFET Degradation and Hot-Elccmn Induced Interface-State Generation," IEEE Electron Device Letters, vol. EDL-5,p50, 1984.

-3

-78-

[3.50] H Gesch, LP.Leburton, and G.E. Dwda. "Generationof Interface States by Hot Hole .

Injection i MOSFET's," lEEE Tran. an Elecaon Devices, v d -29, n

May 1982.

n J p.913, o,

[3.51] T.Y. Chan, P.K. KO,and C. H , "A Simple Method t Qlaracteriz Substrate Cumnt u o

i MOSFET's," IEEE E l m n Device Leaem, voL EDGS, no. 12, pJOS, 1984. n
13.521 M.-C. Jeng, J. Chug, AT. Wu,

T Y Chan, J. Moon, G. May, P.K. KO,and C Hu, ..

"Performance and Hot-Electron Reliability of I)eep-SubmicrometcrMOSFEI"L" IEDM

Tech Digs., p.710, 1987.

Chaps4

-79-

Chapter 4

DEEP-SUBMICROMETER MOSFET DESIGN

Although deepsubmicrometer MOSFFTs with excellent characteristics have been demonstrated and the basic device physics of these devices has been shown t be essentially o unchanged, deepsubmicrometer devices arc stin restricted t device level studies because no o design guidelines are available. For longerchannel devices, previous studies [4.14.3] have proposed design guidelines based mainly on the threshold voltage shift due to short-channel effects, subthreshold cumnt, and hotelectron reliability considerations, but the different trade-

offs between reducing oxide thickness, channel length, and power supply are still not clear.

This chapter attempts to provide comprehensive design guidelines for MOSFETs in the deep
submicrometer regime by investigating a wide range of performance and reliability constraints

on device dimensions and power supply. The mechanisms examincd in this study are: shortchannel and drain-induced-banier-lowering (DIBL) effects, the punchthrough and gate-induced
+

drain leakage (GIDL) [4.44.6] currents, hotelectron reliability, timedependent dielectric breakdown P D B ) [4.74.9], currentdriving capability, voltage gain, and switching speed. Using this set of performance and reliability constraints, design curyes are developed based on measurements of n-channel non-LDD deepsubmicrometer devices. The relative importance of each mechanism for a given technology and design criteria is compared. The five basic param-

T eters in MOS scaling are: effective channel length La,oxide thickness ,

power supply VDD,

junction depth X3 and channel doping concentration N m . For most technologies, Xj is relatively constant compared t other parameters. Once Tm and t e threshold voltage is detero h

, T mined, Nsm is fixed. Therefore, only b,

and VDDare considered in this study. X is j

fixed to about 0.18p.m and Nsms arc adjusted such that the long-channel threshold voltages

h for all oxide thicknesses are around 0.65V. T e design considerations included are divided
into two categories. One sets device limitations and the other sets performance constraints.

4.1 Device limitations

4.1.1 Threshold voltage

Fig. 4.la and 4.lb show the threshold voltage shift due to shon-channel and DJBL
effects. As mentioned in Section 3 2 that thcse two effects a essentially om,they arc .

separated here for easy description. In Fig. 4.lb, only , = 8.6nm data are shown. Similat T

results are also observed for other oxide t h i c h ~ .The threshold voltage shift A , , is V,
defined as the difference between the measured threshold voltage at a given drain voltage and

. its corresponding lon-channel value (Vdat a drain voltage of 5OmV.

Although the threshold

voltage model derived in section 3.2 showed that AV& deviates from a simple exponential expression for AVh > O.lV, straight Iines are drawn to fit measured data for simplicity. The dashed lines in Fig. 4.14.8 demarcates the performance and reliability criteria (Table 4.1) used in this study t obtain the design curyes (Fig. 4.9-4.11); the arrows indicate the acceptable o

T and regions. As an example, for , = 8 . 6 ~ 1 VDD = 3V, the minimum allowable Lctrin the
circuit is a b u t 0 . 2 8 ~ purely based on thc threshold voltage shift consideration.
4.1.2 Off-state leakage current

The off-state leakage current is also sensitive to the short-channel effects and was used as one of the criteria for MOSFE" miniatuxization [42]. As shown in the insert of Fig. 4.2%
off-state leakage current is composed of two m i components: punchthrough current ( nand an I)

gate-induced drain leakage current

w. Thc punchthrough current is the leakage c u m t

between the source and the drain. The gate-induced drain leakage current is the drain-tosubstrate leakage due to band-to-band tunneling between n+ and p regions. I n increases with decreasing channel length because of the threshold voltage reduction and the increase i n subthreshold swing.

kIDL however, independent of Ld is,

and is determined by , and the T

power supply used. In Rg. 4.2, the off-state leakage currents were measured at Vw

- 0.6V

for all device dimensions and drain voltages. A gate voltage of Vm 0.6V was used to e h -

m . 4

-81-

inate any effect caused by tbc variations m threshold voltage between different gate oxide

thiciaesses. The punchduough m n t dominated regions arc indicated by open symbols; tbc

GIDL current dominated regions an indicated by closed symbols. The m n t lcvcl of the
experimental data is clamped at a lower bound of O.SpA/pm due t~ limits i the measurement n resolution.
1.00 '

EXP(-L I

s
d

9 t ,

0.10

AVT S 0.1V

o To,=3.6nm A To,=5.6nm o Tox=8.6nm 0 Tox=15.6nm

0.0 1

0.0

0.1

0.2

0.3

.
0.4

0.J

0.6

Effective Channel Length

urn)
3V

Fig. 4.l(a)

Threshold vdtage rechction (AVd versus effedve chaolnel length c Vm d for fau oxi& thicknesses.

Chap-4

-82-

I0.N

Fig. 4 l b .()

'Ihreshdd voltage reduction (AVd VQSUS effective c h a a n d length for , = T 8.6nm at differeat drain voltages.

-83-

-4

VDS

= 3v

---

VGS =

ov

-5
n

Q
ha

r. l \

4
E
Q)
h
c)

-6
-7

0 -8 -9

L L

$
a

T0,=3.6nm A To,=5.6nm o T0,=8.6nm

Q W

2 -10

2 -11
-12
-13

.
0.0

.
0.3

0.1

0.2

0.4

0.5

0.6

Effective Channel Length (pm)

E .42(a) g

0E-stat.e leakage current versus effective channel l q t h m d at , V 3V for four oxide thicknesses. "he off-state leakage ament has two companeats: p c h t h m g h ament and gateinduced drain leakage ament. 'Ihe shows the diEerent paths for these two m p a m t s .

-84-

-3
-4

3v
2v

Tbx = 8.6nm

# h Y

-6.

g
&

1v
-79
-8-9

u'
.I

0.osv

0
bD

2 n -10
-It
=---

-I2
-13

4
0.0
0.1

0.2

0.3

0.4

0.5

0.6

Effective Channel Length (pm)

Chap.4

-85-

4 l Hot-electron reliability .3

Recent studies showed that digital circuits axe fairly robust to bot-elccmn effects ( . 0 . 411
Therefore, the definition of device lifetime in section 35.1 (3% drain current change i the n linear region) is very tight for most applications. In this chapter, a more relaxed definition.

1096 drain current reduction in the linear region, is used for device lifetime. Fig. 4 3 displays .
the extrapolated maximum allowable power supply voltage to

ensun a 10-year device lifetime

( . 1] as a function of channel length for four oxide thicknesses. For a given substrate currmt, 41
thinner oxide devices exhibit less degradation than those with thicker oxides ( . 2 .However, 411 for a given drain bias, thinner gate oxide devices also exhibit greater peak substrate current

than those with thicker oxides (see Fig. 3.18). These two counteracting trends explain why
8 . 6 gate oxide devices show a slightly smaller minimum channel length than those of 5.6nm ~ and 15.6nm gate oxides devices a a power supply of 3V. According to Fig. 4.3, at a power t supply of 3.3V and with effective channel length larger than 0 . 5 p , LDD may not be needed.

414 Breakdown voltage .. . Fig. 4 4 shows breakdown voltage versus effective channel length for different oxide
thicknesses. The breakdown voltage is defined as the minimum voltage of the c-shaped break-

. g ., down curve shown in the insert. Comparing Fig. 4 3 and H .4 4 it is found that the breakdown voltage is about 1V to 2V higher than the maximum allowable power supply set by hotelectron requirements. Although under normal operations the breakdown w i l l not be a limiting mechanism in MOS scaling, it sets an upper bound to the burn-in voltage.
4.1.5 Tim-dependent dielectric breakdown

Based on a defect-density model, a technique to predict oxide breakdown statistics has

been developed [ . ] Plotted in Fig. 4.5 is the maximum allowable supply voltage to ensure 49. 10-year lifetime at 12?C versus oxide thickness for two defea densities. Because oxide quality is a sensitive function of the device fabrication process, the oxide reliability results used in

this study should be viewed as a rough approximation only. Other fabrication technologk~ can

Clbap.4

-86-

yield a higher quality oxide with a lower defmdcnsity than i observed i this study (1.0 s n
an-2). Listed i Table 1 is the oxide niiabii criterion used i Fig. 4.9411. n n

2.6
2.4

Fig. 4 3

Maximum allowable power supply t CDSUIC lo-year device lifetime &e t o o hrrt-$ectron && e vefsus &edive Cbannd length for severat oxide brichesses. Ihe device lifetime is &fined a 10% fornard drain aurent dtgras dation i the linear region. 'The dashed line indicates the criterion used t n o
&tainedthedesignawes.

90

Breakdown Voltage (V)

U m

c
c
..,
4

O O D O

U
0

-88-

6-

5m
m

1 O y e a r li

4 -

3 m
m m

2 m
I ,

.
t
t

Y
I

Defect density:

v
I
t t

.5 cmo2
. I
8
t

1'

10

15

20

Oxide Thickness (nm)

Fig. 4 5

Ibhimum allowable power supply to ensure lO-year &vice lifetime due to t i m e d e p h t dieledc hreak&wn vezsus oxide thickness for two Meet dep
sitits.

m . 4

-89-

4.2 Performance constraints

43.1 Currentdriving capability:

Fig. 4.6 shows drain saturation m n t I

~ versus effective channel length. 'ihe drain T

saturation current is measured at V a = 3V and , V

= 3V as shown in tbe insat As

expected, the currentdriving capability for a given gate oxide increases as the channcl lcaglh decreases. However, because of mobility degradation due to high vertical fields, tfie cuTrcIltdriving capability tends to saturate at very thin gate oxides unless the channel length is very
small such that all carriers in the channel arc moving with the saturation velocity. The high

channel doping concentration required to achieve the required threshold voltage for thin oxide at devices also degrades camer mobility. The sharp increase in I ~ A T very shortchannel

o lengths is mainly caused by the threshold voltage reduction due t short-channel effects.
43.2 Voltage gain

In Fig. 4.7, the peak voltage gain (solid l n s m a u e near V m = OV and the gain ie) e s r d

(alternated lines) measured at V a VT = 0.3V,where most analog circuits arc biased, arc plot-

ted for various device dimensions. The voltage gain is defined as &&, when g i the ,s
measured transconductance and

is the output resistance. Since both g and & are higher ,

for thinner gate oxide devices, the voltage gain increases as oxide thickness decreases. The sharp decrease of the gain at very short channel lengths is caused by bulk punchthrough which significantly reduces L.
4 3 3 Switching speed

Because no CMOS circuits were available, the switching speed studies w r achieved ee
through simulations on CMOS ring oscillator delay time. T ensure high confidence, a MOSo

FET model accurate down t quarter-micron channel length was used in the simulation. This o
model is described in chapter 5.

ng.4.8

shows SPICE simulated delay time of an ll-stage

CMOS ring oscillator with a 0.lpF load capacitor on each stage for different oxide thicknesses,

chaps4

-90-

channel lengths, and power supplies. The channel widm is 1 5 p fop n-channel and 3Opn for pchannel devices. The overlap between the gate and mt sourct (drain) i 0 . 0 5 ~ As oxide s . thickness decreases, the gate capacitance eventually becomes larger than the load capacitance. However, because IDSATtends to saturate at thincr gate oxide (see Fig. 4.6), tfie capacit;lllce

charging rate does not increase as rapidly as the gatc capacitance These two mechanisms
explain why the delay time dots not continue to decrc;rsc with diminishing oxide thiclrness m

Fig. 4.8a Because the drain current saturates at larger gate voltage, the delay time also

saturates at larger power supply.

o To,=3.6nm A To,=5.6nrn

VGS = 3v

v*s = 3v

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Effective Channel Length

Fig. 4 6

urn)

0.9

1.0

Drain saturation ament versus effective c h d la@ for f a n oxide t h i c k n ~ .Ihe insert shows the bias conditions wben the m e a t w8s me8sc d

o TOx=3.6nm A TOx=5.6nm

= ov
r'
i

0.0

0.2

0.4

0.6

0.8

1.0

13

1.4

1.6

Effective Channel Length (pm)

Fig. 4.7

Single stage voltage gain (8versus &&e channel leqth far four oxide thiclmesses. The solid lines i dW the maximum availde gain and the ni alternated lined are the gain meamred ab v,-v* = 03v.

T0
0

---------

.
S
10

.
1s

20

Oxide Thickness (nm)

Fig. 4.8(a)

!PICEsimulated ring osciUatm dclgr time opereded at a pawct supply af 3V versus oxide thickness for s e v d c h d lengths. 'Ihe load Capacitance i 0.lpF on way s

0.5
n

20.4

Q)

-s E
W

c)

a 0.3.

17

2 -

0.2

0.1

VDS =
0 01 .
1
I

4v
1 1 1

Fig. 4S@)

SPICE simulated (Tules ring oscillator delay time versus &ective channel length for Ta 86nm operaded a Mereat supply voltages. t

Chap.4

-94-

4 3 Design guidelines
Based on thc experimental results presented in SectiOIls 4.1 and 4.2 various design curves
were developed. As mentioned b f n since oxide thickness, channel length, and supply voleo, tage axe the key design parameters in this study, three types of design curves axe provided for

maximum flexibility (Fig. 4.94.1 1). Each type of m e fixes one parameter while varying the
other two. The intersection of these performance and reliability curyes (shaded area) indicatcs
the region of allowable device dimensions and/or power supply for both digital and analog

applications under some design specifications. Table 4.1 summarizes the meanings of the symbols in Fig. 4.94.11 and lists the performance and reliability criteria used in developing t h e design curves.

TABLE I

Time D c p d c n t Dielecdc Breakdown

S 1%

Table 4.1

Design aitcria for design c w c s .

Chaps4

-95-

43.1 Oxide thickness versus channel length

Fig. 4.9 shows design cwcs whem the optimal oxide thickness for this technology i s plotted v e m channel length for a power supply of 3V. Al the curves corresponding to thc l constant contours of different design considerations use the criteria listed in Table 4.1. For example, the m e marked by AV,,, w s obtained f o Rg. 4.1. The gate oxide and effective a rm channel length combinations along this m e will give 0.1V threshold voltage shift The

arrows indicate the acceptable regions. Devices with T and Itf!in the acceptable region have ,
k less threshold voltage shift than 0.1V. But t channel-lengthcan not be too long due to I
~ T

and switching speed requirements, which set upper limits to device dimensions. The intersection of all acceptable regions forms design windows (shaded regions). Because of different design requirements for analog and digital circuits, different bounds (different windows) are used for these two applications. T e breakdown curve is not included in Fig. 4.9-4.11 because h it is not a limiting mechanism under normal device operation. According to the design windows, the minimum gate oxide thickness at this supply voltage is limited to 5.6nm by the gate-induced drain leakage current, and may be limited by the time-dependent dielectric breakdown for technologies wt less robust oxide. For digital appliih

cations, depending upon the oxide thickness, the minimum channel length is determined by
either the threshold voltage shift or by the hot-electron reliability criterion; the minimum allowat able channel length is found to be 0 . 2 6 ~ Ta = 7.8nm. The largest channel length is about
0.45p.m limited by the switching speed requirement. For analog applications, the minimum

~ , channel length is about 0 . 3 1 at T = 6.3nm limited by the voltage gain requirement. It should be kept in mind that the minimum (maximum) device dimensions mentioned here refer
to the "worst case" conditions. For example, if the channel length variation for a given process

is fo.lpm, then a minimum channel of 0 . 2 6 ~ implies a nominal channel length of 0.36~.

The same argument also applies to t e oxide thickness. Another advantage of these design h
curves is that the relative importance of each mechanism can be identified for any device dimensions which makes design trade-offs very clear and provides a direction for future tech-

Qlap.4

-96-

nology devdopmcnL

AVT

Digital Application Application

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Effective Channel Length (pm)

E .4 9 g

~ g m e s for a power sudy of 3 ~ DiBFerent &es n . o c t the o constant contour of each design d & r a t i o n with the criteIia listed i Table n 4.1. 'zbe shaded areas indicate the allowable regions.

Qtap.4

-97-

43.2 Power supply versus channel length

Fig. 4.10 shows design curves where the suitable power supply for this technology i s
ploncd against channel length for T= = 8.6mn. Again, each curve cormponds to the constant

contour of a design criterion listed in Table 4.1 and shaded regions are the allowable design
windows. At this oxide thickness, the maximum power supply voltage is limited by the hotelectron reliability while the minimum power supply voltage is limited by the switching speed requirement. The minimum allowable channel lengths is about 0.28pm for digital applications limited by the threshold voltage shift, and is about 0 . 3 6 ~ analog applications limited by for

the voltage gain. These values are roughly independent of the power supply voltage because t e peak voltage gain is independent of power supply and short-channel effect is much more h
sensitive t the channel length than to the power supply. The maximum channel length is o
about 0.48pn. At a power supply of 3.3V,hot-electron reliability does not pose a problem to

devices with channel length longer than 0.4 pm implying that LDD may not be needed, but

w t the bum-in consideration, longer channel length or LDD may still be necessary. ih
433 Power supply versus oxide thickness
Fig. The last type of a w e s is the design curves for Lg = 0 . 3 ~ . 4.11 shows power At supply versus oxide thickness of each design consideration for Ld = 0 . 3 ~ . this channel

length, the maximum power supply is Limited to about 3V due to hot-electron reliability, no
matter what oxide thickness is used. The minimum power supply is determined by the speed requirement, about 2V at TQ = 4.0~1. The maximum TQ is about 9nm for digital applica-

tions and 6 . 5 ~ for analog applications due to voltage gain requirement 1

43.4 Junction depth

Although the junction depth has been fixed at 0.18pm in this study, with slight modifications, the design curves in Fig. 4.94.11 can be extended to other junction depths. For example, if the junction depth is decreased, short-channel and DIBL effects and punchthrough

currents would diminish. However, hot-elemn reliability would degrade due to the increase

chap3

-98-

i the peak channel electric field. n

+G
5 1 4

n n

h 3.

I A

= I
1

0
0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Effective Channel Length (pm)

Fig. 4.10

Design a w e s for T , 8 6 m Diffezeat awes comspd t the cuastmt o contouf o each design consideration with the critcxia listed i TaMe 4.1. 'Ihe f n shaded tlI#Ls indicate the 8lIlcnVablt regions.

m . 4

Design Curves for Leff = 0 3 . - --__ -- .- ___

~

Application Application
0

IO

IS

20

Oxide Thickness (nm)

Fig. 4.11

Design curves for & 03pm. mra curves cOneSpOnd t the camtzmt eet o contou~f each design Consideaation with the criteria listed in Tde 4.1. ?be o
shaded areas indicate the allowable regions.

-100435 Other power supply and device dimensiau

M g n c w e s for other pow= sq#yYT,,

d h values am be obtaincdwith thc s m c

approd~Similar design curves as those in Fig. 4 9 far a v e r supply of33V arc shown in

Fig. 4.12. Since the &vice lifetime is more sensitive to the powex supply than other mdum

isms (see F .4 . 1 4 4 , this fact i dected by &e large shift OII the z cureve i Fig. 4 2 q s m n
COmpEned to that i E .49. 'Ihe design windows arc d e r and shift toward longer chrond n g and thicker oxide directions a s
43.6 Other technologies
' b e same

methodology used t derive design curves shown in Figs. 494.11 can also be o

extended t any technology, including p-channd aad LDD devices. For example, with LDD o

devices, short channel, DIBL, and GIDL effects would be less s c v m and the hotelectron lf ie
time would be longer. However, currentdriving capbility and gab w u d decrease due t the ol o

increase i s d d r a i n resistance. 'Iherefore, the design windaws i Fig. 4 9 will move n n

toward the lower left, i.e., shorter channel length a d thinner oxide a expecbd The LDD s
effects on Fig. 4.10 and 4.11 can also be a~lalogizcd,

-101-

Application Application

0.0

0.1

0.2

03 .

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Effective Channel Length (pm)

Fig. 4J.2

Design curves far a power supply d 33V.

w - 4

-102-

4.4 References

(4.1)

H. Masuda, M Nakai, and M. Kubo, "Characteristics and Limitation of Scaled-Down lc n MOSFFT's Due to Two-Dimensional Field Effect," IEEE Tran on Ee m Devices,

VOL ED-26, pp.980-986, J u n ~ 1979. ,

[4.2] J.R. Brews, W. Fichtner, E H Nicollian, and S.M. Sze, "Generalized Guide for MOS..

FET Miniatuxization," IEEE Electron Device Latten, voL EDLl, no. 1, Jan., 1980.
(4.3)
H. Shichijo, "A Recxamination of Practical Performance L m t of Scaled n-Umncl iis and pChannel MOS Devicts for -1," Solid-state Electronics, vol. 26, no. 10,

pp.969-986, 1983. [4.4] T.Y. Chan, J. Chen. P.K.KO, and C. Hu, "The Impact of Gate-Induced Drain Leakage
Current on MOSFET Scaling," IEDM Tech. Digs., p.718, 1987.

[4.5]

C. Chang and J. Lien, "Comer-Field Induced Drain Leakage in Thin Oxide MOSFI~s," IEDM Tech Digs., p.714, 1987.

[4.6]

H. Sasaki, M. Saitoh, and K. Hashimoto, "Hot-Carrier Induced Drain Leakage Cumnt

in N-Channel MOSFET," IEDM T c .Digs., p.726, 1987. eh

[4.7]

M.H. W o s and B.L.Euzent, "Reliability in MOS Integrated Circuits," IEDM T c . od eh Digs., p.50, 1984.

u xd [4.8] J. Lee, I.C. men, and C. H ,"Modeling and Characterization of Gate O i e Reliability," IEEE Tran. on Electron Devices, 1989.

.. [4.9] R. MoaUami, J. Lee, I C Chen, and C. Hu, "Projecting the Minimum Acceptable
Oxide Thickness fir Tie-Dependent Dielectric Breakdown," EDM T c . Digs., eh

p.710, 1988. [4.10] P.M. Let, UM. Kuo, K. seki, P.K. KO, and C. Hu, "Circuit Aging Simulator (CAS),"
IEDM Tech D g . pp.134-137, 1988. is,

Cbap.4

-103-

( . 1 C Hu, S Tam, F.-C. Hsu, P K KO, T.Y. Qlan, and KtW. Tenill, "Hot-Electron411 . .
Induced MOSFET Degradation Model, Monitor, and Impmvemau." IEEE Tran. on Electron Devices, voL ED-32, p.375, Feb. 1 8 . 95

I . 2 M.Yoshida, IEDM Tech. Digs., p 2 4 1 8 . 411 .5, 95

-104-

Chapter 5

A DEEP-SUBMICROMETER MOSFET MODEL FOR ANALOGDIGITAL CIRCUIT SIMULATIONS

In a t i o n to high m a t drive, mother +or advantage of scaleddown devices is the
reduced device a e which allows high= integration levds. W h the dwnatic increase i the ra i t n
number of transistors per chip, the circuit complexity and the fabrication cost also incnxse ~ a r p
portionally. In order to speed up the

VLSVULSI system design and t reduce costs, it has o

become necessary to start the circuit design in the early stages o technology developmeat and f
to predict circuit behavior before the circuit is ~lctudyfabricated, both of which require intee sive use of circuit simulato~~. Since the device charactdstics of small-geomeby devices are

highly sensitive to parameter variations, optimal circuit designs become even more difficult to
create than before. Therefore, an
~ ~ c ( w ~ t e mpu~ooaUy a

and

efficient drain aurent LllDdd

for deepsubnicnxneter MOSFEI's becomes extremely crucial and indispeasabie in developing

future system designs.

In this chapter, aMOGmdrrdn CUlTcDt model suitable to p d c t small geometry &ects

for size as smaU as quarter-mimn channel length, for digital 8s well as analog applications is

described. The basic framework of this mo&l is b a d on the recent improved physical understanding of deepsubmicrometer MOS devi-.

In developing this maM, meticulous cam has

b e taken in retaining the basic b c t i d form of fully physical models while impnrvipg en
m d l a c c u r q and compltational efficiency. ' h e oe
e8se

o parmetex extraction was also a f

major consideration. In addition t the efec& wmmcmly included in the MOSFET drain o aureot equation, it is found t a the inversiotAayer Capacitance &ect I5.1321, hot-elecbpn ht in&ced output resistance degradatioa 1533.41, and sourrce/drain parasitic resistance effect [55-5.7) are also important factors t Considex m deegsubmicraneter MOSFET modding. A o
model considering all o these effects has been implemeakd in SPICE3 (5.8-5.101. Some of f

-5
the simulation results are presentad

-105The d ppzuxeter extraction dgozithm and the

ma^-

uramat system arc also bridy discussed (5.111.

5.l General properties of MOSFET m d l n oeig

5.1.1 Semi-empirical nabre

Because of stringent requiranents,fully physics-based models an s e l h used in Circutit

analysis either due to too complicated d equations 'or poor
EICCUTBC~.

Most MOSFET

drain ament modeas for circuit simulations an, to a certain exted, semi-empirical i nature n
[52]. In semi-empixical models, only the basic functional form of equations derived f o devrm

i e physics are kept to describe the general MOSFET behavior. Higher-order physical e.feds c
are incorporated through empirical equations with fitting parameters to achieve better accuracy

and computational efficiency. The drawbacks of the d-empixical approach 8te, however, the
existence of non-physical parameters and the increasing size of the parameter set. With the wmpter capacity of today, an increase i the number of parameters is usuaUy not a proMem n as long as all the parameters can be automatically d But the existence of non-physical
parameters and the associated parameter redundaucy problems are vitaI t the Optimization p w o x

cess during parametex extradon [5.12,!U3]. Non-physical parametex values a~ also d i f h l t

t interpolate or extrapolate for devices with Merent sizes. Therefore, a carefid selection of o
model equations and parameter extmztion strategy is important &ring the model developneat,

5.13 Accuracy
b e t tight specifications i circuit designs, M O S m m d l for Circuit simulations o n oes

usudy require high acwacy under all bias conditions. Much work has been done t the o
MOSFET drain avrent models. Important physical phenomena such ss velocity saturation, mobility degradation, and some short-channd effects previmly discussed are already included in most sophisticated models. Far digital a p i a i n , existing drain aurent m d l an g e plctos oes e d y Considered adequate for MOSF'EI's down to near-micron channel length. But for analog

-5

-106-

5.13 Computational efficiency

Since the model equations are usually evaluated thousands of times h i n g Sirmlation far
mast MSI circuits, it i essential thad device m ~ d e l s s u~ed'incircuit simulrdor~ be
LIS

tiondy efficient

8s

possible. The compltational dficieq of a modd i dected by thne s

properfies: simplicity, explicitness, and Continuity of the mudel equations and their derivativeS.

'Ihe first two properties directly reduce the equation evaludon time and the last oat reduces the number of iterations required i simulation and helps the program t comexge. While most n o

MOSFET m d l have explicit expressions for the drain ament, discontinuitieS ab transition oes
points from strong-inversionto subthreshold, d from t h d e to saturation regions usually exist i the model equations and their derivatives. With the increasing complexity in VLSI circuits, n
convergence requiremeats have become moxe Strict. ' h e continuity property has bees a crucial
consideration in future MOSFET modeliqg.

5.1.4 Ease of parameter extradim

For modem MOSFEI' m d l that typidy have a xather larger set of pammetem, ease of oes
parameter extraction i anothex essential property of M0m;ET models, since the applicability s

o aMOSFEI'model i Circuit simulation i highly dependent on how easily and 8ccuf8bcIy f n s

the model parametem can be errtractai. Usually, MOSF" models and the papaneter extraotion systern are developed

in sequence which implicitly embeds difficulty t the parameter o

extraction and limits the potential capability of a modd. This is one of the reasons for the

weak link between device chmctexization and Circuit simulation, A useful MOSFIT mDdd
should be developed with ease of pawnctcr d

n in Consideration,

-107-

As pointed out i section 33, the basic physics involved in d e e p s u b m i c r m MOSn

FETs is similar to thd of their mimn-sized wunteqmts and existing 1p MOGFET mod& are
extendiMe to the deepsubmima regime with only the need for minor modifications.

Since the exiSting BSIM drain anent mbdd [5.14,5.153 (BSM) has al the favorable properl
ties fse in section 5.1, it provides a good basis for &vcloping a deepsubmicrcnneter MOSitd

FET m d d .

'Ihis Section briedly discusses the BSIM appr$ach and formulation. Some results

and problems of the BslMl model are also reviewed. More detailed description o the BSIM f

histmy and m d l can be found in [5.16]. oes

5.2.1 The BSIM approach

BSlM is a geaeric name of

~LI integrated

system for circuit designs.

It is composed of a t model, a parametex

mea^^

group of models such as the drain CufIMt model and the substrak m

extraction system, and a Circvit simulator such as SPICE BSIM n p c U are physically ingfd and mathematidy corn@,

and since they wexe developed based on cornprehsive

studies o device physics, most of the important physical effects are included Except for the f

very basic physical equrbions, the rest o the model equations were empi~%Ay determined to f
achieve high accuracy and maximize the compltational efficiency. 'Ihere are no M a l t parameter values and al model parameters are automatically extrwted from physical devices with the l
crssuciated parameter - n o system

"his approach links circuit designs with p'ocess tech-

nologies, which makes simulation results more realistic and also eliminates any problems

ceused by slight process variations.

533 BSIMl review

'Ihe present BSIM drab current model b been shown to be adequate i modeling n
MOSFETs with one mkron channel length, but the a x u r q begins to degrade when the c
h

nel length is reduced becaue the sewnckder effects of some physical phenomena became

more severe and others rn not propedy implemented, Without mentioning the success that

?he drain CuIzrtlt equations of BSIMl arc similar to those of atextbook model, but with

abetterrnobilitymodel. ?hebullr-chargeetrectisalsoinclu&dandsin@ed.

laedor

m d l equations of BSIMl axe listed i (S.l)-(S.l2). A oanplete list o BSIMl moda e ~ u a oe n f

tions and the meanings of each paramttcrs axe given i Appenaix B. n (A) Threshold voltage:

where Vm is the flat-band voltsge,

h is the surf-

potential at which the threshold voltage

voltage is defined, Klis the body-effect coefficient (+valent

text books),
*

t the parameter rused i roost o n

the d r a b

K2 axounts for the non-unifonn

channd

doping effect, and q is

induced-barrier-lowering coefficient (S.l7].

g =1

1 7 4 +0.8364(k .4 -Vm)

(55)

U is the mobility &graaEdion coefficient &e to the vextical fidd, & is the critical fidd for the ,
velocity saturation effed, a ami g arc derived from the sim@d bulkcharge effect

K=

1+vc+qimr@

-Vd vc- (va

and the drain satudon voltage is given t y

(D) Subthreshold drain cun-ent:

(5.10)
where

(5.11) (5.12)

, is the the& V
current in the

voltage given by kT/e n i the subthreshold Swiog coefficimt, I= is the s

subthreshold region, and & i used t limit b&in the strong-inversion region. s o
a e body-bias and/or dmb-biss d e p d m t r

Some of the parameten i (5.1)-(5.12) n

Although BSMl includes many o the impOrt.nt physical effecb, these effects are only f
corrected to the first o&.

'Lherefore, the minimum valid &vice dimensions of BSIMl are

15nm. The channel length modulalion effect (or the autpt

limited t & s lpm and , o T

resistance) is empirically modeled by the

pammetexusiog a quadratic function o Vm f

(sat

Appendix B or [5.18] ). ?his approzch is geaerally d e q a t e in m d l n the drain a e t as oeig mn shown by the good agreement between the meafllred d calculated Im

- Vm characteristics in

Rg. 5.1% but does not w d y predict the a u t p resistance a shown i Eg. 5.lb, where the s n

-5

-110-

== m outpltr w 5
~~ICC makes

o Fig. 5.lais plotted. 'Ibe inability to modcl the artplt IC&+ f

the

BsMl less suitable for d o g applications than for digital.

transition from the subthreshold region t the strong-inversion region is d e v e d l summing o q

up the CUITenfs calculated in both rtgions. 'This approach adds 4, to the strung-invasion
drain m
t

and results in a CoDstBDlt

CMent

offset in the stnmg-i~~~eon region

EIS

ca

shown in Fig. 52. For analog a p i a i n ,wherc most MOSFETs lllt oper&cd d low culzlmt plctos levels, this aurent o f e may caue large QCOIS in simulation results. Also, B L ~ fst mpkical COQstant elB i s

used in (5.11) t 8coounf f r the slight difference in threshold vd@e between o o

strong-inversion and subthreshold regions. In reality however, it is found that this thnsboid ioltage offset is technology dependeat, varVing with process, and i a fundon o device s f
dimensions. An example i shown in Fig. 5 . Uig a fixed number f r the offset may also s 3 sn o

introduce large simulation errors related to the off-state leakage such as DRAM rehsh time.

53 The BSIM2 model

The deepsubmicrometer model, B S M , w s developed b a
aforementioned problems o BsIMl in mind. f

d on BSIMl but with tbe

&nvation o the f

In this section, the detailed

BSlM2 model is Qescn'bed. BsIM2 has been successfully used t model the drain ament and o
output resistance o f

MOSF'EI's with gate oxide thicknesses as thin z 3.6mn d channd s

lengths as small as 02pm. 'Ihe drain cumat equations and their h t derivatives are mim t r
ous throughout the b a ranges. An hpxuved parametea extrdon algorithm and systan for is

BSIM;! were also developed [5.11] and arc d 53.1 Physical && e
included

d in section SA.

Based on recent physical uaderstandiog o deepsubmicrometer MOSFETs discussed in f

chapter 3, it is found that the importmt & % a
that should be iocluded i n

MOSFET modtling

are:

-111

1.0

:Jf

05

ff#
0.0
0

: I
1

Drain Voltage (V)

1) 1

s I .: c
1. 00
Y

...

1s
2.0

31)

Drain Voltage (V)

Fig. 5.1

B S M modeling results. "x"s m measured data and the solid hes an the B S M moW. (a) Vm, (b) the cOITeSpOnding output resistance o the f

Samedwice.

-1l2VS B

1D

01)

-31)

05

0.o
0

Gatevoltage (V)
I

OS

1s

Gatevoltage (V)
Fig. 5 2

Fig. 5 3

-1 1s

1 mblt rechction due t the vertical f d . oiiy o id

2. carder velocity sahuation,

3. draiDinduced banier lmaing.

4. sauce/drain charge shariog.

5. llomuniform channel Qping.

6. channel lcngth modul&on.

7. subthreshold condllcticm.
8. d i parasitic resistaace.

9. h o t 4 ~ n - i n d u c e d outplt resistance reduction.

10. inversion-layer capacitance.

E c q t for the last t r e effects, most of these were alredy included in the BSMl mode. In he

the following sections, these effects were mexamined based on deepsubmicrometer MOS

m considerations and their implementation i BSIMlL is descn'bed. s n

5 . Strong-inversion region 32
(A) Threshold voltage

It has been shown i chn

3 that the threshold voltage of propexiy designed deep

submicrometer MOSFEI's does not exhiit severe short-channel effects until the devices are oear punchthrough. Therefore, the -hold voltage model, E;q.(5.1), used in BSIMl which

already includes m s of the important short-chanuel effects such a the d d r a i n charge ot s

sharing, non-uniform channel

doping,

and draikindud=er-lowering,

is retained in

BSIMIL. A typical threshold vd-e

for a quarterdcron n-chamel MOS transistor is shown

Rg. 5.4. The asterisks are meanucd data aod the d i d a w e is calculated from (5.1). In
BSIMl, the c m - m h e C a r e - o e i gd u e n t q is empi.xically expressed a a linear ihicccbrirlwxn s
function o , fV

md. , V

But in BSlM2, be dependence of q on, , V

qB is nmoved since

it does not agree w t physical principle and may c81se negative output resistance at low ih
ament levels if q D has awnmg sign.

-114_ - .

1.5

T , 86 A o
Weff = 10 pm
n
U

NMOS

+
m

La
1.0

0.25 p m

!Y c,

$
a m

2
8
0.5

'

'

'

'

0.5

0.9

1.3

1.7

21

Fig. 5.4

Threshold voltage v e m s body bias for a qucater micron whamel MOSFET. The ssterisks aremeanuleddataapld the d i d curve i thtmodcl, s

-115-

Ibe sccumy o a drain a m a t modd is M f

effect

y diected @ how the vdocity saluratioa

is implemented, apedally for deepsubmi-

&vices in which the c h d dcctxic

field is high d the drain clll~t quickiy saruratcs. 'Ihe nlltionship bctwetll the c x i r o d e axc
Qty eDd the chaanel e l h c fidd har been s u i d tde

vollious groups [5.19$20].

of lhc

d t s is shown in Fig. 55 (5391. 'Ihc dots arc mawed dasa md the c w c s rcpreseat different velocity models w i h will be described below. 'Ihe most cammonly used dQ. hc

velocity model is (5.13), becase it leads to simple analytical chin camcat equations.
(r

v=l+pJ

(5.13)
p i the mobility, and v- is the carrier satmition velocity. 'Ihe result s

where & &,EV&, -

o (5.13) i indicated by me1 in F .55. However, this modd undurstimates the h e r f s q

velocity in the low-field region as cao be sea in F .55. A second m d l the socalled s oe,
"two-section" model [521), was proposed, to improve the tccunxy of (5.13). In the t w e d o n d, a larger Critical field of&-=
v, whea E > E , The result is plotted
~~ccuracy, it

is used in (5.13) w h E <E, md sets v

= awe-2.

Although this modcl am achieve betta

results

in a discontinuity in the b duivadive o the drain ament equation d t f

V .

To retain the high l~ccuracy yet to rnroid the discontinuity prublan, a compmmised and

solution is used in B M S .

when the critid field &starts from alargervalue of&&

+ Q in the low-field reg;Oa IS

IS

m the twesecticm modd d smoothly CbaDges to & t&V= = V -

i (5.13). &is n

fitting paramctcr. The rcsult of (5.14) is shown i awe-3 in FSg. 53. The q u a c fuodion n
used in (5.14) is to keep the first derivdve of the drain cuzrcllt @on

continuals at V ~ T .

-116

IC#

.
a

ICW

"d

. . . . . .
I

.
ICIC+2

. V = A : 1 + (E/E,) .
I

'

Ice3

IE-

I E+S

ICY

Electric Field (Vlcm)

2.

E,=2E,
v =vat

ESE,

E>E,

3.

-117-

(Q Mobility Isduction due to v d d field

It has bcar shown Paaa the d e r mobility cam be explesssd s aunivasal furdon o the f
effective vertical electric fidd for a wide renge of oxide t h i c k and c h d doping casea-

tdon (522-5241.

where h, I&, and n are mutants whose values am be fouad in [524],

vertical electric fidd in the inversion layer given by

& is the effsctive

(5.16)

4 and $I are the bulk and iqwrsb charge density, respectively. However, Eq.(5.15) is sd,
dom used i circuit analysis for several reasons. Fixst, Eq.(5.15) docs not have a desiie n
functional fom for ckcuit simulation purpose becarse of the power function in tbc denomina
tor. Tale 5.1 lists the relative evaludon time required for v & a u functions based m 106 4 -

culations in a SUN SPARG1 station. 'Ihc evaluadion tkne of a p a function is about 3

times that of an exponential and 120 timer E ad asimple arithmetic a e a i m secoadly,Q, ht prbc.

in the subthreshold

w not be errplicitly expnssed s a fuoction of the

v01-

tag=, therefore it can m be dinctly used in most cirarit simulators d d t s in d f i u t i t ifcly n parameter extraction. Thirdly, the parasitic saurcddcain nsistaaoe effect also cases mtllsurcd

mobirity t devi& from (5.15). A more Widely accepted mobility modd i (5.17), which can o s

be considered a a first-ordtt approximation o (5.15). s f

For d c e p s u M devices with thin gate oxides, the vertical electric field is too lage ~

which caws the first-order a p o i d d (5.u) to bacome indexpate as shown in Fig. p r am m

5.6, whae the electron d t y for 8.6nm gate oxide &vices i plotted agaiast Vm-V,. s
Qss

'Ihe

arc meawsd dada and the clashed h e i thebest fit o (5.17). A simple amemrimat to s f

-5

-1111l l x x v ~ c yis

improve the

t add higbcr-orda t m to the hamugor d (5.17). It i f o a * s

that the inclusion of the SdOOtlCCOrdQ term only, (5.18), is am@ for most t i gate axi& hn
devices undcrIlorm$ bias cooditions ad the result i giveaby the d i d curve i Fig. SA. s n

'Ihe use of (5.18) also provides BSIM2 with the capabitity to mo&4 the nowmonotun nxM'c

ity bthavior with the vettical fidd at low

(529

The effect o the SoUrcejdfEdn resistance on device paformance has bctn discussed in f section 3 3 . In section 33, these parasitic rtsistaoces were frcatcd as external components t o

the MoSFETs, but from a circuit shlation point ab view, ddbg extra e l m to each
transistor w d d greatly increase the circuit size and slow &wn tbe simuldon speed.
more, extrecting intrinsic MOSFEI' paoanebs h m
wdrinsjc

&vice

'csrequire

p i a l c r during themeasurerpe~r Optimizatioaprocsdurs, which w o u l d g d y ae and

a @ -

cape the param"r txtraction proccss.

It am be shown [52q that with a papa sdediua o f

the model equations, the parasitic resistrrnce c f ~ c a n b e l U m p e d i n t o t h e m o b i l i t y ~ In

BSIM2, the parasitic resistance effect is i n c o p d i ( Srad (5.18). 'Ibcrcfore, w h the n U )

mobility parameters are extracted fnnn test devices, tbe d d r a i n parasitic nsistaKx efFect

is altomedically included i this rryytl. n

Iu BSIMI, the velocity saturation d mobility rc&ctkm &e to vertical field effects w a e
p togetha through multiplication o (5.15) d (5.17), xcsultjng in a pro&ct tam in tbe t f
denominator of (52). Wh such formulation, t Saturatioo vdodty decreases as tbe grte voli t k
*e

incrurses which does

mt

agree With the physid ObsavatiOO thac the Canicr

velocity is ccmstmt at a givea tanpedum, independent d the v d c a l fidd [5.19$20$27].

A more physical approach, which sums the two dkts t o g a , i &ptd io BSM2 rad tbe s

-119d t i q cfrain cunmt for the linurr region is giva i (5s). n

S20.0

440.0

360.0

280.0

208.8

chap5

-121-

when E, is given i (5.15). As a mattex o fact, when the channel length is longer thau one n f
micron, either using a procfuct term or a summa$ term i the deoormnado of (5.19) hrs vay 'on n r

little difference, 8s far a the (wwzy~y concerned.This is shown i F .5.7 where S i m U l d s is n g

drain aments for both appmaches are compared t measured data for a device with o

, T

8.6nm and

15pm. 'Ihe dots are measured data and the curves are simulations. The

difference between the two simulation results is negligible. However, as the channel length is

reduced, velocity saturation effects become more important and simulations from the summa
tion approach becomes more 8ccuTafe than the multiplication approach as shown i Fig. 58, n

where measured and simulated 1~

- Vm characteristics for a quarter-micron MOSFET are

l'hus far the drain current formulation of BSIM2 i the strong-inversion region is similar n
to that of BSIMl listed i (5.2)-(59) except for some minor modifications. Since the h o m i n
nator in (5.19) i different fmm that in (52),the expression for V, s

in (58) should be changed

to (520) accordingly.

Fig. 59 shows messured and calculated Im V,

an n-cl~annel MOSFET with
= 025pm and , T

chmckxistics in the hear region for

8.6nm. The asteaisks are m a u e data esrd

and the solid m e s axe simulation results. 'Ihe dashed w e along V,

- OV

shows the fesult

the impor-

if (5.17) is used instegd of (5.18) i the drain current equation, (5.19),-e n x

tance of the second-order term of the mobility mhction effect in (5.18). Fig. 5.10 shows
meaSured and calculated Im

- V,

charadcristics in the sahuation region for the same device.

Similar figures for a pchannel MOSF" with

OApm and , = 75nm are shown i Fig. T n

-5

-l22can

5.11 d 5.12. More

alsQ bcfoundin [5.11]

Tox= 86
-PI-

15 .

Fig. 5.7

c o m p r h n of modeling results betwan a d o n term md a produd te!am i the denominapor of Eq(5.19) for a "longer" c h d device. n

Summation Term

3
w
M

13
1

Tox 86
- I . - . -

5 0.25

Product Term
2
.%

vm 0
K . 5.8 g

-124-

50E-06

0.8

-6

1e 2

1.8

2.4

Gate Voltage

(V)

-125-

40E-04

Lea

NMOS
0.25 p m

Gate Voltage

(V)

Fig. 5.10

BSIM2 modeling results i the saturation region for an nc n -asterisks are m

device. ?he

d data and the solid lines are the modd.

ToX 75

PMOS

OOE+000 . 0

L
-.8
-1.6
-2.4

-3.2

-4.0

Gate Voltage

(VI

fig. 5.11

BSIM2 modeliog results i the l n a region for a bchmnd &via.'Ibe astaL n ier i h =measured dataand t solid lines are the model. s k

-206-04

-16E-04
n

A 7 ToX 75 = Wa-5pm Lea 0.4 p m

PMOS

00E+00 0.0

-.e

-1.6

-2.4

-3.2

- 4 .0

Gate Voltage

(VI

Fig. 5.12

BSIMIZ modeling results i the satudion region for a pchannd device. 'Ih+ n asterisks are measured data and the solid lines are the model.

chap5

-128

5 . Subthreshold region 32
Ihe drain current in the subthresholdrrgion is *y b
thcdifFusion~ [527].

Uig the chargashed approXimation [528], the subthreshdd currerd of a MosFEf cm be sn

exHesd=

A quick derivation o (521) is given in Appendix C However, Eq.(521) w n not be directly f

used unless & can be expressed as an explicit function of the terminal voltages. A relationship
between the gate voltage, Vm,and & has been dexived in [5.27], but it is too ooolplicaded t o

be used in circuit analysis. In BsIM2, a simple appmximation is used which will be d e s c r i i

below. Fig. 5.13 shows a plot of & vemus V a

analysis. It is found t ak h l

- Vm

calculated froin lwo-&mensionrd

in the subthreshold region c811 be axumtdy approximated as a

hear function of, V

with slope nV, and y-intercept -V, as drmn by the dashed in i fig. n

5.13.

where n is the subthreshold swing coefficient givm by

GI

n=l+C,
and

(525)
A detailed derivation of (523)-(525) cm ills0 be found in Appendix

substituting (523)

-129-

i t (521), the subthreshold curzeaf can be mvntten IS no

Eq. (526) can further be simplified t yield o

where all the missing tenns i (526) are incorporated i t the fitting panmetex V n no ,,

which

accounts for the threshold voltage o f e between strong-inversion and subthreshold regions. fst

e. e

I. I )

2 .I)

3.8

1) .

f. I

S G '

-vFB

Fig. 5.13

Surfixe potential versus gate voltage. ?he dashed line is a hear approximation
of the d a c e potential i the subthreshold region. n

chap5

-130-

533 Transition regiao

(A) Inversion-layer m t m c c d k t
When the gate oxide thiclrness becomes comparable t the depletion-layer thickness 8s i o n

in most deepsubmicrometer devices, the inversimlayer czptxiw effect is no longer negligible and has to be included i MOSF" modeling especially for low gate vdtage operdoos. n

Fig. 5.14 shows calculated inversion charge density as a fuection of the gate voltage f r a , o T
=

8nm device. ?he stmight line in the same figure repnsents the usual linear approximation

given by &(V,-V&.

Because of

the inversimlgra

capacitaoce &ea,

the inversiall

charge density deviates from its linear approximation when the gate voltage is near the tbshold voltage. ?his deviation increases as the gate oxide thickness decreases. Although the

drab

current equations in both the mng-inversion

and the subthreshold regions can be

derived, there is no simple analytical expression for the drain currenf near the threshold vol%e-

In this m, &
o , fV

a transition region between the strong-inversion and the subthreshold

regions is determined. ?his transition region is marked i Fig. 5.15. A cubic spline function n
is created for this region t axamt for the inversion-layer capacitance effect. Ihe o

upper and lower bound of the transition regiOn can be dculated from the equivalent Circuit

shown in H .5.16. The effective gate cap9citance Ch o a MOSFET looking i t the gate g f no
terminal is equal t C,i series w i t h a . o n

(5W
where

C, is defined 8s W d k and can be

expressed a (529) in the subthreshold region s

Using the same approach used in the chivdon o (527), f

& cau be approldmatad as

-131-

50.8

0.0

.0

1.2

1.6

2.8

Rg. 5.14

Channel inversion charge density versus gate voltage calculated iium t w e

dimensional analysis. 'Ihe straight h e is the usual qproximation given by cdV,-V,)*

-132-

lo4

4
w

1-' 07

m CI

100
0.4

0.8

12 .

16 .

2.0

Hg. 5.15

I>rain ament V~ISUS gate voltage in logarithmic scalei illustr&g the smooth tmsition from subthreshold region t the strong inV&on region. o

Fig. 5 1 .6

Equivalent capacitance circuit of a M O S m looking into the gate.

-5

-13%

~n stmng-immsion region, the

c is lul~h tfian G, o r e , C&G.TES is larger w

i valid. In the subthreshold region hows

where the linear appmxim&ionQ,<(V=-Vth)

ever,

, is much larger than &. 'Ibis is where the cliffusion current dominates* BycornparC bg the relative magnihrdes of C, and & dong V=,the thelowerboundVa andupper
of the transition region can be determined. For example, if we define the Iowa
then Va wiU be

bound V,

bound to be at which C,-lOOG,

Similarly, the upper bound, defined a &,= lO, can also be calculated. t OC,

The width of this transition region ( Vm V a ) is about 02 03V depending on the oxide
thiCkLMXS.

An effective gate voltage

is created in this region by using a cubic spline function of

where the coefficieats

cunent equation

c are to be detearmned from the boundary conditions. 'Ihe drain s

v,.
his cubic * e

used in the eansition region i the same as that in strong-inversion region s

except V& is used

instead o f

function also serves a a means to s

acQuire a smooth transition from the subthreshold region t the strong-inversion region. Ihe o
reason t use V& for tht cubic spline function i this region rather than using the drain o n
CulIMt directly

is t simplify the boundary conditions. l l i s approach avoids the need to detero region drain curzent equrSions should be used

mine whether the linear region or the -00

at the upper bound

chap5

-134

A the lower bound, Vm Va,the bamdary conditions am t

and at the upper bound, V a

- Va,

the boundary conctitions

v;, =vc;z

Substituting (534) and (535) into (533), the coefficients of the cubic spline function,cs can

be determined. ?he solutions for these coefficients arc given in Appendix D .

(c) Modeling results The measured and calculated subthreshold char~~terktics an D and p-channel devices o f are shown in Fig. 5.17 and Fig. 5.18. In Fig. 5.17, three regi0as madred A, B, and C for the

, V

= OV a w e

indicate the subthreshold, transition, and sfroag-hversiOn regions when the

three different

drain ament equations wen uscd. A smooth transition between the regions is

observed.

-135-

h
W Y

Fig. 5.17

B S M modeliDg results i the subthreshold region for an nchannd device. n 'Ihc askrisks are m d data d the d i d lines are the 4 .

- 1E-a4
- 1 E-05

-1

E-09

i
V,--O.OSV

:
1

-1E-13

-0.8

-1.6 -2.4 Gate Voltage

-. 32

-4.0

(VI

fig. 5-18

B S M modeling I t s i the subthreshold region for a pchamd device. n The m s k s are rneasmd data and the d i d lines are the modd.

-137-

53.4 Output resistance modding

Although the outpt resistance & is m e of the most importmt perameters in analog c i ~

cuit designs, few MOSFET models can simulate & accwdy.

meal autput resistance

charactenstic of a short-channel MOSFBI' is shown in Flg. 5.19. 'Ihe shape of the artplt
resistance in the saturation region can be attdmted to three mechanisms: drain-induced barrier

lowering, channel -1

mocblation, and bot-electron induced cutplt resistance reduction.

In

m s MOSFET models, the drain-induced-eer lowering &ect is included in the threshold ot

voltage. In BSlM2 this efect is modeled by the q pammder, therefore in this section, only the other two effects will be discussed.
(A) Channel length modulation
When the drain voltage is larger than VmAT, the velocity saturation region extends

t w r the source, which effectively &ces oad

nel conductance (or finite R,,J

the channel length and results in a non-zero chan-

in the saturation region [5.29,530]. A schematic diagram of

the channel length modulation is shown in F4g. 520.

Channel length modulation is the dominant mechanism affecting

& when , is near V

increases.

,,V

This effect is usually implemented i the model through the Bo parameter. BecaPrse of n

the reduced channel length, the chaunel conductance coefficient, BO,increases as , V

where & is the chanael length reduction due to the channel length modulation &e&
According to a quasi-2D analysis [531332], LyaM is zero when the drain voltage is less

than VmT ahd increases logarithmically with , V

adter Vmp

A qualitative r d t of the

quasi-2D analysis is plotted by the solid a w e in Fig. 521.

empirically that the combinatian of a h+c

In practice, however, it is found

taugent function and a quadratic functjon is

more ac<wate and approPriate t model & when, o V

is near V ~ T .

-5

-l38d d e n t s extraded at linear md -on

regions,

when Bo and B 8 8 c the amdu=q=tivelY, I%, 4B4 B2,

fittiog paraneta, ad Br

8,-(BO+4Vm-P,Vib.

A*-

M v e sketch (537) is plotted by the dse curve i F .521. In (537), the cnhdmce a d h n q
coeffideat @ starts to increase from , V

0 which is Merent f o the @2D rm

"he e of each f&

dysis.

Eq. (537) also eliminates the aiscontinuity problem a Vmp t

(537) on the shape o f

in

& is indicated i Fig. 522 which atso rev& the mems in which n

these parameters can be extracted from meanued data

As the drain voltage increases beyond VmAT, the peak e l d c field i the velocity n

saturation region increases sharply and electron-hde pairs are generated due to impact i&
tim [533,534]. 'Ihe holes generated are collected by the substrate is referred t a the sub o s

strate wrent Ism. When the substrate ament flows through the substrate, it slightly forward

biases the source junction with respect t the substrate becau~e the ohmic voltage drop VI, o of
( I s d m ). ?his positive body bias (for NMO6) reduces the thrtshdd voltage camsing the drain current to increase and in turn ckgndes the outplt resistance [53]. This process i dep s

icted i Fig. 523. Therefore, to the first-0rde.r apprordmatioa, the d t a n t drain d o n n

current I

k T due to the hot-electron effects caa be expressed a s

wee I hr

~ is the Qain saturation current without hot-electron effect & a by (5.6), &UB i T e s

the effective resistance of the substrate, and C is a constant. Substituting the substrade cumat
equation, (324),

into (538), Eq. (538) can be rewritten ES

where A, and

are impact ionization wcffidents. Under n o d bias ConditiOnS, the second

term i the brackets is much smaller thm OM, henct (539) has very little e f k t on the magnin tude of the calculated drain current, but it has Significant e f c on the output resistance as will fet

-139be shown later.

-- .

10E+e+

Triode Region

. -

Saturation Region

80E+03

Effect

68E+03

e cr a #"
v

40E+03

20E+03

00E+00

i1.
***

d
I

&I
I

* I

.
06

0.0

Fig. 5.19

weal a u p t resistance characteristics of a shortchannel MOSFET.

-140-

Fig. 520

A schematic diagram showing the chamd le@

tm&lation & t a.

Posat

VDSAT
Fig. 521
versus drain vdtage. The Qualitative plots of thc conductance coefficient solid tame is the d t of a quasi 2-D analysis and the dashed curve is the

B S M 2 model.

-141-

Drain Voltage

Fig. 5 2 2

resamce vetsus drain voltage showing the effects o various f parameters on the shape o the outpt re&tance. f

BSM2

-142-

Rg. 5 2 3

A schematic diagram showing the process of outpt xtxktance rexbction due t o

hot-elcdron dccts.

-143

Fig. 524a b

s measured d calculadbd I=

- V=

characteristics of a quarter-micrOn
~wzf-

n-channel MOSFEI: The comqxmchg autpt resistaxe i shown in Fig. 524b. 'Ihe s
rate Ins and

& modeling

results make

BSIMIZ highly suitable for both digital and a d g no

applications.

As illustrated i the design a w e s developed in chapter 4, hotelectron reliability has n

becume the major concern in deepsubrnicnweter device.and circuit design.

T predict the o

device Iifetime andor aged circuit behavior due to hotelectron &ects have also become one
of the design steps i VLSIKJLSI systems. Recently, various activities in this area have bees n

reported [535-5381. More programs are expected to be developed in the future. In these pro-

grams, model parameters f o both fresh and hot-electron stressed transistors are usually rm
required. Therefore, a MOSFET model for the future s h d d serve well for this pupose. To
ts BSIM2's capability i modeliog stressed devices, the device used in Fig. 524 was p et n r

posdy degraded by hotelectron stress to generate a threshold voltage shift of 022 volts, then model parameters were -r

from this device. "he modeling results are shown in Fig.

525. Again, very good agreement between measured and calculated Im and & are observed
which proves t a BSIM;! is also a potential candidate for Circuit aging related simulations. ht

Sne the LDD structure has become common in ament technologies,a MOSEET model ic
will not be useful if it fails to model LDD devices. BSJM2's capability i this aspect is n
verified in Fig. 526 where m a u e and calculated I= and esrd for an LDD transistor are

shown. Fnly the modeling d t s for a non-LDD pchaanel transistor are shown in Fig. ial,
527.

-144-

2.K-83
I

T = 8.6nm ,

NMOS

---

---

Drain Voltage (V)

Fig. 524

(a) BSIM2 I=

mo&ling results for a quarter-micron n-channel d v c , eie The asterisks arc meErmnd data and 0) CorresPoMhng cwJut the the solid lines are the modd.

-, V

-145-

2.61V

183V

Drain Voltage (V)

Fig. 5 2 s

BSIM2 I= V= modeling results for a quarter-micron n-channel device after hot-e!ledr~n stnss. 'Ihe threshold voltage shift is 022V. (b) thc coxresponding outpt resistance. 'Ihe &sks are meamred data and the sdid
(a)

linesZU!5thCmodd.

I.t s*

T = 125nm , ,

NMOS

n
Y

4
w

cB.Ic41

6
. cc.eE-83. -

tl L

4.06V 3.12v

ii

2.17V

8.0

1 .8

2.a

3.8

4.a

Drain Voltage

(v)

Fig. 526

(a) BSlM2

- , modeling results for tm OGhannd LDD device, (b) the V corresponding cutpt resi-. The d s k s are measured daka and the d i d

linesaretfitrmdd,

-147-

e
v

Fig. 527

(a)

BsTM2 - Vm modeling d t s for a p - c h d &vice, (b) the corresponding outprt resistance. 'Ihe d s k s am measured data and the d i d

-1485 3 5 Bias-dependent parametaJ

So far, 18 S 3 2 parmetes havekm descxihd. SaneoftheseparaDetas rae f a d I4

to be slightly biasdependent which are approximated by liocar imcticms of biases.

these

AU of

dong with the equations danonstratiq their b i a s d e p e m a e ~ listed are

below.

1 7 . 4 = & + Ag 18. Bj Ba + Bg

Note

that the

biasdependencies of prametas 5 and 15 arc H e r e n t from those in BSIM1.

They are more physical now. & and &)in (5.14) have been @aced by VI and Urn,

-149-

respectively ESin BSIMl, wherc &=-.

53.6 Size-independent parameters

'Ihe parameters extmted from a ts device only pertain to that particular device size. et

'Ihe parameter set for each device size i r e f e n e d to s

a "parameter

file". Several Siza

dependent "parameter files" can be procased to generate a set of S i d e p e n d e n t parameta

called a "process file". The equation used in BSIMl to generate the "process file" is given in
(5 . ) a.

pw p(4,WJ =Po +-PL +-

Wi

where P , WJ is a parameter for a padcular effective length 4 and width W ,Po, and Pw & i PL
are the sizeindependent parameters. A schematic dirlgram o this proudme is shown in Fig. f
528. The Size-independent pparanetrrs arc generated by f t i g parameter files with different itn

device dimensions (Lt's and W<s) (5.40). Once PO,PL and Pw ace known, the model to parameten for a device with any channel length and width can be calculated from (5.40) by

replacing 4 and Wi with the desired dimensions. Detailed description of this procedure um be
found i [5.11]. n Although (5.40) does not wo& wdl wheo the rmge of the device dimensions i w d ,for s ie exampIe~>lO,itisstillkeptinBSIM2forthetimebeing. Ifawiderangeofdevice dimensions h s to be used in a circuit design, breaking the process fde i t two or more proa no
cess files with d e r device dimension m g e s is recommended. Studies on improving (5.40)
areundexway.

-150-

Para. file1
Ll9

Para. file2
L9 2

Para. filen
Ln, Wn

Wl

w 2
m m m m m m m m m m

P=P*+-

PL
Leff

+- PW
wf ef

Process file

-151-

5.4 Parameter extraction for BSIM2

An IBM FGbascd integrated system has been develqzd for autom&cd d o n o f
BSM2 parametas. In this section, only a g m d ov&ew o the system is dcscn"bcd. A f

cunplete description ofthepram&erextraction systan,useiS guide$ a n d c x q i e s aregival

m [S.ll].

5.4.1 Automated parameter extraction system

A schematic diagram of the system hardware i shown in Rg. 5.29. "his system Consists n

of three major parts: an IBM PS/z (model 50 or higher) or a CAT complter with a VGA
graphics card running under

Dos 3.0 or higher @os 4.0 or higher t enable VGA screen o

dump), an HP4145 paramebic analyzeryand a manual probe s a i n An IOtech GP48812 intertto. face board is required in the computer t Commuoicrde wt the HP4145 parametric analyzer. o ih

The extraction program is written i Microsoft C veasion 5.1 wt d e d IOtech Pern ih sonal488/2 modules. 'Ihe executable code is about 310KB. @) systan operation

Fig. 5 3 0 shows the flowchart of the parameter extraction progtmn. The program is
m d l r and menu-driven for easy operation and future modification. 'Ihe only required useroua
supplied inputs are the device dimensions, dit location, supply voltages, and the SMU

(Stimulus-Meawement Unit) Connections for the HP4145 pammekz andyzer. 'Ihe functions
of the parameter extraction system are grouped into two categories: single device mode and

multiple device mode. In the single device mode,parameter files are extraded from each device. In the multiple device mode, a process file is created hnn user selected parameter fls In ie.
either mode, calculated I-V charaderistics cau be

displayed togethex with measured d t s for

comparison. Dwice I-V data caa be either meawed directly from physical devices thruugh
the Hp4145 p a r a m h c analyzer or read back from a hadfloppy disk. If the

I-Vdata are t o

-5

-152-

and the last two data sets are used t extract cupt-resistmcc related pamnetm, (537>(539). o
The playback featwe of the program then allows the usen to check the quality of the extractbd

parameters for each device. 'Ihis extraction process is repeaded every time the single device
model operation is executed. ?he total extraction time for each device is about 20

- 30

seconds without measurement and about 2 minutes with measurement on a PS/2 Model 50
computer. After a few devices have been extracted, a prows file may be created.
5.43 Extraction algorithms
?he most commonly used technique in parameter e m t i o n i the nonlinear global aptins

ization [539-5.421. Although global Optimization will give the minimum avenge emr
between calculated and measured results, the extracted parameter values may not be physidy

meaningful which makes interpolation or extrapolation o parameters for other device f

sions very difficult and unreliable. Also, the optimization processes are usually slow, since the
compltation time incresses drastically with the number o pametem. Most o al if some f f l,

parameters are mutually correlated in the model, the o p h h t i o n plocess becomes difficult to

m e r g e o may d r

t i non-uniye solutions. n

V r o s auxiliaoy aiu

me&~ods such

LIP

Levenberg-Marquardtmethod [5.43,5.44], modified Gam method [5.45,5.461, and the steepest

descent mehod I5.471, etc., are incorporaded i t the global ophhation process t expedite no o
the convergence

or to midmize the effect of parametex redun-.

'Therefore, parameter

extraction programs adopting the globat optimization technique are a w y quite corzlplicatcd. las

i t
manual

probe

station

IEEEWBUS

r]
I

HP4145

Iprinter

I SMU1-4

Hardware Platform
IBM model 50 (or higher)
IOtech GP488/2 interface board

HP4145B parametric analyzer

VGA graphics capability

Parallel Printer

- U n t v l z t p1a m e k n u
Safyfatlon Realon Parameter ExtractiQn

8
lkxtrad subthreshold Parametem

Putbut Resistance Paramter E x t r a c w

Fig. 5 3 0

Flowchart o the BSIM2 f

cxtnxtim Prognm.

-5

-155Ihe to the mathematically compgcf functiooal forms d the BSIM2 modd, a l d Optimi-

zation technique together with a physi-

paranetrr extrtajon method am be anplaysd

t extract BsIM2 parameters. Becalse no sophisticated algorithms m needed with this o

appaoach, the pameter extraction progran can be easily implement and the pmmctas
extracted are also more physical and reliable than those fn>m global 0pthhtior.w.

Wh local i t

opt;m;zatian, d y two or three param&s ate cxtracted at atime under a certain bias condition

and the optimization process is qeated t cover al upemtion regions until all of the parama o l
texs are extracted. Since only two or three parameters rn optimized each time, the o p t i n k
tion p m s

is very fast. ?he nonconvergence and non-uniqueness problems usually do not

exist.

In the BSIM.2 parameter extraction program, the only 0pt;m;Zation process is a combina
tion of Newton-Raphson's iteration and a linear least-square fit routine with two or three vari-

able.~. "he flowchart of the opt;m;zaSion process is shown in Fig. 531. The model equations
are first arranged in a form suitable for Newton-F&phson's i e a i n as shown in (5.41). trto

(5.41)

w e e fo is the function t be optdzed, Pl, P2, P are the parameters to be extradcd, PlW hr o and 3

Pb, and Pk stand for the true parameters that we are looking for, Plm), Pim),and P$")
represent the parameter values after the m* itemtion. III mi case, the function fo may be the

drain current equation or is variational form, and f(Plo,PbP& would be measured I-Vdada t
To make (5.41) ready for the l n a least-square fit routine (a form of y =a+bxl +cxz), both ier
sides of (5.41) arc first divided by 8f/8Pl. Thea the measured I-Vdata are fitted to (5A1) and
the increments of parameteas for next iteration, L
P ~ ~ ~are ,determined, S

be prameta value^

for the (mg)* iteratia are given by

pi"' =pi'"' +&p)

i=1,2,3

(5.42)

'Ihis procedure is qeated until all bpi's are smaller than some p n x b m ed values, at this * ~ ~ ~

point the o p t i n h i o n process is considered converged.

chap5

-156.

ple shawing how tbe optimjzeaioapmccss is pllyskdy applied. Exst o d, drain culzmt f the
equation i the linear e o n (5.19) is matmged i such a fann suitable for (5.41). n n

where G = I&Vm is the measured chanacl condudmce.Tbe Q , V

termin rhc demunm& r *

of (5.19) hm been dropped in (.3, since Vm is & (0.1V) compared to Vm. S~bstit~tiag 54)

(5.43) i t ( . 1 , the equation used in the Newton-Raphsonsiteration can be obtained no 54)

where

(5.45)

and
-=

v-*-, ,v-v

During each iteration, the same measured 1 ,

- V a dppa are fitted through (5.44) to d d a t e

&?Am), &Jim), and

for mxt ite,ratioa. Ihe itemtion is tPrmjnaied when the increu~eats of

all three patameters arc less than 0.01% o their ammt values o when a preset maximum f r

iteration numbef i reached. s

For each substrate voltage, a set of Bo, Vu ad I& arc extracted. Ihese pammeter vducs
may exhibit slight substrate birr, ckpdemc and are fitted through ahear equation a listedh s
section 535 t extract the subsmte-bias dependent parcanetess. o

-157-

Initial estimates of parametas P, ,

<
Model quatiorw

calculated values
v

Measured data
*
fi

Linear least S q w
3

fit routine
1

Fig. 5 1 3

-158-

5 5 SPICE simulation results

The BSlM2 model has been in.@&

SPIcE3.Cl. A program list of

r

the

BSIMevaluate.~module, w i h evaluates the BM model expaions i SPI-, hc S n

Appendix E An cxBmple of SPXCEiaplt deck with BSlM2 model m

i giva i s n

s i shown i s n

Fig. 532. BSIM2 model has been used to simulate an NMO6 cahmementdpletion type
ring oscillator with , = 8.6m and T

OBpn The simulaled delay time is 24ps/stage,

very close to the measured data of 22ps/stzige. The

8 c ~ l l 8 c y the of

BSIM2 model has been demonstrated in section 5 .More results 3

can be found i [5.11]. In this section, the computational efficiencyof the model is discussed. n

Table 5 2 shows the comparison of SPICE simulation times required for BSIM2,level-l, and

level-2 m d l on two typical circuits. The device dimensions used in the simulation were , oes T
= 25nm

and &

2pm for level-1 and level-2 models; T,

= 8.6m

and & 025,05, and

0.7pm for BsIM2. The parameten for level-1 and level-2 models are tpcl values for 2-p yia
technology provided by MOSIS.

'Ihe first simulalion is a DC aaalysis of five I=

-, V

charaderistics. Althaugh the

oe o evaluation time of BsIM2 model itself is slower than that of level-1 m d l and comparable t
that of level-2 model, the total cotuptation

times required for BSlM2 in this simulation i s

similar t that of o

level-1 mode4 a d twice as fast 8s that of level-2 model. This is bezause the

number of i e a i n needed in the simulation for BSIM2 is less than those of the other two trtos

models due to BSIM2's smoother functional form. Ihe total number of iterations for each mc&l are also shown in Table 52. The second simulation is the traasient analysis of a 15-

stage CMOS ring oscillator. Similar results w e n also observed. More simulations on analog
circuits aTe mdemay.

chap5

-159-

11-STAGE CMOS RING OSCILLATOR WITH TOX-86A AND LEFF-0.3UM .SUBCKT INV 1 2 3 c1 3 0 0.1P M1 3 2 1 1 PMEN L-0.3U W=30U AD-lZOP AS=75P PD-36U PS-6U M2 3 2 0 0 NMEN L-0.3U W-15U AD=60P AS-37.5P PD-23U PSm6U .ENDS INV x1 21 2 3 INV x2 1 3 4 INV x3 1 4 5 INV X4 1 5 6 INV X5 1 6 7 INV X6 1 7 8 INV X7 1 8 9 INV X8 1 9 10 INV x9 1 10 11 INV x10 1 11 12 INV X11 1 12 2 INV VDDl 1 0 4.0 VDD 2 1 0 PULSE(0 4 . 0 0 0.5N 1N 500N) .TRAN 60P 60N .PLOT TRAN V ( 2 ) .PRINT TRAN V(2) .OPTIONS VNTOL-1E-5 ABSTOL-1E-9 ITL4-50 + CPTIME-lE4 RELTOL-0.01 CHGTOL-1E-12 PIVTOL-1E-29 ITL1-500 ITL2-500 .OPT ACCT .WIDTH OUT-80 .model NMEN nmos level 4 + vfb -1.0 lvfb 0.0 W f b 0.0 + phi = 0.889 lphi 0.0 wphi 0.0 + kl = 0.93 lkl = 0.0 wkl 0.0 + k2 0.125 lk2 = 0.0 wk2 = 0.0 + eta0 0.017 letaO 0.0 w e t a O = 0.0 + etab = -0.007 letab = 0.0 wetab 0.0 + mu0 = 327.3 dl = 0.0 dw 0.0 + muOb = -8.42 lmuOb = 0.0 wmuOb = 0.0 + musO = 431.8 lmus0 0.0 mus0 = 0.0 + musb = -7.4 lmusb 0.0 wmusb 0.0 + mu30 = 15.1 lmu30 0.0 mu30 = 0.0 + mu3b = -1.34 lmu3b 0.0 wmu3b = 0.0 + mu3g -2 lmu3g 0.0 wmu3g 0.0 + mu20 = 2.37 lmu20 0.0 wmu20 0.0 + mu2b = 0.09 lmu2b 0.0 wmu2b = 0.0 + uaO = .443 luaO 0.0 m a 0 = 0.0 + uab -0.025 luab 0.0 wuab 0.0 + ubO 0.075 lub0 0.0 wubo 0.0 + ubb = -0.0076 lubb 0.0 W b b 0.0 + u10 0.18 lul0 0 . 0 wul0 = 0.0 + ulb = 0.00014 lulb = 0.0 wulb = 0.0 + nO = 1.125 In0 = 0.0 wnO 0.0 + nb 0.35 l n b 0.0 w n b = 0.0 + nd -0.017 lnd 0.0 wnd 0.0 + vofO = 1.16 lvof0 = 0.0 wofO 0.0 + vofb = -0.034 1~0fb 0.0 Wofb 0.0 + vofd -0.069 lvofd 0.0 Wofd 0.0 + ai0 332.68 laiO 0.0 waiO 0.0 + a i b = 108.55 laib 0.0 waib 0.0
AN

--

- --- -- - -9

--

+ b i b = 2 . 9 2 l b i b = 0.0 w b i b 0.0 + v g h i y h = 0 . 2 3 2 lvghigh = 0.0 wvghigh = 0.0 + vglow = -0.114 lvglow 0.0 wvglow = 0.0

biO = 2 4 . 6 2 lbiO = 0.0 ubi0 = 0.0

+ t o x 8.6e-3 t e m p = + cgdo = 2.0e-10 cgso

+ xpart = 0 + r s h = 1 0 c j = 0 . 0 0 0 2 cjsw = 1.0e-10 + js = 5e-5 pb = 0 . 7 pbsw = 0 . 8

27 vdd 3 vgg = 4 vbb = -3 2.0e-10 cgbo 5.0e-11

+ mj 0.5 mjsw 0.33 wdf = 0 + dell 0 .model PMEN pmos l e v e l 4 + vfb -1.0 l v f b 0 . 0 wvfb = 0.0 + phi 0.889 l p h i = 0.0 w p h i - 0.0 + k l = 0 . 9 3 l k l = 0 . 0 wkl 0.0 + k2 = 0 . 1 2 5 l k 2 0 . 0 wk2 0.0 + e t a 0 = 0 . 0 1 7 letaO = 0.0 wetaO = 0.0 + etab = - 0 , 0 0 7 l e t a b = 0 . 0 w e t a b 0.0 + mu0 131 d l = 0 . 0 d w = 0.0 + muOb = -3.42 lmuOb = 0 . 0 wmuOb = 0 . 0 + musO = 1 7 3 . 8 lmusO = 0 . 0 wmus0 = 0 . 0 + musb = -3 l m u s b = 0 . 0 wmusb = 0 . 0 + mu30 = 6 . lmu30 0 . 0 wmu30 = 0 . 0 + mu3b = - 0 . 6 lmu3b = 0 . 0 wmu3b = 0 . 0 + mu3g = -0.8 lmu3g = 0 . 0 wmu3g = 0 . 0 + mu20 = 2 . 3 7 lmu20 0 . 0 wmu20 = 0 . 0 + mu2b = 0 . 0 9 lmu2b = 0 . 0 wmu2b = 0 . 0 + uaO = . 4 4 3 luaO = 0 . 0 wuaO = 0 . 0 + u a b = - 0 . 0 2 5 l u a b = 0 . 0 wuab 0.0 + ubO = 0 . 0 7 5 lubO = 0 . 0 wubO = 0 . 0 + u b b = -0.0076 lubb = 0 . 0 wubb 0.0 + u10 = 0 . 1 3 l u l 0 = 0 . 0 w u l 0 = 0 . 0 + u l b = 0,0001 l u l b = 0 . 0 w u l b = 0.0 + nO = 1 . 1 2 5 I n 0 = 0 . 0 wnO = 0 . 0 + n b = 0 . 3 5 l n b = 0 . 0 w n b = 0.0 + n d = - 0 , 0 1 7 l n d = 0 . 0 wnd = 0 . 0 + vofO = 1 . 1 6 l v o f O = 0 . 0 wvofO = 0.0 + vofb = -0.034 l v o f b 0 . 0 wvofb = 0.0 + v o f d = -0.069 l v o f d 0 . 0 wvofd 0.0 + a i 0 = 0 laiO = 0 . 0 w a i O = 0.0 + a i b = 0 l a i b = 0 . 0 waib = 0.0 + biO 0 lbiO = 0 . 0 w b i O = 0.0 + b i b = 0 l b i b 0 . 0 wbib 0.0 + vghigh = 0.232 l v g h i g h = 0.0 Wghigh = 0.0 + vglow -0.114 lvglow 0.0 wvglow 0.0 + t o x = 8.6e-3 t e m p 2 7 vdd = 3 vgg = 4 vbb -3 + cgdo = 2.0e-10 cgso = 2.0e-10 cgbo 5.0e-11 + xpart 0 + r s h = 0 c j = 0.0002 c j s w = 1.0e-10 + js = 5e-5 pb = 0 . 7 pbsw = 0 . 8 + m j 0 . 5 m j s w = 0 . 3 3 wdf 0 + dell = 0

--

--

.END

Fig. 532

An exEpLlplc of SPiCE3 inpt deck for an 11-me CMO6 % oscillator with

RsMparametes3.

-161-

SPICE Simulation Results

Measured delay time: 22psktage Simulated delay time: 24psktage (NMOS E-D ring. osc., Tox=8.6nm, Leff=0.25um) Model

I Level 1 Level 2BSIM2 I BSlM2 I BSIM2 250 250 I 86 I 86 I 86

I
I I

2.0 2.0 0.25 0.5 0.7 DC Ar alysis, Id-Vd characteristics Circuit 1.51 2.80 I 1.55 I 1.49 I 1.52 Time (s) Iterations1 113 111 I 71 I 71 I 71 TRAN Analysis, l5stage ring osc. Circuit Time (s) 1 185.4 ----- 173.7 142.7 152.6 342 369 Iterations1 576 1 ----- 435

-1

Table 5 2

Comparison of SPICE simulation times between the BSIM2 model and level-1, level-2 models.

-162-

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d P. Yang, "An BKcient Algorithm for the Ekhactioa

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and G E Dorda, "v-E Dependence i S a l S z d MOS Tassos" n ml-ie rnitr,

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[5.45]

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-167-

Chapter 6

CONCLUSION
High current drive, high pdring density, and high integration levels have been the motivations i MOS scaling. &e t the resolution o optical lithography, the minimum MOS n o f

FET channel length was limited t the range of near micron. W h the advent of X-rgr lithogo i t
raphy and

S h direct-wnte technique, MOSFETs wt channel length a small 8s 0.1pm ih s

have been demonstrated However, these techniques are v e q expensive and are incompatible with existing technologies. In this work, a photoresist ashing technique has been developed which, when used i conjunction With conventional g-line optical lithography, permits the CODn
t o l d defbition o the gates o deepsubmicrometer devices. Since most polymer-based resist rle f f

material are ashable with oxygen p a m , this photoresist-ashing technique can also be lsa extended to supplement other lithographic processes, such as those of e-beam and X r y -a.

As the device dimensions arc scaled Mow one micron, shoxt-cbannel ef&

and other

second-order effects become more prominent. To design and model deepsubmicrometer devices, the physics of these dewices has to be reexamined and understood. Studies based on the

performance and reliability have shown that the basic physics associated with deep
submicrometer devices is similar t that o t& long-channel counterparts. Therefore, existing o f h design guidelines and models can still be applied with the need only for minor modifications.

In this work, various design awes for deepsubmicrometer devices have been generated
hm experimental results based on the following Considerations: short-chmd and dnib

indu&barrier-lowahg

efects, punchthrough and gabinduced drain leakage currents, hot-

electron reliability, timo-dependent-dielectric breakdown, current-driving W t y , voltage gain, and switching speed. It is fd for an effective channel length of 03pm, the maxthat

i u dowable power supply is 3V,which h@.ies that some kind of hot-ekc~resistant mm

structure is

stiU desirable for OJpm technology w t 33V power supply. ih

cbap-6

-168-

Wh the d r m c increElse in the number o traasisdon pu chip, the circuit Complexity l t f

and the fabrication cost also increase proportionally. In order to speed up the VLsVtRsI system design andtorsduce costs, it hasbecomeoecessary t start the circuit design inthccady o
stages of technology development and to predict circuit M o r before the circuit is actually

fabricated, both of which require intensive use of c r u t sirmlators. Since the device c h m e ici

t x s i s o small-geometry devices am highly sensitive t m eitc f o

r variations, optimal circuit

designs become even more difficult t create than bdon. Iherefon,m EIcw8dt and complta o tionally efficient drain current m d l for deepsubmicrome& MOSFETs becomes extremtly oe cmcial and indispensable in developing fuhue system designs.

In this work, a MOSFET drab current model suitable to predict s a l geomeq effects ml
for size as small as quarter-micron channel length, for digital as well as analog applications is developed. In developing this m d l meticulous care has been taken in retaining the basic oe, functional form of fully physical models while improving model
8c<w~cyand

compltational

ao efficiency. The ease of parameter extrxtion was also a m j r mnsi&ration. In dditim to the
effects commonly included i the MOSFEI' drain aurent equation, it i found that the n s

inversion-layer capacitance effect, hot-electron induced output resistance degradation, and

sourddrain parasitic resistance effect are also important factors to consider in deep

submicrometex MOSFET modeling. This d e l has been hplemented in SPICE3. A p ter extraction s s e dedicated to this model was also developed. ytm

-169-

APPENDIX A

PROCESS FLOW
su5MIcRoMEIERNMa m (modified from MICROLAB CMOS PR single poly-Si, single mtal
Step 0 Starting Wafus: 15-30fh11, ptype, d 0 : o3 scribed SUBcl t o

m
version 3.0)

control wfr: aes PSUB (ptype) Measure bulk resistivity (Q-cm) of prime wafers on Sonogage. [NCIlZJ:Only amy out HF dips where i d c t d niae.

smo.

Step 1: Initial Orridation: target oxide 2OOangstrom

1 Standard clean wafers, include PSUB control: 2

piranha clean for 10 min, spindry.

1 3 Dry oxidation at 950 d e g d 3ohdryQ 20 m h dry N 2 Measured oxide on PSUB contrd. (Rework i oxide <SOangStrOm). f

Step 2: Field Implant (Blanket Implant): boron (Bll), 1 E U m , KeV 5 l c 270 Include PSUB control (no photoresist).
se 3: tp

Locos Pad oxidation/Nitride Depositioa: target thickness 250aagstmm SiQ + 1OOOangstrom SisN,

31 TCAcleanfumacctube. .
3 2 Remove all oxide i 1 l H until wafers &wet (including PSUB). n O F : Measure sheet resistance R, of PSUB control on pn>metdx.
3 3 standard clean wafexs.

34 Dry oxidation at 950 degree42 .

45mindryq

20 min dry N2 d. a) Measured oxide on PSUB control.

-170(Rework i oxide <18oaugstrom). f b) Strip oxide off PSUB control i BHF. n

3 5 Deposit 1OOOaogstromof Si-nit&dc immediatdy: Deposition time-22 min, temperature = 800 degnd=. Include S U B Contrd.
MeasuredTa(Make additional deposition if T Save R B control for Step 7. U
~~ ~~

<8OOaogstmm)
~ ~

Step 4: Active Area Photo uask:ND (emulsi@ -hydrate, HMDS, Spin, expose, develop, descum, hard bake.
Step 5: Nitride Rch Technics-C plasma etcher

[ w ]Rotate wafexs t insure unifom nitride etch. N 1. : o 2. Wet-etch oxide. (Check for dew& in field regions).
~~

5.1 Remove photoresist aod piranha clean wafers.

Step 6:

Loco6 Oxidation:

target oxide

3OOOangstrom)

6.1 TCA cleao furnace tube.

6 2 Standardcleanwders. No HF dip.
-~
~

6 3 Wet oxidstion at 950 degreeC:

5 d Q y 4 1 hour25minwttQ

5 h W 4

20minN2cmneed on a device w f r in the field a m . ae Measured oxide (Stop and consult if oxkk <25OOangstrom and check waferd o h t y ; stop and consult if oxi& variatian >SOOangstrom)
step 7: Nitride Removal (include PSUB mtd)

7.1 (bride dip i 25:l HF for 1 min. n

~~ ~

7 2 Etch nitride o f i hot phosphoric acid: 145 degreeC, 60 min. f n l 3 d point detection by dewet of PSUB contd.

73 Dip off sacdicial oxide (dewet) i 25:l H for 1 min. n F

Step 8: Sacri6dal Oxide Growth: target oxide

2Wangstnw

8.1 KA clean fumclce tube.

-171-

83 Dry oxidation at950 degrecC:

30ddtYQ 2omin*anneal a) Meawcd oxide onPSUB control b) Donot iOCludePSUB control in Step 9 t 12. o

Step 1 : Enhancement Implant: Boron (B11) a 30 KeV, 0 t

9 splits i implant dose. n

WaferSUBC-

I
I

6,lO

I I
oh = 5oang-)

h e (*lE12/m2)3.0 I

60 I 9.0 .

Rmme photoresist and piranha clean wafen aftex hplaut.

Step 11: w e t i o n Implant Mask M (chmmedQ align, q o s e , develop, Dehydrate, HMm, WUTEl: ?he exposure shouldbe increasedby 25% to for the dark field
-9

--

Step 12: Depletion Implant: Axsenic at 50 KeV,

9SplitSinimpiantdose.

Wafer SUBC-

I
I

I
I

6,lO
12

1
I

b e (*lE12/cm2) I 20

14

vat - 5oang-)

-172-

Remove rcsist and piraoha clam w f r after implant. aes

Step 13: Gate Oxidation/Pdy-Si Depositioa: target = 25angstrom SiQ + 2500mgstrom poly-Si for w f r SUBCl-3 aes target = 50angstrom SiQ + 2500sngstrom poly-Si for SUBCA- aod SUBClO target = 75angstrom S i Q + 2500mgstrwn poly-Si for w f x SUBC7-9 aes

13.1 TCA clean furnace tub, reseme *-Si 132 Standard clean wafexs,

deposition tube.

include new monitor w f r Toxl,'IDX2 and TOX3. aes

133 Dip off sacrificial oxide (dewet) in 251 H (approx. 1 min). F

13.4a Dry oxidation at 800 d e g r d Wafers: SUBCl-3,Tox1

target , T

25angstrom

5hdryQ

10 min N 8Meal. 2
MerrsurcT,=
onToxlcontrd.
135a Immediately after oxidation deposit 25OOaogstmm of

phosphorous-dopedpdy-Si. time = 1 hour 15 min, temperahue-650 d e g d [ o include Toxl contrd;hcluck a new N not D : o control with 1 O O O a n g s thermal SiQ on it. ~ Megsur~Twstop and consult i Tw ~2ooOangstrom T , >3OOOangstrcm) f or + ,
13.4b Dry oxidation at 800 degreeC SUB<;Q-6,SUBClO,TO7Q target Tar = 5Oangstrom 3ohdryQ 10 min N anneal. 2 Measure Tar = onmx colltrd.
~

1 3 3 Immediately after oxidation deposit 25OOaugstmm of

phosphortxwkpd poly-Si. time = 1 hour 15 min, b p r a t u m 650 degreeC [NUIEj: Do not include Tox2 control; include a new control with lOOOangst10m thermal S i Q on it. Mea~lre Tp.ly stop and c d t if Tw <2000a43stn>m or T , >3OOOangstrom) +,

-173-

13% Immediately d c oxidation deposit 25OOangstmm o tr f Phosphorous-doped PdY-Si. time 1 hour 15 min, tanperatun 650 @re& [Narq: Do not indude Tolo contd; include a new control with lO0Oangstrom thennal SiQ on it. M-TWstop and CoLlSulf i TW <2000aagstrom or T m >3OOOangstrom) f

Step 14:

Gate Definition Mask: NP (emulsion-cf) Dehydrate, MIX,spin, align, expose, develop. 1. Right before exposure, do a fms-exposure test for GCA wafer stepper to detexmine the best focus and exposuie. 2. Expose and develop. 3. Photoresist ashiog. 4 2 : BHF dip. .5l 5. Etch poly-Si in LAh4.

Step 15: Reoxidation: target oxide

15.1 TCA clean furnace tube.

200angstrom on poly-Si.

152 Standard clean wafers, include controls, 'NIX2 and Tox3. No dip i HF after piranha n

Step 16: N+ Source/Ixarn Implant

*

16.1 linplant Arsenic a Odegree inclination, 50 KeV, 3 E l 5 / d , t including 'TO=, and Tox3 controls.
Step 17:

N+ S / D Reoxidation and h e a l : target orride = 4OOaagskom on pdy-S

17.1 TCA clean furnace tube.

172 Staodard clean wafers, include TOX2 aod 'TOX3 mr td

Appendix24

-174-

[NCYEl: No dip i H after piranha. n F

17.4 Strip Tox2 and Tox3 conttols and me8surc sheet resisbnce ( / q ae on FkoxnCk ns u r ) Save aU controls in "comp>leted controls" box,
Step 18: Reflow

target oxide = 3OOOangstram

~ ~

18.1 Standard clean w f r (NUIE No H dip). aes F Include only one new, PSG control. 182 Deposit undoped LTO. including PSG control. Layers: 3000angstrom undoped LTO. time (approx) 15 min ttl (check current deposition rates) oa temperature 450 degreeC. Mea~ure Tps~ on PSG control.

- -

183 ~ ~ g I a s s a t 9 2 5 d e g r e e C include one PSG control. 20mindry4.

Step 19: Contact Photo Mask: NC (chrome-dl) Dehydrate, HMDS, spin, align, -e, HAND develop, desaun, bardbake. The exposure should be incresed by 25% t compensate for the dark field. o

Hand develop 90 seconds. One part Microposit developer, one part watn.

20.1 Dry plasma etch in LAh42 rnspfxt thoroughly.

Step 21: B f e Doped-Poly Depositio~ ufr

21.1 Remove photoresist and piranha clcm. 212 Standard clean widen: piranha clean for 5 min, followed by dip in 25:l for 15 stc. [ N W : fresh 25A HF solution. use

213 Immediately after spin dry, deposit 2000angstn>m o f

-175-

phosphorous-dopedpoly-Si. time=lhOUr,-650 & p e d Include a new control with 1OOOangstrorn thermal SiQ cm i. t M!fSSlWT*21.4 Wpoly actiVatiOa. h e a l waders i N2 at900 degreeC for 15 min. n

Step 22: Btxk S & Bch i

22.1 Spin photoresist (front side), Q not expose; hard bake.

222 Spin photoresist again, and hard bake.

~ ~ ~

223 Etch back side of w f r 8s follows: aes a) Wt etch poly-Si (buffer poly-Si thickness). e b) Etch off PSG in BHF. c) Wet etch poly-Si (gate poly-Si thickness). d) Fmal dip in BHF until back dewets. 22.4 Remove photomist in Q plasma: 5-7 min at 300 wts at, followed by piranha clean w f r . aes

2 5 Do a 20 sec 2 : H dip just before metallization. 2 5l F

Step 23: Fmt Metallization: target thickness 6OOOangstrom Sputter A with 2%Si on all waders. l

Step 24: F t Metal phdo Mask: Nh4 ( e m u l s i o ~ f ) m

24.1 Spin Hunt WX-235 resist, expose, develop, descum. p : No HMDS step. m 1. 2. No hard bake. 242 Wt etch A . (Wet w f r first in D w t r ) e l aes I ae. 243 Wt etch buffer pdy-Si, visual end point detection. e 24.4 h v c resist with acetone (no piranha!)

24.5 Rinse wafers in DI water for 20 minutes, spin dry.

24.6 Probetestdevices.
~~~ ~

Step 25: Back Side Metalization

25.1 Spin photoresist (front side), Q not expose; hard bake.

-176-

252 Dip i BHF until badr dewcis. n

2 3 Hardbake at 120 &gmC, 10 min. 5

25.4 Right after hardbake, sprtter 6OOOangstrom A with 2% Si un l back si& of dl wdas.
Step%:

sinteriag: 400 degreec for 20 min i farming gap. n

Step27: Endof procesS

APPENDIX B BSIMl MODEL

List of Parameters
flat-band voltage

surface potential
body-effect coefficient

non-uniform channel doping coefficient

value of rl extracted at , V sensitivity of q to , V sensitivity of 7 to Vm value of ,80 extracted a Vm t sensitivity of

=0

and, V

=, V

=0

Bo to v,

at v,

and , V
0

=0

value of Bo extracted at Vm = 0 and Vm = VDD sensitivity of Po to v, at v,

v ,

sensitivity of Bo to Vm a Vm = V m t value of U extracted a V B = 0 , t

sensitivity o f

u, to v ,

value of Ulextrru=ted at V B - 0 d Vm - V m Sensitivity of

u, to v , sensitivity of u, to v,

valueofnextractedatV~=OaudV~=O

sensitivity of n to V B sensitivity of n to, V

-178-

(3)

Linear region:

033)
1 1.744 + .3 6 ( -V=) Oi 3 4h

g =1

03-41

(C) Saturation region:

K=

1+v,+42

@) Subthreshold regiosx

APPENDIX C

SUBTHRESHOLD CONDUCTION
Ihe drain current i the subthreshold e o n is doninateti by the diffusion current Sipen n

where

qS) and Q(Jl) a the invexxiomcharge density a the source and the drain. D,,s the m t i

diffusion constant given by D , , = V d .

(C.l) over the depletion depth, the subthreshold ament can be derived.

when

-181-

"he relationship M e e n the gate vdtage V a and the surface potential & i givm by s

v,-v*=-* Q G
where the inversioncharge Q i the subthreshold region c8n be apcroxirnated by n

[a S
(C.10)

A plot of q versus , & V

i shown i Fig. 5.13. s n

In the subthreshold region (& <2M,& can

be approximated by a linear function of , V

a shown by the dashed line in Fig. 5.13. s

(C.11)
where

Substituting (C.12) into (C.ll) and COmpaLing with (C9) apxl (ClO),V can solved. ,

-182-

APPENDIX D

BSIM2 MODEL
List of Parameters
Given parameters:

Tx a

oxide thickness
temp-

T Vm
, V
VBB

drain supply voltage

gate

supply voltage

body supply voltage

lower bound of the transition region

, V
, V

upper bound of the transition region

AppedixB

-183-

Extracted parameters:

vm
4s
Kl
K 2

flat-band vd-t
Surf=

potential

bodytff~coefficient
non-uniform channel doping coefkicnt d l o w e *
coefficiat

rl
rl0

valueof q extradeaatVB-0
sensitivity o q to v, f

rlB
80

conductance coefficient value of Bo extracted at VB = 0 and Vm

sensitivity of Bo to v ,
at v ,

Boo
BOB
BSO

value of j30 extracted at V B

sensitivity of /? to v !s ,

=0

0
=

0 and Vm

Vm

BSB
83

a v, = v t ,

linear empirical parameter in

expression
=0

80 3

value of P3 extracted at , V
sensitivity of 83 to v , sensitivity of /93 to v,

dVm 0

B B
83G

8 4

quadratic empirical panmeter in

expression
=0

80 4
84B
84G

value of P4 extracted a , tV
sensitivity o 8 4 to v, f sensitivity of 84 to v,

= 0 and, V

82

empirical m e t e r i BO e x p s i o n n

820
BZB

value of 82 extraxted a v, = 0 and v t ,

sensitivity o & to v, f sensitivity of 8 2 to V a

B2G
u 8

first-order parameter of vertivd field effect

u,

value of U8extracted at V s = 0

-184Sensitivity o f

u to v, ,
.

saxmhdu pmmctcx a vutical fidd effect

valueof&extradedatVBs=O sensitivity of rr, to v, velocity sahuation ccefEcieat value of VIextracbd at , V sensitivity of u, to v, sensitivity of u, t v, o subthreshold Swing coefficient value of n when Vm sensitivity of n to , V
sensitivity o n to Vm f

0 and, V

= Vm

m n Vm ad

V of set i the subthreshold region , f n

value of V extracted a , tV
to v,
to v ,

0 and Vm

sensitivity of v ,
sensitivity o v f ,

pmexponential pararneter of & degradation due t high fidd o value of 4 extmted at Vm

sensitivity o 4 to v f ,

exponential parameter of value of Bi

%\It degradation due to high field

at , V

sensitivity Of Bj to Vm

-185-

Model equations:

(B) Drain saturation voltage:

K=

1 +v,+42

(C) Linear region:

(.) C 1 drain current:

Bo-

GWta

uq,uv =r+,,

(C.2) biasdependent parameters:

(C.4) output conductance ( d g:

-188-

0335)

dg=

-0.8364 ~ 4 . 8 3 6 (1 4 ~ V B S (1.744+0.8364(&-VBs))2
.

-o>t

03-43)

da

ws 3

VDSAT 2K

P53)

, 2ulS
I

uld

vIX (VE6 -vIXAT)

V L T

%SAT

av,

D53)

@) Saturation region:

FR

0354)

(D.4) output conductance (Gds):

4

0m 3
@) Transition region:

(El)effective gate capacitance:

where

n=nO+

6-i

nB

+mv,

-192-

(D-75)
(E4) lower tJa&

(E6) cubic spline fundon:

boundary conditions at Va:

boundary conditions at Va:

where

-194-

APPENDIX E

PROGRAM LIST OF "BSIMeva1uate.c"IN SPICE3

xtnclude "prefix&" xtnclude *tdiob Rlnclude qnarh.b Rtnclude "Utilh" xtnclude " K d f h C T eS " xtnclude "BSIMdefS&" xtnclude -lR?iNdefs.h#nclude "C0NST.h" xlcnclude "suffixh"

P This routine evaluates the drain current, its derivatives and the * charges associated with the g a t e m and drain tertninal * using the BSM (Berkeley Short-Channel-1 Model) Quations. */ void BSIMevaIu ate(vds,vbs,vgs ,hereplodel ,gmP&ter,gdsPointergmbSPointex, %Pointer ,qbPointer,qdPointer,cggbPointer,cgdbPointer,cgsbPohta, CbgbPointer,cbdbPointer,cbsbPointer,cdgbPointer,cddbPointer, CdsbPointer,cdra;lPo;nter,vonPointer,vdsatPointer,c~)
register CKTcircuit *ck, register BSIMmoc3el *model; register BSIMinstance *here; dcuble vds ,vbs,vgs; double *grnPointeq double *gdsPoinW, double *gmbsPobW,
dcuble *qgPointeq

double *qbPointeq dcuble *qdPoine, dcuble *cggbPointeq dcuble *cgdbP&W, double *cgsbPohW, double *cbgbP&*, dcuble *cbdbPohteq double *cbsbPointeq h b l e *uigbPointeq b b l e *cddbPointeq h b l e *cdsbPointeq double *cdrainPointw,

Wble *vonPohteq

QuMegmg&@s;

-e%&& &le cggb,cgbb,cgdbfigsb; &ubk cbgb,cbbb,cb&&sb; double cdgb,cdbb,cd&&& double ua,ub,ul plinv; double &advbs,dubdVbs,dul~, double cta; double detadtrbs; double Ai,Bi; double daidVbs,cibiciWs; double V l m t V l m t V l m t dii,gii,bii; double Vp,Vpinv; double scptvp,sqrt@nv; double Von,Vth,VthO; double dvthdvbs,dvth0dvbs,dvthdVds; double Vgsmiwth,VgsminvtM); double Vgl,Vg2; double Vof,Vtm,Vcom; double Vgef,Vgeffinv; double Vc,VcnewSqrtlzvc; double dvcdvbs,dvcdvgs&cdvck,dvcncw~, double kkJdcinv,kknesv; double dkkdVbs,dkkdVgs,&dVds,dkkdVc,dldmewciWs; double sqrtkk,ssqrtkkimr; double Vdsat,Vdsahv,VdsalO; double dvdsatdvbs,dvdsatdvds ,dvdsatdVgs; double IdsJdd; double FRJXinv; double didVgs,dWvds,dMVbs; double UvertJhertiW; &le duvertdvds,duvertdVgs,duvertdvbs; double Usatvd; double dusatveldVds&satvcldVb~; double Utot,Utotinv; double dutotdVds,chrtotnvbs&btdVgs; double G&dVbs; double A,Ainv;
double

double alpha; double dalphaxdvbs; double n; double betalin,betasat,betabxq double dbetabmpdvbs,-gs;

-1%

i( ( C k t - X X T r n d e & (MODEAC I MOD-) f ((~kt->cKTmode MODEIRANOP) &Bt (~kt->crcrmode MODmC)) & &
(ckt-XKTmode & MODEDXI'SMSIG) ) { QlargeCompltationNeeded 1; W e ( QlargeChmptationN4

II

0;

if (vbs 012.0 * here->BSIMvbb)

v w 2.0 heresBSIMvb, b t P the dependence ofparamon Vbs is limited to2Vbb +/ detadvbs OD; duadvbs 0 ) 1; d u m OD; duldvbs OD; daidvbs 0 ) 1; d b i o s 00;

else
vblimit vbq detadvbs here->BSIMetaB; duadvbs h e S 3 S W a B y dubdvbs hers23SIMuBy duldvbs hem>BSIMulB; daidvbs berP>BSIMaiBy dbidvbs-here->BsIMbiB;
if (vgs > 2.0 I

---

hemA3SIMvgg)

vglimit = 2.0 here3sIMvgg; P the Qependence o parameters 011 V s is limited to 2Vgg */ f g

-197-

eta here>BslMetd+h>BsIMetaB VMimit; if(etaeO.0) {

eta = 0 0 .; detadvbs

else if ( eta > 0 5 )

- OD;

<eta - 05;

detadvbs 0 ) 1;

if ( vds * 20 * hereJ-SSMvdd) .

<Vcuimit - 2.0

henA3sIMvdd;

-198Von = Vth, dvthdvbs -heraSIMkl2

e; vgsminvth = vgs - vth,

-&dVb~

Vdlimit 0 5 b > B s I M k l

G- 1.0- 11)/(1.744 + 08364 Vp);

dgaVbs=48364*(1.0-G)*(1.0-G);

A-1.0 + 0 5 G *here->BsIMkl sqrtvpinv; AinV-11)/& dadvbs -0.25 hersS3SlMkl sqrtvph * (2.0 dgavbs + G * Vph); Vgl = here->BsMvghigh; Vg2 = here->BsIMvglow; Vof hem>BSIMvofO + h ~ S S X M v o B Vblimit + hex+>BSIMvofD Vdlimie Vtm = 8.6255 (hereSSlMtemp + 273); I* should be moved./ n = here->BSIMd) + here>BSIMnB * sqrtvph + h->BSIMnD * Vdlimi; tmpl8 2.0 * n Vtm; tmp19 = 1.0 / -18; if (vgsminvth >Vgl) { Vgeff = Vgsminvth;

else if (vgsminvth <Vg2)

1 = vgsminvth tmpl9; i f ( w 1 <-151))

<Vgeff - sqrt(2 * A)
3
{ Vgef 4

Vtm 4 0 5

Vof - 1 . ) 50;

else

else
a l = Vgl; n

2 * A) Vtm 4 0 5

Vof + -; 1 )

coo2-1D; con3 = sqrt(2.0 A) * vtm * e 4 0 5 Vof + v 2 -19); g con4 = con3 -19; Sqlvgl Vgl Vgl; scpvg2 = vg2 * vg2; cubvgl Vgl sqrvgl; albvg2 = vg2 sqrvg2; w p l = sqrvgl+ sqrvg2; tmp2 = 2.0 * cubvgl + cubvg2; con3 - Con1 + con2 he>BsIMv&i& tm$ delta-2.0* Vg2 tmpZ + 3.0 v g l * tmpl+ 6D * Vgl arbVg2- 6 0 * q g l *scpVg2-21) lm$ Vgl .

3.0 scp~g2 - ; 1 CMta=lfl /delta; CkRb-21) con2 vg2 tmp2 +31) sqrvgl tmpl (3x34 +6.0 Vgl q g 2 tmp3-60 Vg2* v g l -2.0 Vgl con4 tmp2- 31) qwg2 * chi2 - ; 1 aXffb=Coeffb*dclta; M c = G m 4 tmp2 + 3.0 s p g 1 t @ + 3 8 * cubvg2 *coa2 m 3.0 sqrvgl* vg2 con4 con2 lxqQ 31) s p g 2 tmp3;

C =M

Cheffd-2.0

* Vg2 tmp3 + ( h 2 tmpl+ 21) Vgl Vg2 * con4 - 21) sqrvg2 coo2 - 2.0 .Vgl anp3 - coa4

* delta;

-; 1 Coeffd coeffd delta; Coeffa- Cd con2 Vgl + W c * sqwgl+ 21) W d o * cubvgl; Vgef = Coeffa + coeffb * Vgsminvth + Coeffc * Vgsminvth * Vgsminvth + Coeffd * Vgsminvth * Vgsminvth * Vgsminvth,

Vgeffinv 1.0 / VgeE; ua = hemSSIMuaO + hers>BsIMuaB vblimit; ub here-SSIMubO + here93SIMubB Vblimit; Uve,rt = 1.0 + ua* V g d + ub Vgef V g e , duvertdvgs = ua + 2.0 ub Vgef; drvextdVds = duvextdvgs dvthciVds; duvertdvbs = Vg& * d u m + Vgeff Vgeff * &bdvbs duvertdvgs * dvthd\lbs;

Uvertinv = 1.0 /We* u l hemS3SIMulO + here-SSIMulB Vblimi~ u l MAX(u1JaS); ulinv 1.0 /ul; v c - u l V g d Ainv uvertimr; dvcdvgs vc Vg&m - vc uveatinv * duvertdvgs; dvcdVcls = Vc dvthdvds ( Uvertinv duvertdvgs Vgdfinv ); dvcdvbs Vc ulinv duldvbs Vc Vgeffinv dvthdvbs -Vc Ainv dadvbs Vc* Uvertinv * ctwertdlb; . sqntvc = 4 1 + 2.0 Vc); dkluiVc 05 (1.0 + 1.0 / sqrt2vc); Irk = 05 ( 1 )+ v c + sqt2vc); 1 kkinv = 1.0/& ssrtkk-sqrt(kk); sqrtkkinv = 1.0/sqrtkk; dkkdvgs = dkkdvc dvcdvgs; dkkdvbs dkkdvc d v m ; dkkdvds = dw<dvc dvcdvdq v s p = VgeE Ainv sqrtkkim; da

--

= MAX(Uvert,05);

V& = MA?C(V&z&,leS); Vckatinv=lx)/Vdsat; dv = v s t Ainv dadvbs v s o vgetiinv dvwvbs da da -0s Vdw * kkinv dkk*; dvdsddvgs = Ainv s@dcim 0 5 * Vdu$ * kkiw M g s ; dvdsatdVds --Vdsat * Vgeffinv dvthdvds 0 5 V u * kkinv dkkdvck;

betalin = b>BSIMbetao + here->BSIMbet&B vblimit; betasat = here->BsIMbebsO + here-SIMbetaSB vblimit;

beta2 hemSSMbeta20 + here->BsIMbeta2B VbWt +
sgrvdd = hersSSIMvdd * here>BsIMvdd;

beta3 = here>BSXMbetdO + hae>BSIMbets3B * Vblimit

here>BSIMbeta2G* V g W ,

+ here-SSIMbeta3G

beta4

here-%SIMbeMG * Vglimit; bebtmp betasat- betalin - beta3 * hae>BsIMvdd+ beZa4 sqrvdd; dbetatmpdvbs = here>BSIMbetasB - here-SSMbeMB
p

herej8S1MbetaQo + here>BsIMbetaQB W h i t

Vglimit;

- hereSSIMbeta3B * hers>BsIMvdd + here-SSJMbeMB * sqrvdd;

=

db&t@Vgs

+ abetacravgs sqrvdd;
tmP'l=be&2*vds*vdsatimr;

- dbeta3dVgS

ha*>BSIMvdd

if ( h p 7

< tanh
1

>ax))

= 1.0; scysech = 0.0;

else if ( -7

< tanh
3

<-201))

= -1.0; sqcsech = Ox);

dse

-201-7 V&&IV dv-6 ) - 2 M v&, dbeteodvbs =b>BsIMbetaoB + c t x m q d b tanh+

tmp22 vdr v s t da; if(Vds+Vdsat)

heza>BsIMbeta3B vds + ktaanp aqsech (vds v s t v k S S I M b e t a 2 B !DIP7 v r t n dai n dsiv dvdsaedvbs) b>BSIMbetaQB vds v&,

tmp20-(1.0 -hera>BSIMulD* tmp22 tmp22 Vdsatinv Vdsstinv); =&eel = u l tmp#); dusatvddvds = u l tmp22 v s t v v s h 2.0 * dai n da v he>BsIMulD (v& VdsaPinv dvdsaddvds - 1); tAlSalveldVbs = tm@O * &ldvbs + u l vds tmp22 2.0 here-SIMulD * V d s h Vdsatinv V d s h dvdsatdvbs; UtDt = uvert + u av l vds; ste Utolinv = 10 /utot; . cbtotdVds = duvertdvds + Usatvel+ vds dusatveldvds;
dutotdvbs duvertdvbs + vds * dusatveldvbs; beta = bet$) Utotinv; betainv = 1.0 /beta; Vg& 05 A * vds; -21 Ids = beta - 1 2 vds; gm=beta* vds + Ids betaimt utotinv * (dbe&Ddvgs beta * dutotdvgs); gds = I & * betainv utotimr (abetaocivds - beta dutotdvds) +beta* tmp21 -beta* vds (dvthdvds + 05 A); gmbs =Ids * betainv utotinv (dbet$)dVbs -beta* dutotdvbs) -beta* V& ( M d b + 05 vds dadvbs);
dutotdVgs = duvertdvgs;

else

kta=bet$) watinv; behillv = 10 / bets; . Id$) = 05 beta* Vgeff

A = k>BSIMaiO + here-SlMaiB VMimit; i

WW2J4; tmprl-Bi/tmp; if(tmprl<50.0)

Vgef'* Ainv

kkinv;

B = h e m S I M b i 0 + hereS3SIMbiB VblimiQ i

rn

-202FBiIlV=11)/FR; W g s t@ m dvds?tdvgs; dErbvds = -m l@ (1 dvdsatdvds);

dfrdvbs = tmp23 dvdsacdvkr;

IdS=Idso*FR;

dse

<FR-lQ
FRimr = 11);
dfrdvgs = 0.0; cifrdvds = 01); dfrdvbs 0.0; Ids Idso;

betainv * Uvertinv * (dbet$)dvgs - beta * duvertavgs) 2.0 Vgeffinv Ids kkinv dkkavgs + Ids * FRinv W g s ; gds = Ids * betainv Uvertinv (dbetaDdvds beta * duvertdVds) 2.0 * Ids Vgeffinv * dvthNds -Ids * kkinv dkkdvds +Ids * FRinv * dfrdvds; gmbs -Ids * betainv Uvertinv * (abetd>dVb~ beta duvertdvbs) 2.0 * Ids Vgeffinv dvthdvbs -Ids Ainv * dadvbs-Ids kkinv dkkdms + Ids Flzinv * dfrdvbs;

gm

- Ids* Ids * +

model->BsIMcox (here->BSM - model->BSIMdeltaL 1.d) (here->BSIMw - model->BSlM&ltaW 1.0-6) 1.4; P F */

x
charg~mpltalid&=

i( b>BSIMchannelChargePartitionFlag>1) f
1 ;

1
if( ! ChargeGxrptationNeeded )

qg =ox); qd 0.0; qb = 0 ) 1;

cggb = 0.0; cgsb = 0.0; cgcb = OD; d g b = OD; cdsb = OD; cdd,= 0.0; cbgb 0.0; cbsb = 0.0; cbdb = 0.0; got0 finisbtd;

i( ( h ~ > B S I M c h m d Q e P d t i o d b g 1) f
{ PO400 partitioning for drain/source charges i saturarion region*/ n

Vgb V S vbs; g Vgb-Vfb = Vgb hers>BSIM*, Vgl -02; Vg2 = -0.15; VtM) hem>BSlMvfb + here->SSMphi sqrtvp; vgsminvtho = vgs V W ; vdsato = v g s m i l l a Aiw, v lao = MAxglasclrop); cs t

+ here->BSIMkl

i( Vgb-Vfb <O.O) f
{

P Accumulation Region */

qg * wLx=ox * Vgb-Vftq qb=-qg; qd = 0.0; cggb = WX; cgdb = OD; cgsb OD; cgbb - cggb; cbgb--wLx=ox; cbdb = OD;
cbsb cbbb = Cggb; cdgb OtO;

cddb = 0.0; cdsb = 0.0; cdbb = OD;

-- OD; -

goto finished;
else if ( VgsmimrtM)

Vg2 )

P Subthreshold Region */

AppendixE

trnps=sqrt(l1)+41)*Vgb,Vfb/(hc,m>BSIMkl b>BsIMkl)); a = 05 wLX=ox b>BsIMkl beaaS3SlMkl (-ll) + tmp8);

+=qi?;
x / tmp8; cgbb = c g gb cgdb = cgsb = 01); cbbb = Cggb; @b=-cggb; Cbdb=CbSb-Ox); cdgb = cckib = cdsb = cdbb =OD; goto finished;

qd = 0 ) 1; cab =W

else if ( VgsminvthO <Vgl )

<tmp8 = ~qrt(l.0+ 4.0 * (Vgb-Vfb - VgsminvtM) + Vg2)

/(hem>BSIMkl* here+BSIMkl)); coni= 0 5 WLOX h->BSIMkl herct>BsIMkl (-1.0 + tmp8); tm@ 4 1 . 0 + 4.0 * (Vgb-Vfb VgsminvtM)) /(here>BSIMkl here->BsIMkl)); con2 0 5 WLX=OX here->BSIMkl heae->BsIMkl (-1.0 + tmp9); dvtM)dvbs = - hae->BsIMkl* 05 )L triode region */ i( vds 4 k l s a b o ) f

w;

alphax = A; dalphaxdvbs = dad\lbs; tmp9 = Vgl 0 5 alphat vds;

tmp9 = W W , leg);
dtmp9dVbs -dVtM)dVbs 05 * vds * dalpha~dvbs; ~b@dVds=-O.S*d~ -10 alphax * vds; tmpl = -10 bq2;
tmp2=1.0/*;

q l l = vds * tmp2; -12 = tmpl0 honpll mp2; -14 1.0 al+; Imp13 = -14 * vds; con3 = WLCOX (Vgl+ VW her*>BsIMvfb here->BsIMphi 05 V& + 0.08333 V& tmpl); tnq>2o=conl-C0O2; -21 coo3 C0O2; delta= 11) /(vg2 Vgl V g l - Vgl * vg2 V 2 ; g) coeffb (tmp20 Vgl Vgl tmp21 v 2 * Vg2) delta; g

-205-

W c = (vg2 tmp21- Vgl tmp#)) ddta; qg = con2 + GXBb * v g + W c vgsminvtm vgtmhvtho; cod = - W u h x ( - VthD + here->BsIMvfb + b S W + 05 -13 - 0.08333 * -13 -1); tmp21= con3 con2; COefIb- (tmpu> Vgl* Vgl- tmp21 vg2 * Vg2) delta; coeffc = (vg2 tmp21- Vgl tmpu>) ddta; cp-- (COD2 + coeffb VgSminvtM) + coeffc vgVgsminvtbo); trmjo Vgl vg2; tmp21=1.0/(tmp20*~~ q 2 2 = VgsminvtllQ vg2; tmp23 = -22 tmp2; -19 = @21* tmp23; qd = - WLCOX * (05 Vgl 0.75 bapl0 + 0.125 * tmpl0 -1) * bapl9; C~b~wLx3oX/tmp8*(1.0-tmpl9)+~~*(1.O - 0.08333 * tmp12) * -19; x * ( - 05 + 0.16667 * alphax tmpll cgdb = m 0.08333 * -12 dtmp96VdS) -19; cgbb = - W X * (1.0 - tmpl9) + WLCOX 0.08333 / tmp8 (vds tmpll * daphaxdvbs q l 2 dtmp9dvbs) -19; cgsb - (Cab + Cgdb + cgbb); / tmp8 0.08333 cbgb - W X * (1.0 - tmpl.9) + WX -12 * tmpl4 -19; mp14 (05 - 0.16667 * alphax * - 1 1 Cbdb W X + 0.08333 tmpl2 dtmp9dVds) -19; cbbb = m x /tmg8 * (1.0 - bnp19) - m x * (dvthodvbs + 05 vds dalphaxdvbs + 0.08333 * vds tmpll (1.0 05 alpha) +dalpha~dVbs 0.08333 tmpl4 tmpl2 dtmp96vbs) * tmp19; cbsb-- (cbgb + cbdb + cbbb); cdgb - WX (05 0.125 alpha^ * tmp12) -19; Cddb- WX (0.75 alpha^ - 0.25 alphm alphax mpll+ 0.125 al* * mp12 dtxnp9dvds) -19; cdbb = wLx30x (05 &thOdvbs + 0.75 * vds dalphaxavbs 025 * alpha V& - 1 1 dalphaxos + 0.125 alphax Imp12 dtmp9dvbs) mpl9; cdsb-- ( e b + CdB, + db); got0 finished;

elst

alphax-A;

dalphaxavbs-~, -11) /(31) * dphax);

-10 = Vgl tIllF$; tmpll= tmpl0 / dphax; coa3 wtcox ( M+ Vgl helm>BsIMvfb V kA3slMphi lmpl0); tmp2o=conl-con2; tmp21= coa3 con2; delta = 1.0 / 0 3 2 Vgl Vgl - Vgl v 2 Vg2); g coeffb (-20 Vgl Vgl 1 v 2 * Vg2) aa g t ; oeffc-(vg2 tm@1 -Vgl mp20)* ddta; qg con2 + coeffb VgSminvtM) + Cocffc. vgsminvtho VgSminvtM); Con3 - WLCOX * (h~>BSD&fb+ hm>BsB-@li VW + (1.0 - alphax) * tmpl0); -21 = con3 Qn2; coeffb = (tmprn Vgl * Vgl imp21 vg2 Vg2) delta; coeffc = (vg2 * tmp21- Vgl * q 2 0 ) * delta; qb - (con2+ VgsminvtM) + Coeffc * VgSminvtM) * Vgsminvtho); tmp2o Vgl vg2; 1 -21 = 1 )/(tmp20 tmp20); tmp22 VgsminVtM) vg2; tmp23 = -22 tmp22; tmpl9 = -21 * tmp23; qd 0.0; /tmp8 (11)- -19) + -X (1 1) cggb WX W ) -19; * cgdb = 0.0; cgbb = - w x /tmp8 ( 1 - tmpl9) + m 1) x * (tmp9 dvthodvbs + tmpll dalfiaxdvbs) tmpl9; cgsb = - (cab + ~ g d b Cgbb); + t (1.0 -19) + W I O x (b@ cbgb -WL&x / @ 033333) -19; cwb = 0.0; cbbb WX /tmp8 (1.0 - W l 9 ) - WX((0.66667 + tmp9) * dvtM)dvbs + h p l l dalphaxdvbs) * -19; Cbsbm- ( a b + cbd,+ cbbb); cdgb = 0.0; cddb OD;

--

cdbb =

-OD;

cdsb = 0.0; gdo finished;

3
}
else if( vds

<V&d )

I* tliode Iegion */

AppmcfixE

<

alphax=A; dalphaxavbs-dadvbs; t~@=Vg~mhthO-OJ* alphaX*~do; tmpg = lag); t@ X = 1.0 /tmrJ9; ~ d V b s = a v t M M v b s0 5 * vds aalphaxavbs; dtm@ivds = 05 ai*; q l 0 = alphax vds; tmpl= q l 0 *

ww,

q l l = vds tmp2;

*;
-

q 1 2 = tmpl0 m p l l t; u @ q 1 4 1.0 alpha; tmp13 = tmg14 * vds; W X h-SSIMvfb * (vgs h-SSIMpbi 05 * vds + 0.08333 vds -1); qb WLx30~ ( Vtho + hme>BSIMvfb + hm>BSIM@i + 0 5 * tmpl3 0.08333 * -13 tmpl); W X VgsminvtM) 0.75 tmpl0 (05 @ + 0.125 * tmpl0 * -1); cggb WLCOX * (1.0 0.08333 -12); cgdb = WLCOX * ( - 05 + 0.16667 alpha tmpll 0.08333 * -12 dt@dVds); c g b = WLCox * 0.08333 (vds tmpll dalphaxavbs -12 dtmp!3dvbs); (cggb + Cgdb + ~gbb); cgsb cbgb = W x 0.08333 -12 -14; cbdb WLCOX tmpl4 * (05 0.16667 * alphax -11 + 0.08333 tmpl2 dtmp9dVds); W=WEOX* (dvthodvbs + 05 vds dalpha~avbs + 0.08333 vds -11 (1.0 0 5 * alpha) dalpha~dvbs 0.08333 -14 * tmpl2 * dtmp9dvbs); cbsb = - (cbgb + cbdb + cbbb); cdgb WLX=OX (05 0.125 dphax -12); &=WLCOX (0.75 alpha 0.25 aipha~ alphax -11 + 0.125 * alphax -12 dfmp9dvds); cdbb =WX dvtN)dVbs + 0.75 vds d a l p h a ~ d b (05 0.25 * alphax vds q l l dalphaxdvbs + 0.125 alphax tmp12 * cltmp9dvbs); &= ( a b + cdb,+ a ; ) goto finishad;

else if( vds P Vdsado )

P satmition region */

dphaX=A;

ddphaxaVbs = dadvbs; @t = 11) /(31) alphrrx);

Vgsminvtho * t@ u; -11 tmpl0 / a I WLx30~ (Vgs h m S s I M v f b b w -10); S 98 qb = WLx30x (heJe>BsIMvfb herd3sIMphi V M + + (11) alphax) -10); qd = OD; cggb-WLCor*(lX)-@); cgdb = OD; cgbb - w u h (m ! * CtvtwMVbs + - 1 * dalphElxdvtB~ t pJ 1 cgsb (Cggb + cgdb + cgbb); 033333); cbgb WLCOX * (t~@ cwb = 0.0; cbbb-- W X ((0.66667 + tmp9) dvtM)dVbs + tmpll dalphaxdvb6); &b-- (cbgb + cbdb + cwb); cdgb = 0.0; cddb = 0.0; cdbb = OD; cdsb = 0.0; goto finished;
biIlpl0

1
goto finished;
else

EL QlannelaargePartioag < 1*/

P4OM partitioning for drain/source charges in sahuation region*/ -24 q 2 4 20; Vgb vgs vbs ; Vgb-Vfb Vgb-here->BSM*, Vgl -02; Vg2 = -0.15; Vh = hereSSMvfb + h e r e - S S W + her~>BSIMkl tO * scptvp; VgSminvtM) vgs V W ; v s t = vgsrnhtho Ainv; dao

Vdsalo-~dsaQp);
if( Vgb-Vfb <O.O)

< qg

I* Acaunuldon Region */
Vgb-W,

= WLCox

+--qg;

qd = 0 ) 1; cggb = WLcOx; cgdb = 0.; cgsb = 0.; cgbb = cggb;

w b - - a ,
cbb, 0.;

cbsb 0.; cbbb = Cggb;

dgb = 0.; cdcb 0.; cdsb = 0.; CCBb = 0.0; goso finished;
dsc%(VgsmhvthO+Vg2)

<tmp8 - sqt(l.0 + 4.0 * Vgb-Vfb /(hem>BSIMkl

hem>sSW)); qg = 05 W x * hemSSIMkl * (-10 + tmp8); sb = -98; q = 0.0; i cggb = WIXlox cgbb = - cggb; cgdb cgsb 0.0; cbbb = Cggb; cbgb = - cab; cwb cbsb = 0.0; cdgb cddb = cdsb =cdbb=O.0; got0 finished;

PSuwlrcshadRegion*/

hem>BSIMkl

- --

else if ( Vgsminvtho

<

<Vgl )

P Subthreshold Region */

tmp8 4 1 . 0 + 4.0 (Vgb-Vfb VgsminvtM) + Vg2) / (here+>BSIMkl hexe>BsIMkl)); M= WX > B S I M k l k > B s I M k l 05 *b

* (-1.0+ tosp8);

sqrt(l.0 + 4.0 (Vgb-Vfb V g d ) /@ere>SSIMkl b>BslMkl)); coo2 - 0 5 WLcOx hera>BSIMkl heraSSIMkl (-1.0 + tn9; zp) if(vdp<VdSEdo) Ptrio&regian */
t i @

<

alphax-A; dalphaxdvbs = dadvb6; tmp9 Vgl 0 5 * alpaax vds; tmp9 = MAx(tmp9, leg); lqS2 = 1.0 /tmp9; dtnqj9dVbs -dWMdVbs 0 5 V dtmpj9dVds 0 5 alphaxi tmpl0 al* vds;

~ S

ddpha~avbs;

I -

-210-

tmpl= -10 tmgQ; ~ l l = v d s * ~ ; mp14 1 ) aphax; 1 - 3 = -14 1 vds; mp10 tmpll t q 2 ; -12 tIIIpl5 alphax * tmpll / m ; t@ tmpl6 -10 -10; tmpl7 0.1667 Vgl Vgl; imp18 = 0.125 - 0 1 * Vgl; -19 o * -16; m -17 -18 + -19; t@O e l =2.0 -15 /tm@ * tmp20; &i3 - W (Vgl+ VtM) k ~ - S S l M v f b h e S S I M @ X 05 vds + 0.08333 vds -1); 2 = cod-con2; -23 con3 ad; delta = 10 / (Vg2 * Vgl * Vgl Vgl Vg2 * Vg2); . coeffb = (tmp22 Vgl * Vgl hp23 vg2 * Vg2) delta; WC(Vg2* tmp23 Vgl tmp22) * delta; qg = C d C o e f f b vgsminvtho + w c * VgSminvtM) Q+ * VgSmiwtK); coa3 = - WLCox * ( - VthO + he>BSIMvfb + h e > B s b Q h i + 05 h p 1 3 0.08333 -13 * tmpl); tu4323 con3 ad; coeffb = (tmp22 * Vgl Vgl -tmp23 v 2 Vg2) delta; g WC(Vg2 * tmp23 Vgl tmp22) delta; q b = - (Con2 + coeffb VgsmiwtM) + COeffc VgSmbtMl * VgsmimrtM)); -22 = Vgl vg2; -22 = 1.0 / (tmp22 tmp22); -23 VgsminvtM) Vg2; -23 = -23 -23 * w 2 ; qd-- W E O X (05 V g l - 0 5 * o l + -15 * tmp20) * bmp23; 1 ) 2 ) + -X (1 1) C S b WLCox / tmp8 * ( 1 - 3 0.08333 * -12) tmp23, cgdb wL&x ( - 05 + 036667 d h x -1 pa 1 0.08333 -12 * dbmp9dVds) t1@3; cgbb-- W x / h p 8 (1.0 +W X 0.08333 (vas tmpll Qlphaxavbs bnpl2 dtmp9dvbs)

-h ) e
-

tmp23;
cgsb

cbgb

- (cggb + Cgdb + cgbb); - WLX=OX / tmp8 (1.0 - -3)

+WIOX

088333

-12 -14 tmp23; ~ ~ c U WLCOX tmpl4 (05 0.16667 alphax tmpll J + 0.08333 tmpl2 cbnp9dVds) * tn1~23;

cbbb=WLCox /tmp8 (11) t m p 2 3 ) - W (

-211+ 0 5 vds dal#~~dvt~+01)8333 vds tmpll (1.0 05 d e ) ddlphaaavbs O m 3 3 -14 * -12 chug$*) t; n @ &b ( a b + &b + cbbb); e b WL&X (05 + -15 (03333 Vgl 0.125 -10) -) 1 t@ M; cddb wIx;ox (OS al* + tmpzl &np9dvdi? tmp2 tmp2 (-17 20 - 8 . 1 + 3.0 hpl9)) bnp23; cdbb (05 d v t M d h ~ 0 5 vds daiphaxavbs + +-21 dt~@dVb~-t~@l /t@ * (-17 dalphaxavbs 03333 alphax Vgl dvWdVb 21) tmpl8 ddlphaxavbs + 0.l25 d * -10 mdvbs + 3 8 mpl9 ddphaxdvbs)) Qnp23;

--

I -

--

&=

- ( bcddb + cdbb); a+
> VdsatO ) P

goto hished;
else if( vds

saturation region

*/

alphax = A; dalphaxavbs d a d b ; tmp9 = 1.0 / ( . dphax); 30 -10 Vgl tmp9; tnrpll tmpl0 / dphax; con3-wLx3ox*(VtM)+V~l-~>BsIMvfb-h~>BsIMphi tmPl0); tmp2O-cOnl-Gm2; tmp21- con3 coo2; delta- 10 l(vg2 Vgl Vgl- Vgl vg2 Vg2); . a e f f b = (tmprn * Vgl Vgl tmp21 vg2 Vg2) * delta; coedfc (vg2 tmp21- Vgl tmp20) * delta; qg -con2 + coeffb* vgminvtho + VgSminvtM) VgSmiwtM); Con3 = - m x (hereeBsIMvfb + hers>BsIMphi VthD + (la alphax) bnpl0); tup21 con3 con2; coeffb (bnp20 Vgl Vgl tmp21 vg2 Vg2) delta; W C (vg2 1 Vgl tmp20) ddtq qb-- (con2+ coeffb vgsmiwtho + M C vgsmimho Vgsmiavw); tmp20 = Vgl vg2; tup21 1 )1 1 (tmP20 W); t@ m v g s m i n m vg2; tmp23 m p 2 2 * tmp22 tmp21; qd-- m x 0266667 Vgl tmp23; c u b - W I B x /tmp8 (1.0 + WX (1.0

-- -

*w;

- w)

- e)

...

ApoiE pedx
cgd, = 0 ) 1;

-212-

x /t+? (11) tmp23) + WIX'na (tmp9 dvthDdvbs +tmpll d$phdvbs)* t@ m; (Cggb + cg& + cgbb); qsb -X / tmps (11) + cbgb (tnaJ0 033333) t z @ ; cbdb = 0.0; cbbb WLCOX /t+? ( . t11@3)- WUOX ( 0 6 6 7 10 (.66 + tmp9) dvthodvbs + tmpll daIphaxdvbs) rmpz3; cbsb (Cbgb + cbdb + cbbb); ebm0266667 b@3; CdB, 0.0; c&b= WX* 0266667 dvtfdMvbs t@ m; cdsb- -(cdgb+&+&b); got0 finished;
cgbb = w

- w)

I -

got0 fished,

eke i( vds <VdsatO ) f

< dphax
-*=-

I* t h i e region */

= A;

tmp2 10 /m@; .
dh-ng9dvds = 0 5

dalphaxdvbs = dadvbs; bnpg -VgsminvtM) 05 dpha~ V& * hmpg = lag);

alphax vds; tmplp -10 tmp2; -11 = vds

-0 1

-w w , - * = -4 1

dVtM)*

-05 dphax;

* vds ddpha~dvbs,

-4 1
-13

10 alphax; .

*; vds;

mpll tmp2; t q 1 5 = alpha -11 mp2;

tmp16 = -10 * -10; -17 = 0 1 6 7 Vgsmiwtho VgsminvW; .66 -18 = 0.125 -10 * VgdnvthO; -19 = 0.025 -16; -7 1 tmpl8 + - 9 1; t~@ -1 -2.0 * - 5 2 1 mp2 ~g = W X (vgs h-SSIMVfb 05 vds + 0.08333 vds -1); WLCox ( Vh + he>BSIMvfb + he>BSD@i tO + 0 5 -13 0.08333 * -13 tmpl); qd m x (05 vgsminvtho 0 5 Imp10

tmp12 = - 0 1

w; -

+ -5 1 W); a b = WLCOX (1.0 - 0.08333 -12);

--

cgb,-WL&~ ( - 0 5 +O.l6667 dpha -11 008333 -12 WdVds); qbb = W L b x OB8333 (vds -11 ddphradvbe

(cggb + q ;+ qbb); d, cbgb = wLx=ax OB8333 m2 tmpl+ l M-wIx=oa -14 Q.5 056661 -1 + 0.08333 w2 &@dVdr); l CW=(dvthodvk + 05 V& ddpkdW6 + 0.08333 V& -11 (11) 05 dphm) datphaxavbs 008333 -14 w2 -; l ) cbsb-0 (cbgb + + &); e b (05 + -15 (03333 V g M 0525 -10) mp2l); cddb (05 alphax + imp21 dhnp9dvds alpha h p 2 * tmp2 (-17-24 -18 + 3.0 -19)); cdbb - W x (05 dvtN)dVbs + 05 vds ddpbadVtm +t@l dt@dVbs-t@l /h$ (-17 ddphaxavbs 03333 alphax V g M dvthDdVbs -2.0 -18 ddlphaxavbs + O U alpha -10 dvtM)dVbs + 3.0 -19 * dalph=dvbs)); &b= (cdgb + cdb> + e); got0 finished;
~gsb
I -

-@w w-);

I -

--

else if( vck

<

>V d s d ) P sahuadion rq&m */

a h a4 l EP

dalphadvbs = dadvbs; Y@= 1.0 / (3.0 dpbax); I mpl0 = vgsminvtho * tmp9; -11 = mpl0 / alphax;
qg = wubx

(vgs baa>BsIMvfb k S S I M p b i *lo);

qb= WLcOx (hercF>BsIMvfb+hub>8shplbi - V W + (11) dpha) -10);

qd=-n*0266667*VgsminvthD; c6gb=WIOx* ( 1 . 0 - w ) ; cgcb = 0.0; qbb =wubx ( @ dvtMMvbs + -11 t clalphdvb6~ C @ m - (cab + cgb, + qbb); cbgb = W U h @ t ( 033333); cwb = 0.0; &bb=- WL&X ((066667 + t ) dvtfJodvk @ + mpll d a I m ) ; &b (cbgb + && + &bbh * b - W ,0 -

I -

-214-

grnPointcr- gm; *gdsPointer = gdp; *gmbspointer = gmbs;

*qgPointCr qg; *qbPOinW = qb;

*qdPohtcr

*cggbPointcx = cggb; *cgdbPointer cgdb; *cgsbPointcr= cgsb; *cbgbPointer c g bb *cbdbPointu cbdb; *cbsbPointcr c s bk *cdgbPointer = cdgb; *cddbPointer = * , *cdsbPointcx * cdsb;
*cdrainpointw = uAx(lds,1.0e50);

- sd;
--

*vonPointer Von; *vdsaPointe!r= v s d da ;