Quervin Lloyd L.

Buco TERMS:

COMSYSORG

ALU - is a digital circuit that performs arithmetic and logical operations. Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. An ALU loads data from input registers, an external Control Unit then tells the ALU what operation to perform on that data, and then the ALU stores its result into an output register. The Control Unit is responsible for moving the processed data between these registers, ALU and memory. Special Function Registers - The Special Function Register (SFR) is the upper area of addressable memory, from address 0x80 to 0xFF. This area of memory cannot be used for data or program storage, but is instead a series of memory-mapped ports and registers. All port input and output can therefore be performed by memory move operations on specified addresses in the SFR. Also, different status registers are mapped into the SFR, for use in checking the status of the 8051, and changing some operational parameters of the 8051. Memory Unit - Microprocessors rely on memory for storing the instructions and the data used by software programs. The memory unit is responsible for communicating with the system memory. All von Neumann CPUs store their instructions in memory. The memory unit is typically one of the slowest components of a microcontroller, because the external interface with RAM is typically much slower then the speed of the processor. General Purpose Registers - can store both data and addresses, i.e., they are combined Data/Address registers. They are available to store any transient data required by the program. For example, when a program is interrupted its state, ie: the value of the registers such as the program counter, instruction register ormemory address register - may be saved into the general purpose registers, ready for recall when the program is ready to start again. Peripheral Interface Chip - Peripheral Interface Controllers (PIC) is one of the advanced microcontrollers developed by microchip technologies. These microcontrollers are widely used in modern electronics applications. A PIC controller integrates all type of advanced interfacing ports and memory modules. These controllers are more advanced than normal microcontroller like INTEL 8051. The first PIC chip was announced in 1975 (PIC1650). As like normal microcontroller, the PIC chip also combines a microprocessor unit called CPU and is integrated with various types of memory modules (RAM, ROM, EEPROM ,etc), I/O ports, timers/counters, communication ports, etc. All PIC microcontroller family uses Harvard architecture. Howard Architecture Harvard Architecture - This architecture has the program and data accessed from separate memories so the device has a program memory bus and a data memory bus (more than 8 lines in a normal bus). This improves the bandwidth (data throughput) over traditional von Neumann architecture where program and data are fetched from the same memory (accesses over the same bus). Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Von Neumann Architecture - The von Neumann architecture is a design model for a stored-program digital computer that uses a central processing unit (CPU) and a single separate storage structure ("memory") to hold both instructions and data. It is named after the mathematician and early computer scientist John von Neumann. Such computers are theoretically equivalent to a universal Turing machine and have a sequential architecture.

 


What is the difference between a von Neumann architecture and a Harvard architecture? Applies to: ARM1020/22E, ARM1026EJ-S, ARM1136, ARM720T, ARM7EJ-S, ARM7TDMI, ARM7TDMI-S, ARM920/922T,ARM926EJS, ARM940T, ARM946E-S, ARM966E-S, ARM9TDMI Harvard architecture has separate data and instruction busses, allowing transfers to be performed simultaneously on both busses. A von Neumann architecture has only one bus which is used for both data transfers and instruction fetches, and therefore data transfers and instruction fetches must be scheduled - they can not be performed at the same time. It is possible to have two separate memory systems for a Harvard architecture. As long as data and instructions can be fed in at the same time, then it doesn't matter whether it comes from a cache or memory. But there are problems with this. Compilers generally embed data (literal pools) within the code, and it is often also necessary to be able to write to the instruction memory space, for example in the case of self modifying code, or, if an ARM debugger is used, to set software breakpoints in memory. If there are two completely separate, isolated memory systems, this is not possible. There must be some kind of bridge between the memory systems to allow this. Using a simple, unified memory system together with a Harvard architecture is highly inefficient. Unless it is possible to feed data into both busses at the same time, it might be better to use a von Neumann architecture processor.

Use of caches At higher clock speeds, caches are useful as the memory speed is proportionally slower. Harvard architectures tend to be targeted at higher performance systems, and so caches are nearly always used in such systems. Von Neumann architectures usually have a single unified cache, which stores both instructions and data. The proportion of each in the cache is variable, which may be a good thing. It would in principle be possible to have separate instruction and data caches, storing data and instructions separately. This probably would not be very useful as it would only be possible to ever access one cache at a time. Caches for Harvard architectures are very useful. Such a system would have separate caches for each bus. Trying to use a shared cache on a Harvard architecture would be very inefficient since then only one bus can be fed at a time. Having two caches means it is possible to feed both buses simultaneously....exactly what is necessary for a Harvard architecture. This also allows to have a very simple unified memory system, using the same address space for both instructions and data. This gets around the problem of literal pools and self modifying code. What it does mean, however, is that when starting with empty caches, it is necessary to fetch instructions and data from the single memory system, at the same time. Obviously, two memory accesses are needed therefore before the core has all the data needed. This performance will be no better than a von Neumann architecture. However, as the caches fill up, it is much more likely that the instruction or data value has already been cached, and so only one of the two has to be fetched from memory. The other can be supplied directly from the cache with no additional delay. The best performance is achieved when both instructions and data are supplied by the caches, with no need to access external memory at all. This is the most sensible compromise and the architecture used by ARMs Harvard processor cores. Two separate memory systems can perform better, but would be difficult to implement.

 

SAP-1 Architecture - The architecture is 8 bits and comprises of 16 X 8 memory i.e. 16 memory location with 8 bits in each location, therefore, need 4 address lines which either comes from the PC (Program Counter whish may be called instruction pointer) during computer run phase or may comes from the 4 address switches during the program phase. All intructions (5 only) stores in this memory. It means SAP cann't store program having more than 16 instructions. SAP can only perform addition and subtraction and no logical operation. These arithematic operation are performed by an adder/subtractor unit. RISC - Reduced instruction set computing is a CPU design strategy based on the insight that simplified (as opposed to complex) instructions can provide higher performance if this simplicity enables much faster execution of each instruction. A computer based on this strategy is a reduced instruction set computer (also RISC). CISC - complex instruction set computeris a computer where single instructions can execute several low-level operations (such as a load from memory, an arithmeticoperation, and a memory store) and/or are capable of multi-step operations or addressing modes within single instructions. The CISC architecture contains a large set of computer instructions that range from very simple to very complex and specialized. Though the design was intended to compute complex instructions in the most efficient way, it was later found that many small, short instructions could compute complex instructions more efficiently. This led to a design called Reduced Instruction Set Computing (RISC), which is now the other major kind of microprocessor architecture. Intel Pentium processors are mainly CISC-based, with some RISC facilities built into them, whereas the PowerPC processors are completely RISC-based. WDT - Watch Dog Timer (WDT) is a timer which makes micro controller program work properly without freezing. Its basic working principle is to makemicrocontroller reset when WDT overflows. To prevent this, we have to clear WDT register periodically in the program flow. Actually, WDT is a standart 8 bit timer that counts continously. However, when overflow takes place, it reset microcontroller instead of interrupting. INTCON - The INTCON register is a readable and writable register which contains the various enable bits for all interrupt sources. Instruction Cycle - The time period during which one instruction is fetched from memory and executed when a computer is given an instruction in machine language. There are typically four stages of an instruction cycle that the CPU carries out: 1) Fetch the instruction from memory. 2) "Decode" the instruction. 3) "Read the effective address" from memory if the instruction has an indirect address. 4) "Execute" the instruction. Machine Cycle - The steps performed by the computer processor for each machine language instruction received. The machine cycleis a 4 process cycle that includes reading and interpreting the machine language, executing the code and then storing that code.

 

Pipelining - Pipelining is an implementation technique where multiple instructions are overlapped in execution. The computer pipeline is divided in stages. Each stage completes a part of an instruction in parallel. The stages are connected one to the next to form a pipe instructions enter at one end, progress through the stages, and exit at the other end. Fetching - To locate the next instruction in memory for execution by the CPU Program Memory - Program memory is normally used for storing program code, i.e. instructions. The ROM memory also called as n program memory. Program Counter - The Program Counter (PC) is a register structure that contains the address pointer value of the current instruction. Each cycle, the value at the pointer is read into the instruction decoder and the program counter is updated to point to the next instruction. For RISC computers updating the PC register is as simple as adding the machine word length (in bytes) to the PC. In a CISC machine, however, the length of the current instruction needs to be calculated, and that length value needs to be added to the PC. Data Memory - Data memory is used for storing program data. Moore's Law - Moore's law describes a long-term trend in the history of computing hardware. The number of transistors that can be placed inexpensively on an integrated circuitdoubles approximately every two years. This trend has continued for more than half a century and is expected to continue until 2015 or 2020 or later. Gray Code - The reflected binary code, also known as Gray code after Frank Gray, is a binary numeral system where two successive values differ in only one bit.The reflected binary code was originally designed to prevent spurious output from electromechanical switches. Today, Gray codes are widely used to facilitate error correction in digital communications such as digital terrestrial television and some cable TV systems. Shannon's Code Enigma Code - Two gentlemen, Alan Turing and Alfred Knox, were instrumental in the final breakdown of the Enigma. The created a gigantic machine called Colossus, which helped decipher complex intercepted Enigma messages. Gordon Moore - Gordon Earle Moore (born January 3, 1929) is the co-founder and Chairman Emeritus of Intel Corporation and the author of Moore's Law Ted Hoff - Marcian Edward Hoff Jr. is the Inventor of The Microprocessor. :) Robert Noyce - co-inventor, with Jack Kilby, of the integrated circuit.co-founded Fairchild Semiconductor in 1957 and Intel . He is also credited (along with Jack Kilby) with the invention of the integrated circuit or microchip which fueled the personal computer revolution and gave Silicon Valley its name Federico Faggin - an Italian physicist/electrical engineer, principally responsible for the design of the first microprocessor and for leading the 4004 (MCS-4) project to its successful outcome and for promoting its marketing. He also designed/led the design and was the vital force during the first five years of Intel's microprocessor effort. William Shockley - an American physicist and inventor. Along with John Bardeen and Walter Houser Brattain, Shockley co-invented the transistor, for which all three were awarded the 1956 Nobel Prize in Physics. Nano Technology - Nanotechnology (sometimes shortened to "nanotech") is the study of manipulating matter on an atomic and molecular scale. Generally, nanotechnology deals with structures sized between 1 to 100 nanometre in at least one dimension, and involves developing materials or devices possessing at least one dimension within that size. 32BIT Floating IEE Format T Flip-Flop - The T or "toggle"flip-flop changes its output on eachclock edge, giving an output which is half the frequency of the signal to the T input. SHIFT REGISTER - A special type of register, known as the shift register, is used to pass or transfer bits of data from one flip-flop to another. This process of transferring data bits from one flip-flop to the next is known as 'shifting'. Shift registers are useful for transferring data in a serial manner while allowing parallel access to the data. COUNTER - In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. RING COUNTER - formed by a shift register with feedback connection in a ring. A ring counter is a shift register (a cascade connection of flipflops) with the output of the last one connected to the input of the first, that is, in a ring. Typically, a pattern consisting of a single bit is circulated so the state repeats every n clock cycles if n flip-flops are used.It can be used as a cycle counter of n states RIPPLE COUNTER - An asynchronous (ripple) counter is a single JK-type flip-flop, with its J (data) input fed from its own inverted output. This circuit can store one bit, and hence can count from zero to one before it overflows (starts over from 0). This counter will increment once for every clock cycle and takes two clock cycles to overflow, so every cycle it will alternate between a transition from 0 to 1 and a transition from 1 to 0. Atom Architecture Flash Memory - This is a special type of memory where READ, WRITE, and ERASE operations can be done many times. This type of memory was invented by INTEL corporation in 1980. A PIC Chip normally contains a certain amount of flash memory.

 

 

    

 

 

 

 

NVRAM Flash - NVRAM is a general term for all non-volatile memories, but hereafter the NVRAM refers to the battery powered SRAM (or DRAM). Dallas/Maxim and ST have shipped many NVRAM products in the microcontroller, RTC and some special ICs. NAND Flash - The NAND flash memory is most commonly used in the secondary memory devices, either in the raw chip (SMC) or managed devices (SD card). Its programming speed is much faster, with larger but less reliable memory blocks. It offers block fashion operations, including read, write, erase, lock and unlock of the specific blocks. FeRAM Flash - The FeRAM has many advantages over the EEPROM. It runs faster and requires less power. However, it can not dominate the market since EEPROM is very cheap. A few manufacturers (like NEC) use FeRAM in RFID, which can benefit from its fast accessing speed. NOR Flash - The NOR flash offers the similar access interface of a RAM. It can be read and programmed on byte or word, but it must be erased by block (or by chip) before programming. Its programming time is also longer than the NAND flash. It can offer so-called XIP (eXecutive In Place) capability for the microprocessors, while NAND flash can not. Although NOR flash is much slower than the memory bus of the modern microprocessors it connects to, it is still acceptable during the initialization period of the whole system. It is widely used in BIOS/bootloader, because the regular microprocessors can not boot from NAND. Mono Stable - in which one of the states is stable, but the other state is unstable (transient). A trigger causes the circuit to enter the unstable state. After entering the unstable state, the circuit will return to the stable state after a set time. Such a circuit is useful for creating a timing period of fixed duration in response to some external event. This circuit is also known as a one shot. Bi Stable - in which the circuit is stable in either state. The circuit can be flipped from one state to the other by an external event or trigger. Astable - in which the circuit is not stable in either state it continually switches from one state to the other. It does not require an input such as a clock pulse. ECL - emitter-coupled logic (ECL), is a logic family that achieves high speed by using an overdriven BJT differential amplifier with singleended input, whose emitter current is limited to avoid the slow saturation region of transistor operation. RTL - register-transfer level (RTL) is a level of abstraction used in describing the operation of a synchronous digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals. Register-transfer-level structural models and abstractions are used in hardware description languages (HDLs) like Verilo g and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived.Design at the RTL level is typical practice in modern digital design. DTL - Diode transistor logic (DTL) is a class of digital circuits that is the direct ancestor of transistor transistor logic. It is called so because the logic gating function (e.g., AND) is performed by a diode network and the amplifying function is performed by a transistor (contrast this with RTL and TTL). TTL - Transistor transistor logic (TTL) is a class of digital circuits built from bipolar junction transistors (BJT) and resistors. It is called transistor transistor logic because both the logic gating function (e.g., AND) and the amplifying function are performed by transistors (contrast this with RTL andDTL).TTL is notable for being a widespread integrated circuit (IC) family used in many applications such as computers, industrial controls, test equipment and instrumentation, consumer electronics, synthesizers, etc. The designation TTL is sometimes used to mean TTL-compatible logic levels, even when not associated directly with TTL integrated circuits, for example as a label on the inputs and outputs of electronic instruments. CMOS - Complementary metal oxide semiconductor (CMOS) is a technology for constructing integrated circuits. CMOS technology is used inmicroprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors(CMOS sensor), data converters, and highly integrated transceivers for many types of communication. Frank Wanlass patented CMOS in 1967 (US patent 3,356,858).Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Significant power is only drawn when the transistors in the CMOS device are switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for exampletransistor-transistor logic (TTL) or NMOS logic. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips. Excitation Table i8080 - The Intel 8080 was the second 8-bit microprocessor designed and manufactured by Intel and was released in April 1974. It was an extended and enhanced variant of the earlier 8008 design, although without binary compatibility. The initial specified clock freqency limit was 2 MHz and with common instructions having execution times of 4,5,7,10 or 11 cycles this meant a few hundred thousand instructions per second. The 8080 has sometimes been labeled "the first truly usable microprocessor", despite the fact that earlier microprocessors were used for calculators and other applications. i8088 - The Intel 8088 microprocessor was a variant of the Intel 8086 and was introduced on July 1, 1979. It had an 8-bit external data bus instead of the 16-bit bus of the 8086. The 16-bit registers and the one megabyte address range were unchanged, however. The original IBM PC was based on the 8088. i4004 - The Intel 4004 was a 4-bit central processing unit (CPU) released by Intel Corporation in 1971. It was the first complete CPU on one chip, and also the first commercially available microprocessor. Such a feat of integration was made possible by the use of then new silicon gate technology allowing a higher number of transistors and a faster speed than was possible before.