10/100/1000/10G Ethernet

Seminar Ethernet
Thorsten Scholz
thorsten.scholz@ibs-networks.de

10/100/1000/10G Ethernet
Seminar Ethernet
2009 Ingenieurbro T. Scholz, www.IBS-Networks.de, all rights reserved No part or whole of this document may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language without prior permission of Ingenieurbro Scholz. This document is provided "as is", without warranty of any kind, neither expressed nor implied, including but not limited to a particular purpose. Ingenieurbro Scholz may make improvements and/or changes in this document without notice at any time. 2

Contents
Overview Ph i l Layer Physical L MAC Layer Frame Forwarding Integrated Circuits Advanced Ethernet Protocols

Ethernet
Overview
History Standards & Specifications ISO/OSI Model Terms and Topology

Overview
History sto y
1972: Early ALOHA Ethernet (Xerox) 1985: First IEEE Standard 1990: 10BASE-T 1995: 100 Mbps 1997: Full Duplex Ethernet 1998: Gigabit Ethernet 2006: 10 Gigabit Ethernet
Source: IEEE802.3 Organization, Robert M. Metcalfe, 1973 IEEE802 3 Organization M Metcalfe

Overview
O ga at o Organization
Ethernet standardized by Institute of Electrical and Electronics Engineers (IEEE) E i
IEEE Working Group 802 (LAN/MAN) Subgroup 3 (Ethernet) http://grouper.ieee.org/groups/802/3/

Standards available at http://standards.ieee.org/getieee802/ Promoters and additional information:

Ethernet Alliance: http://www.ethernetalliance.org

Overview
Sta da ds Standards
Relevant standard is IEEE 802.3-2005
Contains all Ethernet standards until 2005 Standards after 2005 get working titles until new overall standard released Fast Ethernet IEEE 802.3u now integrated into IEEE 802.3-2005 Gigabit Ethernet IEEE 802.3z (mainly Fiber Optic and short reach copper) g ( y p pp ) Gigabit Ethernet IEEE 802.3ab (Twisted Pair, 100m)

IEEE 802.3an 10 Gigabit Ethernet over Copper Twisted Pair 802 3an Some transmission standards refer to FDDI standards
100 Mbps Ethernet refers to ANSI X3T12
7

Overview
Sta da ds Standards
IEEE 802.3 standard is divided in different clauses (chapters)
Containing information on transmission, coding, management, Clause 3: Media access control frame structure Clause 25: Physical Medium Dependent (PMD) sublayer and baseband medium, type 100BASE-TX Clause 28: Physical Layer link signaling for 10 Mb/s, 100 Mb/s, and 1000 Mb/s Auto-Negotiation on Twisted Pair Cl Clause 33: D T i l Equipment (DTE) Power via Media Dependent 33 Data Terminal E i P i M di D d Interface (MDI) Clause 55: Physical Coding Sublayer (PCS) Physical Medium Attachment (PCS), (PMA) sublayer and baseband medium, type 10GBASE-T
8

Overview
Naming System a g Syste
Ethernet standard naming system
1000BASE-T
Transmission Speed S d Transmission Method M h d Medium / Max. Length M L h

10BASE-5 10BROAD-36 10GBASE T 10GBASE-T 100BASE-FX 10GBASE-LX4

10 Mbps, Baseband, 500 m segment length 10 Mbps, Broadband, 3600 m segment length 10 Gbps, Baseband, T isted Pair Gbps Baseband Twisted 100 Mbps, Baseband, Fiber Optic 10 Gbps, Baseband, Long Reach Fiber Optic
9

Overview
Topology opo ogy
Bus topology for 10/100/1000 Mbps
real bus for 10 Mbps coaxial cable Repeater or Hub assisted bus for 10/100/1000 Mbps Twisted Pair

Point-to-point topology for 10 Gbps Star wiring for Twisted Pair cabling Bus wiring for coaxial cable
Twisted Pair Repeater / Hub Coaxial cable

10

Overview
ISO/OSI Layer Organization SO/OS aye O ga at o
ISO/OSI
Application Presentation Session Transport Network Data Link Physical

Ethernet related
Application Presentation Session Transport Network Logical Link Control Media Access Control Physical Medium
11

Web Browser ASCII, HTML HTTP TCP, UDP IP, IP IPX

Ethernet

Overview
ISO/OSI Layer PDU Naming SO/OS aye U a g
Characters belonging to a protocol: l Protocol Data Unit (PDU) Special names for PDUs at different layers Colloquial use: Everythings a packet
Application Presentation Session Transport Network Data Link Physical Segment Datagram Packet Frame -

Medium
12

Overview
ISO/OSI Layer Organization SO/OS aye O ga at o
Every network element implements part or whole of the stack Only identical layers talk to each other Every layer may add header and trailer information Lower layers do not interpret data of higher layers
Transparent transmission

Example: Switch
Media Access Control Physical Medium

Switch Media Access Control Physical Medium

13

Overview
Network Elements et o e e ts
Station or DTE
Implements all layers

Repeater or Hub p
Only implements physical layer, no collision handling

Switch
Implements physical and data-link (MAC) layer

Router
Implements physical, data-link and network layer
14

Overview
Terms a d Definitions e s and e t o s
Ethernet segment: Collision domain: Physical cable between network elements Segments in which a collision propagates

Broadcast domain: Network that is reached by broadcast frame

Switch

Router

Hub

Switch

Hub

Coaxial cable

Hub

Ethernet segment Collision domain Broadcast domain

15

Overview
Terms a d Definitions e s and e t o s
Local Area Network (LAN)
Small range network within a campus

Wide Area Network (WAN) ( )

Long range network, small to medium bandwidth, branch office connection

Metropolitan Area Network (MAN)

Medium range network, high bandwidth, intra-area connection

Global Area Network (GAN)

Long range network, high bandwidth, global connections Internet, ISP-networks
16

Ethernet
Physical Layer
Plugs & Cables Encoding & Line Code Auto-Negotiation PHY Management Power over Ethernet

17

Ethernet Physical Layer

Plugs a d Cables ugs and Cab es
Copper technology
Category 3 cable (Unshielded Twisted Pair = UTP) Category 5 cable (UTP/Shielded TP) Category 6a cable Coaxial cable

Optical technology
Multimode 63 5/125 m 63,5/125 Multimode 50/125 m Si l Singlemode 9/125 m d
18

Ethernet Physical Layer

Coppe ugs a d Cab es Copper Plugs and Cables
Copper technology typically uses RJ45 plugs/jacks for TP

BNC for coaxial 50 Ohm cable

F-Type connector for coaxial 75 Ohm cable

Picture sources: Product Catalog, Conrad Electronic 2008

19

Ethernet Physical Layer

Cab e C asses and Categories Cable Classes a d Catego es
Twisted Pair data cable divided into categories by ANSI/EIA/TIA S d d 568 classes b ISO/IEC Standard 568, l by
EIA/TIA 568
1 2 3 4 5 5e 6 6a 7

ISO/IEC 11801

Bandwidth 1 MHz

Data rate 1 Mbps 4 Mbps 16 Mb Mbps 20 Mbps 100/155 Mbps

Application POTS, ISDN, Doorbell Token Ring (4 Mbps) Ethernet (10BASE-TX, 100BASE-4), ATM Eth t (10BASE TX 100BASE 4) Token Ring (16 Mbps) Fast Ethernet, FDDI, ATM (622 Mbps) Ethernet (1000 Mbps), ATM (1,2 Gbps) Ethernet (10 Gbps)

30 MH MHz

D E EA F FA

100 MHz 250 MHz 500 MHz 600 MHz 1000 MHz

1000 Mbps 10 Gbps

20

Ethernet Physical Layer

Opt ca ugs and Cab es Optical Plugs a d Cables
Optical Ethernet uses variety of connectors, e.g.
ST SC MTRJ LC E2000

Replaceable transceivers for optical Ethernet are widely used

GBIC SFP
Picture sources: Online Shop, glasfaserinfo.de 2008 GBICs: Datasheet Cisco Gigabit Interface Converter, Cisco 2005

21

Ethernet Physical Layer

Plugs a d Cables ugs and Cab es
For Twisted Pair cabling a differential transmission applies Full duplex is achieved by
Separate wires ( p (10/100 Mbps Ethernet, Optical Ethernet) p , p ) Echo cancellation (1000M/10Gbps Ethernet) or Wavelength Multiplexing

Cables must provide crossover function

Different pinouts for DTE (Layer 3 and up, Station, Router, ) and DCE (Hub, Switch)

DTE and DCE devices can be connected through 1:1 cable Devices of same kind must be connected by crossover cable
22

Ethernet Physical Layer

RJ45 Pinout J 5 out
Pinout 10/100 Ethernet Twisted Pair
Switch
Receive+ (1) ReceiveReceive (2) Transmit+ (3) (4) (5) TransmitTransmit (6) (7) (8)

Station
(1) Transmit+ (2) Transmit Transmit(3) Receive+ (4) (5) (6) Receive Receive(7) (8)

Use of more pairs for higher transmission rates

23

Ethernet Physical Layer

Physical Layer Sub aye s ys ca aye Sublayers
Reconciliation Sublayer Optional interface specification between MAC and PHY
Media Independent Interface p

Physical Layer Signaling (PLS) / Physical Coding Sublayer (PCS) Physical Media Attachment (PMA) h i l di h ( ) Physical Medium Dependent (PMD) Medium

24

Ethernet Physical Layer

Physical Layer Sub aye O e e ys ca aye Sublayer Overview
Reconciliation
MII

Reconciliation
MII/GMII

Reconciliation
XGMII
XGXS XGXS XAUI XGMII XSBI

PLS
AUI

PCS

PCS PMA PMD

MDI

MAU

PMA
MDI

PMA PMD
MDI

MDI

Medium

Medium

Medium

1 Mbps 10 Mbps

100 Mbps 1 Gbps

10 Gbps
25

Ethernet Physical Layer

[ ] []

Ethernet Physical Layer

PCS Scrambler: 10GBASE-R CS Sc a b e 0G S
Self-synchronizing Scrambler Length of 57, polynomial: G ( x ) = 1 + x 39 + x 58 Sync header is not scrambled + + 0 1 2 38 39 56 57

76

Ethernet Physical Layer

PCS Gearbox: 10GBASE-R CS Gea bo 0G S
Adjusts bus width from 66 to 16 bits Used for WIS (WAN Interface Sublayer) Used for an optional interface between PCS and PMA Gearbox is optional if PCS and PMA are on the same chip
Data bus width is implementation specific

77

Ethernet Physical Layer

PMA: 10GBASE-SR/LR/ER 0G S S / /
Transmit direction (to PMD)
Provide clock Serialization and transmission of 16 bit data

Receive direction (from PMD)

Bit clock recovery Deserialization Provide link status information

78

Ethernet Physical Layer

PMD: 10GBASE-SR/LR/ER 0G S S / /
Optical transceiver Provides signal detect information based on optical input power Data rate:
9,95328 Gbps 20 ppm (WAN) 10,3125 Gbps 100 ppm (LAN)
10GBASE-SR 10GBASE-SW Wavelength Power Budget Distance 850 nm 7,5 dB 26 300 m 10GBASE-LR 10GBASE-LW 1310 nm 9,4 dB 10 km 10GBASE-ER 10GBASE-EW 1550 nm 15 dB 30 40 km 79

Ethernet Physical Layer

10GBASE-W / WIS Sub aye 0G S S Sublayer
Additional WIS sublayer to adapt to SONET Speed difference adaptation
STM-64, STS/OC-192 transport mode , p WIS stretches Interframe Gap from 96 bit times to 200 bit times This additional time is consumed by the PHY for rate adaptation consumed

Special frame format with path/header information

80

Ethernet Physical Layer

PCS: 10GBASE-T CS 0G S
Forming of 64 bit blocks by 2 XGMII transfers Adding of a control/data bit extends block size to 65 bit Use of Scramblers with 65 bit blocks (EMC purposes)
Ensure that data is not equal on all pairs E Ensure that same data is not send and received th t d t i t d d i d Use of two different scramblers for link partners Need for distinguishable stations: master / slave

82

Ethernet Physical Layer

PCS 64B/65B Code 10GBASE-T CS 6 /65 Code: 0G S
Data and Control code:
S: Start, T: Terminate, D: Data octet, C: Control octet
Data D0D1D2D3D4D5D6D7 S0D1D2D3D4D5D6D7 C0C1C2C3S4D5D6D7 T0C1C2C3C4C5C6C7 D0T1C2C3C4C5C6C7 D0D1T2C3C4C5C6C7 D0D1D2D3D4D5D6T7 Ctrl 0 1 1 1 1 1 1 Type D0 0x78 0x33 0x87 0x99 0xaa 0xff D1 D1 C0 C1 D0 D0 D0 D2 D2 C1 C2 C2 D1 D1 D3 D3 C2 C3 C3 C3 D2 Payload D4 D4 C3 C4 C4 C4 D3 D5 D5 D5 C5 C5 C5 D4 D6 D6 D6 C6 C6 C6 D5 D7 D7 D7 C7 C7 C7 D6

83

Ethernet Physical Layer

PCS: 10GBASE-T CS 0G S
50 blocks of 65 bits are assembled to single group 3250 bits CRC8 checksum is added Auxiliary channel information bit is added Division into 1723 bits LDPC coded (adds 325 check bits) to
3 uncoded and 4 coded bits

3258 bits 3259 bits 2048 bits 3 x 512 bits + 1723 bits

The resulting 7 x 512 bits form 512 7 bit labels containing g g

84

Ethernet Physical Layer

PMA/PMD: 10GBASE-T / 0G S
Single DSQ symbol consists of two transfers
One PAM-16 unprotected 3-Bit transfer One PAM-16 protected 4-Bit transfer

800M transfers per second Resulting maximum frequency is about 400 MHz
55 m with Cat. 6 cabling 100 m with Cat. 6a cabling

88

Ethernet Physical Layer

Ethernet Link Active but no Activity t e et ct e o ct ty
If no frames are transferred (10BASE-T):
16 ms 8 ms Idle Link Test Pulse Repeat

Link Test Pulse is single positive pulse on Line

Only seen by Physical Layer Also referred to as Normal Link Pulse (NLP) Normal Pulse

No transferred frames above 10BASE-T

Idle codes on the line
95

Ethernet Physical Layer

Link Test Pulse est u se
Single positive pulse

Diagram Source: IEEE 802.3-2005 Standard, IEEE 2005

96

Ethernet Physical Layer

Link State for 10BASE-T o 0 S
Link established if 2 10 NLPs are received or data received
Time between NLPs must be within 25 150 ms Ignore time after NLPs 2 7 ms

Link lost after 50 150 ms of inactivity

No NLP received No data received

97

Ethernet Physical Layer

Link State ( 00 Mbps a d abo e) (100 bps and above)
Link established if data received
Link after 330 1000 s of data or idle Special pattern transmitted on idle condition

Link lost after physical loss of signal

Poor signal quality or level

98

Ethernet Physical Layer

Automatic Polarity Co ect o uto at c o a ty Correction
Correction of interchanged RX+ and RX Due to cabling fault

Monitoring of Link Pulse g

Link Pulse is always only positive

If negative (Link) Pulse is detected prior to Link state

Interchange RX+ and RX-

Monitoring of Idle to Start-of-Frame p y performed at the receivers Operation is only p

99

Ethernet Physical Layer

Auto-Negotiation uto egot at o
Automatic setting of speed and duplex 100BASEX uses same link pulses as 10BASE-T, but
Uses bursts of NLP, time between p , pulses is 62,5 7 s , Maximum of 33 possible pulses Time between two bursts: still 16 ms 8 ms (same as 10BASE-T) 10BASE T) Named: Fast Link Pulse (FLP)
10BASE-T, NLP 100BASEX, FLP 1000BASEX, FLP t

16 8 ms 62,5 7 s

100

Ethernet Physical Layer

Auto-Negotiation: Fast Link Pulse uto egot at o ast u se
Link Information is coded in the 33 possible pulses of FLP
Every 2nd pulse is referred to as clock-pulse Every 2nd+1 pulse is referred to as data-pulse Possibility to transfer 16 bit of information

D0 D1 CLK CLK

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13 D14 D15 CLK

Auto-Negotiation performed before link established (100/1000) Nominal length of FLP: 2 ms + 100 ns
101

Ethernet Physical Layer

Auto-Negotiation: G gab t Ethernet uto egot at o Gigabit t e et
No space for Gigabit Ethernet in base page selector field
Transmission of one additional message pages Transmission of two additional unformatted pages

Message page has a value of 0b00000001000 (0x008) 1st unformatted page

Bit U0 U1 U2 U3 U4 U10:U5 Capability / Description 1000BASE-T Manual Master/Slave Configuration 1000BASE-T Manual Master 1000BASE-T Multiport device 1000BASE-T Full-Duplex 1000BASE-T Half-Duplex Reserved 110

Ethernet Physical Layer

Auto-Negotiation: G gab t Ethernet uto egot at o Gigabit t e et
2nd unformatted page
Contains 11 bit Master/Slave seed value in U10:U0

Gigabit Ethernet does a Master/Slave negotiation g g

Master provides clocking Master is always the multiport device (e.g. switch) (e g If both devices are multiport the one with higher seed value becomes Master

T Transfer always consists of all 4 pages f l i t f ll

111

Ethernet Physical Layer

PHY Management a age e t
Management done by dedicated management interface Realized by serial bidirectional interface
Clock line MDC Data line MDIO
C
MDIO MDC

Architecture
Register based addressing 16 bit data transfer Master-Slave bus architecture

Switch S it h IC PHY PHY PHY PHY

Multiple PHYs manageable by one controller

120

Ethernet Physical Layer

PHY Standard Registers Sta da d eg ste s
32 possible register
Registers 0 to 15 are specified Registers 16 to 31 are vendor-specific
Reg 0 1 2, 3 4 5 6 7 8 Description Control Status PHY ID Auto-Negotiation Advertisement Auto-Negotiation Link Partner Abiity Auto-Negotiation Expansion Auto-Negotiation Next Page Transmit Auto-Negotiation Link Partner Next Page 10/100 X X Opt. Opt. Opt. Opt. Opt. Opt. 1000 X X Opt. Opt. Opt. Opt. Opt. Opt.

126

Ethernet Physical Layer

PHY Standard Registers Sta da d eg ste s
Reg 9 10 11 12 13 14 15 Description MASTER-SLAVE Control R i MASTER SLAVE C l Register MASTER-SLAVE Status Register PSE Control Register PSE Status Register MMD Access Control Register MMD Access Address Data Register Extended Status 10/100 Opt. O Opt. Opt. Opt. Opt Opt. Opt. 1000 Opt. O Opt. Opt. Opt. Opt Opt. Opt. X

For 10 Gigabit Ethernet a special extended management interface applies

127

Ethernet Physical Layer

PHY Control Register Co t o eg ste
Control Register (Register 0)
Reg 0.15 0.14 0 14 0.13 0.6 0.12 0.11 0.10 0.9 0.8 0.7 07 0.5 0.4:0 Name Reset Loopback Speed Selection (MSB) Speed Selection (LSB) Auto-Neg Enable Power Down Isolate Restart Auto-Neg Duplex Mode Collision T C lli i Test Unidirect. Enable Reserved Description 1 = PHY reset 1 = enable loopback mode 0.6 0.13 1 1 = Reserved 1 0 = 1000 Mbps 0 1 = 100 Mbps 0 0 = 10 Mbps Mb 1 = enable Auto-Negotiation 1 = power down 1 = electrically isolate PHY y 1 = restart Auto-Negotiation 1 = full duplex 1 = enable COL signal test bl i l Write as 0, ignore on read Description 0 = normal operation 0 = disable loopback mode R/W R/W SC R/W R/W R/W 0 = disable Auto-Negotiation 0 = normal operation 0 = normal operation p 0 = normal operation 0 = half duplex 0 = disable COL signal test di bl i l R/W R/W R/W R/W SC R/W R/W R/W R/W

1 = TX enable link override (if 0.12 = 0 and 0.8 = 1)

128

Ethernet Physical Layer

PHY Status Register eg ste
Status Register (Register 1)
Reg 1.15 1.14 1.13 1.12 1.11 1.10 1.9 1.8 1.7 1.6 16 1.5 1.4 1.3 1.2 1.1 1.0 Name 100BASE-T4 100BASE-X Full 100BASE X 100BASE-X Half 10 Mbps Full 10 Mbps Half 100BASE-T2 Full 100BASE-T2 Half Extended Status Unidir. ability MF P Preamble S bl Sup. Auto-Neg Complete Remote Fault Auto-Neg Ability g y Link Status Jabber Detect Extended Capability Description 1 = PHY 100BASE-T4 capable 1 = PHY 100BASE-X FD capable 1 = PHY 100BASE X HD capable 100BASE-X 1 = PHY 10 Mbps FD capable 1 = PHY 10 Mbps HD capable 1 = PHY 100BASE-T2 FD capable 1 = PHY 100BASE-T2 HD capable 1 = Extended status in Register 15 1 = able to transmit independent of link 1 = accept preamble suppressed frames t bl df 1 = Auto-Negotiation completed 1 = remote fault condition detected 1 = PHY is able to perform Auto-Neg p g 1 = link is up 1 = jabber condition detected 1 = extended register capabilities Description 0 = PHY not 100BASE-T4 capable 0 = PHY not 100BASE-X FD capable 0 = PHY not 100BASE-X HD capable 100BASE X 0 = PHY not 10 Mbps FD capable 0 = PHY not 10 Mbps HD capable 0 = PHY not 100BASE-T2 FD capable 0 = PHY not 100BASE-T2 HD capable 0 = No extended status in Register 15 0 = transmit only with link 0 = not accept preamble sup. frames t t bl f 0 = Auto-Negotiation not completed 0 = no remote fault condition detected 0 = PHY is not able to perform Auto-Neg p g 0 = link is down 0 = no jabber condition detected 0 = no extended register capabilities R/W RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO

129

Ethernet Physical Layer

PHY Extended Status Register te ded eg ste
Extended Status Register (Register 15)
Reg 15.15 15.14 15.13 15.12 15.11:0 Name 1000BASE-X Full 1000BASE-X Half 1000BASE-T Full 1000BASE-T Half Reserved Description 1 = PHY 1000BASE-X FD capable 1 = PHY 1000BASE-X HD capable p 1 = PHY 1000BASE-T FD capable 1 = PHY 1000BASE-T HD capable ignore when read Description 0 = PHY not 1000BASE-X FD capable 0 = PHY not 1000BASE-X HD capable p 0 = PHY not 1000BASE-T FD capable 0 = PHY not 1000BASE-T HD capable R/W RO RO RO RO

130

Ethernet Physical Layer

PHY Management 10 G gab t Ethernet a age e t 0 Gigabit t e et
More management registers needed Extension to the management frame defined
OP O 01 0 TA T Preamble 32 PHY REG 5 5 Data 16 Mgmt format < 10 Gbps 2 2 2

New OP-Codes:

0b00 0b10 Read 0b01 Write 0b11

Address Post-read-increment-address Write Read

PHY address renamed to Port address (PRTAD) REG address renamed to Device address (DEVAD)
131

Ethernet Physical Layer

Power o e Ethernet ( o ) o e over t e et (PoE)
Incorporated into 802.3-2005 Clause 33, prior IEEE 802.3af Used to supply power to end devices (DTE) connected by TP
Primary target: Access Points, IP Phones, IP Camera, Print Server, y g , , , , Definition of Powered Device (PD) and Power Sourcing Equipment (PSE)

Power supplied by
Unused pairs Add power to the data pairs (offset voltage)

Power may be added by Midspan Power Insertion Equipment

Only defined for unused pairs and only defined for 10/100 Mbps
136

Ethernet Physical Layer

PoE: Detection o Powered Device o etect o of o e ed e ce
It must be prevented to power a non-power capable device Powered Device (PD) must be detectable AC based detection for Cisco proprietary pre-802.3af equipment pre-802 3af
Implements low-pass filter between RX and TX P Power S Sourcing E i i Equipment (PSE) sends low-frequency t t d l f tone If PSE receives this tone apply power

Source: Power over Ethernet: Cisco Inline Power and IEEE 802.3af, Cisco Systems 2004

138

Ethernet Physical Layer

PoE: Detection o Powered Device o etect o of o e ed e ce
DC based detection for IEEE 802.3af equipment
PSE applies small voltage Expects to see 25 (19 26,5) kOhm resistance and 150 nF capacitance PSE probes at least two times with different voltages V 1V Test voltage must be between 2,8 and 10 V

Probing is done in intervals no less than 2 ms Aft successful d t ti PSE may optionally classify PD After f l detection ti ll l if
Based on power class 5 Power classes (up to 15,4 Watts)
139

Ethernet
MAC Layer
Tasks & Operation Addressing Frame Format Virtual LANs Flow Control Advanced Chip Functions

144

MAC Layer
Media Access Co t o ISO/OSI Model ed a ccess Control SO/OS ode
Layer 2 in the ISO/OSI reference model Electrical MII interface to physical layer device (PHY) Protocol (frame) interface to layer 3 (e g IP IPX NetBEUI) (e.g. IP, IPX,
Network Data Link Physical Network Logical Link Control Media Access Control Physical Medium
145

MAC Layer
Media Access Co t o Tasks ed a ccess Control as s
Data encapsulation
Framing Addressing Error detection

Media access management

Medium allocation (collision avoidance) Contention resolution (collision handling) Ethernet uses CSMA/CD scheme for half duplex links

146

MAC Layer
Half Duplex Flow Control a up e o Co t o
Half Duplex relies on CSMA/CD protocol Station waits for a quiet period on the medium before sending Half Duplex Back-Pressure Flow Control
If queues are full any incoming packet is collided JAM signal send i l d Sender retries after back-off time

Router

Hub

Switch

Hub

Coaxial cable

Hub

163

MAC Layer
Half Duplex Flow Control a up e o Co t o
Half Duplex Defer Flow Control
If queues are full medium is occupied by receiver Preamble is send continuously Prevents sending of other stations without collisions

Half Duplex Flow Control used up to Gigabit Ethernet

If Hubs/Repeaters are used If Half Duplex is negotiated/set

164

MAC Layer
Half Duplex Gigabit Example a up e G gab t a p e
Cascading of multiple Switches

Half-Duplex

Full-Duplex

Picture Source: Datasheet GigaStack Gigabit Interface Converter, Cisco Systems 2002

165

MAC Layer
Full Duplex Flow Control u up e o Co t o
No CSMA/CD on full duplex links Full-Duplex always involves intelligent devices Flow Control achieved by exchange of frames Uses MAC Control frame structure and addresses
MAC Control frames are not forwarded by switches Destination address is 01-80-C2-00-00-01 (Multicast) Ethernet type is 0x8808 (MAC Control)

Standard: IEEE 802.3x Full Duplex Flow Control p Exchanged frames are named PAUSE
166

MAC Layer
C p u ct o s C C Ge e at o Chip Functions CRC Generation
Transmit direction
Usually chip takes Ethernet frame consisting of DA SA Type Payload CRC is optionally generated by chip

Receive direction
Chip shall check CRC of incoming frame False CRC frame should be optionally dropped (if possible) Usually not possible for end stations N tifi ti in transfer descriptor of wrong checksum among other errors Notification i t f d i t f h k th
170

MAC Layer
C p u ct o s Chip Functions MAC Filtering C te g
Possibility for checking incoming frames against
One or a set of MAC-Address(es) Broadcast address (destination address all FFs)

Incoming frames not matching filter shall be dropped Possibility to bypass filter(s): Promiscuous mode
Necessary for Switch equipment Used by network analysis tools (sniffers)

171

MAC Layer
C p u ct o s Qua ty o Se ce Chip Functions Quality of Service
Quality of Service (QoS) usually a matter of Switches & Routers Classification of frames into 8 different priority classes
Use of flow-based approach (IP level) pp ( ) Use of Class-of-Service / User Priority (MAC level) Use of DSCP/IP Precedence (IP level) Use of VLAN information (MAC level) Use of Port information (PHY level)

For DSCP/TOS chip must parse IP header Chip may implement different queuing strategies
174

MAC Layer
C p u ct o s Chip Functions QoS Queuing Queu g
Threshold based queues (early tail drop queue)

50% Drop Treshold 60% D Drop T h ld Treshold 80% Drop Treshold 100% Drop Treshold

Multiple queues and priority queues

1 V D V Classify y 2

Combinations
179

Ethernet
Integrated Circuits
PHYs Switches Network Interface Card ICs Media Converters

205

Integrated Circuits
10/100/1000 Mbps PHY 0/ 00/ 000 bps
Realtek RTL8211CL Features:
Crossover and Polarity Detection & Correction y Auto-Negotiation Built-in switching regulator for 1,0 V core voltage Built in 10 MII interface for 10/100 Mbps Ethernet RGMII interface for 1000 Mbps Ethernet Management Interface Pi Pincount: 48 t
206

Integrated Circuits
10/100/1000 Mbps PHY 0/ 00/ 000 bps

Picture source: RGMII to GMII Bridge, Reference Design RD1022, Lattice Semiconductor Corp. April 2005

207

Integrated Circuits
10/100/1000 Mbps PHY 0/ 00/ 000 bps
RGMII Analog signals GND LEDs Digital Supply Co e Supply Core Supp y

Picture source: RTL8211CL-GR Integrated 10/100/1000 Gigabit Ethernet Transceiver Datasheet, Rev. 1.1, Realtek Semiconductor Corp. January 2008

208

Integrated Circuits
10/100/1000 Mbps PHY 0/ 00/ 000 bps

Picture source: RTL8211CL-GR Integrated 10/100/1000 Gigabit Ethernet Transceiver Datasheet, Rev. 1.1, Realtek Semiconductor Corp. January 2008

209

Integrated Circuits
10/100/1000 Mbps Switch 0/ 00/ 000 bps S tc
Realtek RTL8366 Features
5 Port Switch plus MII/GMII/RGMII and management interface p g VLAN support QoS (two queues) Port Mirroring Frame counters per port MAC security filtering 4096 entry l k t bl (SRAM) t lookup table Flow control
211

Integrated Circuits
10/100/1000 Mbps Switch 0/ 00/ 000 bps S tc
Realtek RTL8366 Special Transceiver link with 2,5 GHz interface

Picture source: RTL8266/RTL8369 6/9 Port 10/100/1000MbpsSwitch Controller Datasheet, Rev 1.1, Realtek Semiconductor Corp. September 2005

212