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ConferenceConference
on Accelerator
on Accelerator
and Largeand
Experimental
Large Experimental
Physics Control
PhysicsSystems,
Control1999,
Systems
Trieste, Italy
Digital
Baseband Signal Processing Correction Signal
÷250 MHz)
(0÷ ÷250 MHz)
(0÷
ClockDistributionModule TriggerGeneratorBoard
RF DSP RF
A/D D/A
Front-End Amplifier 500MHz
StorageRingRF
External External
Programming Programming
Wideband
Signal
255
interface. Each FPDP is connected to a DSP board by 4 DSP BOARD AND INTERFACE
means of an Interface Module that distributes the MODULE
incoming data to its four DSPs. After processing, the
data from the DSPs are multiplexed following a The DSP board adopted is the Pentek model 4290.
symmetric scheme and are converted to analog by the 8- Figure 3 shows the DSP board block diagram. The four
bit D/A Converter (DAC) VME board. The whole TI-TMS320C6201 DSPs communicate with the
process is synchronized by timing signals provided by the mezzanine Interface Module via high-speed bi-
timing electronics. directional FIFOs (BI-FIFO). The DSP use the BI-FIFO
The transverse feedback processing electronics will be to acquire the bunch position samples and put the
made of two VME chassis: one for the horizontal and correction samples after processing.
one for the vertical plane. Each of them will host one Each of the DSPs is in charge of processing the
ADC board, one DAC board, six DSP boards equipped samples of a given group of bunches. The Interface
with the Interface Module, and one timing board. The Board receives 32-bit words from the FPDP Input and
VME bus will be used to initialize, control and monitor writes them to the BI-FIFOs of the DSPs to which they
the system and to download the programs into the DSP are specifically assigned. At the same time it reads the
boards. BI-FIFOs and sends out the data words to the FPDP
The ADC board, DAC board and DSP boards are Output. The Interface Module acts as a programmable bi-
commercial-of-the-shelf components. The Interface directional commutator: the switching rules are defined
Module and the timing electronics are in-house in a table where, for each of the incoming/outgoing
developments. FPDP words relative to one machine turn, the
destination/source DSP is specified. As more than one
destination can be specified for each of the input words,
3 ADC AND DAC BOARDS
they can be sent e.g. both to the first DSP and to one of
The ADC and DAC boards are respectively the the other three. This allows using one DSP for beam
ADC750 and DAC750 models from Celerity System diagnostics and the other three for the actual feedback.
Incorporated. These boards perform A/D and D/A The table is downloaded on the Interface Module at the
conversions at up to 750 Msample/s with 8-bit resolution. time of system initialization.
For the Feedback System we operate them at the bunch The TI TMS320C6201 is a fixed point DSP clocked at
crossing frequency, i.e. 500 Msample/s, using a clock 200 MHz (5 ns instruction cycle). The VLIW (Very Long
derived from the main RF signal and connected to the Instruction Word) architecture allows to execute up to
external clock inputs. eight instructions every cycle. The challenging problem
The 8-bit data out of the A/D converter of the ADC is to be able to execute all of the necessary operations in
board are first stacked in 32-bit words and then one revolution period (864 ns). With a highly optimized
sequentially distributed to the six FPDP output ports. The code written in Assembler, the time needed to execute all
six ports work at 20.8 MHz. the operations for a 5-tap Finite Impulse Response (FIR)
An external trigger signal (Start-ADC) provided by the filter is 600 ns, that is shorter than the revolution time.
timing electronics starts the conversion and the de- Another critical issue is the data transfer between the
multiplexing process. Being the bunch number (432)
Interface DSP Board
divisible by 6 (number of FPDPs) times 4 (number of Module
DSP 0
Mezzanine
Connector
Global Bus
byte per FPDP word), each FPDP port always carries the BI Local
FIFO Bus
samples relative to the same group of 72 bunches. This is Local
Memory
the basic principle of the bunch-by-bunch feedback,
FPDP
where each group of bunches is processed always by the IN DSP 1 Global
Programmable Logic
Memory
Mezzanine
Connector
FPDP BI
OUT
In addition, some data buffering is performed by the use FIFO
VME
Local
of FIFOs to de-couple from possible variations in the Memory Interface
BI
timing electronics starts the multiplexing and the FIFO
Local
conversion process. Start-DAC is generated with a Memory
External Programming
programmable delay relative to the Start-ADC in order to
make the correction kicks synchronous with the bunches
Figure 3: Block diagram of the DSP Board and the
passing through the kicker. Interface Module
256
DSP and the BI-FIFO. Simulations carried out with the strong cavity High Order Mode is excited. In order to
machine/feedback simulator show that the feedback fully exploit the available power, it can be convenient to
performance degrades with betatron tune shift when the increase the open-loop feedback gain and to make the
number of processing revolution periods increases. feedback saturate when the oscillations are large. On the
Therefore, the time the data remain in the DSP board other hand, high gain can lead to a greater residual error
must be minimized as well as any delay on every when the oscillation is damped. The possibility of
component of the feedback chain. A thorough use of the changing the filter parameters on-the-fly when the
BI-FIFO facilities, interrupts and Direct Memory Access feedback is running allows to change the gain and/or the
(DMA) allows to transfer data in a very effective way filter type and apply the best algorithm in the different
without interference with the CPU. phases of a mode damping.
With a convenient programming of the DSPs, one
5 TIMING ELECTRONICS uncontrolled bunch can be used for betatron tune
measurements while applying the feedback to the others.
The transverse feedback system relies on a very strict
With the measured tune value it is possible to re-
timing. The A/D converter must sample the analog
calculate the filter parameters and change them when the
signal synchronously to the bunch crossing at the BPM
feedback is running, thus compensating for machine tune
and the D/A converter must generate the analog
shifts.
corrections in phase with the bunches passing through
Thanks to the programmability of the DSPs and the
the kicker. Moreover, the Start-ADC and Start-DAC
Interface Module the same processing electronics will be
trigger signals must start the conversions in a
used for the Swiss Light Source transverse feedback
deterministic and repeatable way with respect to the
system and may be adopted also for longitudinal multi-
bunch structure to let every DSP work with a known
bunch feedback systems.
group of bunches. A new design has been undertaken to
fulfil these requirements. It consists of a Clock
Distribution Module and a Trigger Generator Board 7 STATUS
(figure 2). A transverse bunch-by-bunch digital feedback system
The Clock Distribution Module accepts a 500 MHz has been designed at ELETTRA for damping multi-
sinusoidal signal from the storage ring RF and generates bunch instabilities. The digital processing electronics is
two 500 MHz Differential ECL (DECL) signals which realized by a programmable modular multi-processor
are the clocks used by the ADC and DAC boards. The architecture.
phase of the two output signals can be independently The system mainly relies on standard COTS
programmed in a 5 ns range with 5 ps resolution. components. The ADC/DAC boards have been ordered
The Trigger Generator Board is a VME general- while a sample DSP board is under test. The timing
purpose timing board. For the transverse feedback system electronics and the Interface Module are in-house
it provides two DECL signals: Start-ADC and Start- projects: the first prototypes are foreseen by the end of
DAC. By conveniently programming the board via the November.
VME interface it is possible to place the rising edge of The feedback project is a collaboration with the Swiss
the two trigger signals in any position of the revolution Light Source which is developing the kickers and the RF
period with a resolution of 10 ps. The Start-DAC must front-end. The system will be installed and
follow the Start-ADC and the time between the two has commissioned at ELETTRA: the first tests are foreseen
to take into account the delay of the data flowing from by the end of 1999.
the ADC to the DAC board.
8 AKNOWLEDGEMENTS
6 SYSTEM FEATURES The authors wish to thank the "Detector and
Being the feedback core realized by software Instrumentation Group" of the Experimental Division
programs, a high degree of flexibility in the and the "Instrumentation Group" of the Accelerator
implementation of the control algorithms is provided. Division for their contribution to the project through the
The basic requirements for the feedback algorithm are development of the Interface Module and timing
DC rejection and appropriate gain/phase at the betatron modules.
frequency. A 3-tap FIR is the most simple digital filter
which can be used. However, many features can be added REFERENCES
when a more complicated filter is implemented. Studies
[1] D. Bulfone et al., "Design Considerations for the
have been carried out with the support of a ELETTRA Transverse Multi-bunch Feedback", PAC
machine/feedback simulator [1] using 5-tap FIR and '99, New York, March 1999.
Infinite Impulse Response (IIR) digital filters. [2] M. Lonza, "Theory of the Transverse Multi-bunch
The maximum RF power supplied by the amplifier can Feedback at ELETTRA", ST Technical Note: to be
be a limitation of the feedback performance when a published.
257