8-Bit Atmel Micro Controller

Features
High Performance, Low Power Atmel AVR 8-Bit Microcontroller Advanced RISC Architecture 135 Powerful Instructions Most Single Clock Cycle Execution 32 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16MHz On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments 64K/128K/256KBytes of In-System Self-Programmable Flash 4Kbytes EEPROM 8Kbytes Internal SRAM Write/Erase Cycles:10,000 Flash/100,000 EEPROM Data retention: 20 years at 85C/ 100 years at 25C Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security Endurance: Up to 64Kbytes Optional External Memory Space Atmel QTouch library support Capacitive touch buttons, sliders and wheels QTouch and QMatrix acquisition Up to 64 sense channels JTAG (IEEE std. 1149.1 compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode Real Time Counter with Separate Oscillator Four 8-bit PWM Channels Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits (ATmega1281/2561, ATmega640/1280/2560) Output Compare Modulator 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) Master/Slave SPI Serial Interface Byte Oriented 2-wire Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560) 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561) 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560) RoHS/Fully Green Temperature Range: -40C to 85C Industrial Ultra-Low Power Consumption Active Mode: 1MHz, 1.8V: 500A Power-down Mode: 0.1A at 1.8V Speed Grade: ATmega640V/ATmega1280V/ATmega1281V: 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V ATmega2560V/ATmega2561V: 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V ATmega640/ATmega1280/ATmega1281: 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V ATmega2560/ATmega2561: 0 - 16MHz @ 4.5V - 5.5V
8-bit Atmel Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash ATmega640/V ATmega1280/V ATmega1281/V ATmega2560/V ATmega2561/V Preliminary Summary
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
1. Pin Configurations
Figure 1-1. TQFP-pinout ATmega640/1280/2560
PK2 (ADC10/PCINT18) PK3 (ADC11/PCINT19) PK4 (ADC12/PCINT20) PK5 (ADC13/PCINT21) PK6 (ADC14/PCINT22) PK7 (ADC15/PCINT23) PK0 (ADC8/PCINT16) PK1 (ADC9/PCINT17)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF4 (ADC4/TCK)
PF0 (ADC0)
PF7 (ADC7/TDI)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PA0 (AD0)
PA1 (AD1)
77
100 99 (OC0B) PG5 (RXD0/PCINT8) PE0 (TXD0) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (CLKO/ICP3/INT7) PE7 VCC GND (RXD2) PH0 (TXD2) PH1 (XCK2) PH2 (OC4A) PH3 (OC4B) PH4 (OC4C) PH5 (OC2B) PH6 (SS/PCINT0) PB0 (SCK/PCINT1) PB1 (MOSI/PCINT2) PB2 (MISO/PCINT3) PB3 (OC2A/PCINT4) PB4 (OC1A/PCINT5) PB5 (OC1B/PCINT6) PB6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
PA2 (AD2)
76 75 74 PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PJ6 (PCINT15) PJ5 (PCINT14) PJ4 (PCINT13) PJ3 (PCINT12) PJ2 (XCK3/PCINT11) PJ1 (TXD3/PCINT10) PJ0 (RXD3/PCINT9) GND VCC PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR) 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50
AVCC
AREF
GND
GND
VCC
46
INDEX CORNER
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PJ7
47
48
49
(OC0A/OC1C/PCINT7) PB7
VCC
GND
(ICP4) PL0
(RXD1/INT2) PD2
(SCL/INT0) PD0
(XCK1) PD5
(T4) PH7
(T1) PD6
(TXD1/INT3) PD3
(OC5A) PL3
(OC5B) PL4
(OC5C) PL5
(TOSC2) PG3
(TOSC1) PG4
(SDA/INT1) PD1
(ICP1) PD4
(ICP5) PL1
(T0) PD7
PL6
(T5) PL2
XTAL2
RESET
XTAL1
PL7
2
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ATmega640/1280/1281/2560/2561
Figure 1-2. CBGA-pinout ATmega640/1280/2560
Top view
1 A B C D E F G H J K 2 3 4 5 6 7 8 9 10 10 9 8
Bottom view
7 6 5 4 3 2 1 A B C D E F G H J K
Table 1-1.
1 A B C D E F G H J K Note: GND AVCC PE2 PE3 PE7 VCC GND PB3 PH7 PB7
CBGA-pinout ATmega640/1280/2560
2 AREF PG5 PE0 PE4 PH0 PH4 PB1 PB4 PG3 PG4 3 PF0 PF1 PE1 PE5 PH1 PH6 PB2 RESET PB6 VCC 4 PF2 PF3 PF4 PE6 PH3 PB0 PB5 PL1 PL0 GND 5 PF5 PF6 PF7 PH2 PH5 PL4 PL2 PL3 XTAL2 XTAL1 6 PK0 PK1 PK2 PA4 PJ6 PD1 PD0 PL7 PL6 PL5 7 PK3 PK4 PK5 PA5 PJ5 PJ1 PD5 PD4 PD3 PD2 8 PK6 PK7 PJ7 PA6 PJ4 PJ0 PC5 PC4 PC1 PD6 9 GND PA0 PA1 PA7 PJ3 PC7 PC6 PC3 PC0 PD7 10 VCC PA2 PA3 PG2 PJ2 GND VCC PC2 PG1 PG0
The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2.
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Figure 1-3. Pinout ATmega1281/2561
PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF4 (ADC4/TCK) PF7 (ADC7/TDI)
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PA0 (AD0)
PA1 (AD1) 50
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(OC0B) PG5 (RXD0/PCINT8/PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (ICP3/CLKO/INT7) PE7 (SS/PCINT0) PB0 (SCK/ PCINT1) PB1 (MOSI/ PCINT2) PB2 (MISO/ PCINT3) PB3 (OC2A/ PCINT4) PB4 (OC1A/PCINT5) PB5 (OC1B/PCINT6) PB6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
INDEX CORNER
49
PA2 (AD2)
AVCC
GND
AREF
GND
VCC
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 (T1) PD6
(RXD1/INT2) PD2
(SCL/INT0) PD0
(TXD1/INT3) PD3
(OC0A/OC1C/PCINT7) PB7
(XCK1) PD5
(ICP1) PD4
VCC
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.
(SDA/INT1) PD1
(TOSC2) PG3
(TOSC1) PG4
(T0) PD7
GND
XTAL2
RESET
XTAL1
32
4
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ATmega640/1280/1281/2560/2561
2. Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Block Diagram
PF7..0
VCC
Figure 2-1.
PK7..0
P J7..0
PE7..0
RESET
Power Supervision POR/ BOD & RESET
PORT F (8)
PORT K (8)
PORT J (8)
PORT E (8)
GND
Watchdog Timer
Watchdog Oscillator
JTAG
A/D Converter
Analog Comparator
USART 0
XTAL1
Oscillator Circuits / Clock Generation
EEPROM
Internal Bandgap reference
16 bit T/C 3
XTAL2
CPU
16 bit T/C 5
USART 3
P A7..0
PORT A (8)
16 bit T/C 4 USART 1
PG5..0
PORT G (6)
XRAM
FLASH
SRAM
16 bit T/C 1
PC7..0
PORT C (8)
TWI
SPI
8 bit T/C 0
8 bit T/C 2
USART 2
NOTE: Shaded parts only available in the 100-pin version. Complete functionality for the ADC, T/C4, and T/C5 only available in the 100-pin version.
PORT D (8) PORT B (8) PORT H (8) PORT L (8)
PD7..0
PB7..0
PH7..0
PL7..0
5
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The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8 Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, 4 USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the Onchip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheelsfunctionality into AVR microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent KeySuppression (AKS) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using Atmels high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
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2.2
Comparison Between ATmega1281/2561 and ATmega640/1280/2560

Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1 summarizes the different configurations for the six devices.
Table 2-1.
Device ATmega640 ATmega1280 ATmega1281 ATmega2560 ATmega2561
Configuration Summary
Flash 64KB 128KB 128KB 256KB 256KB EEPROM 4KB 4KB 4KB 4KB 4KB RAM 8KB 8KB 8KB 8KB 8KB General Purpose I/O pins 86 86 54 86 54 16 bits resolution PWM channels 12 12 6 12 6 Serial USARTs 4 4 2 4 2 ADC Channels 16 16 8 16 8
2.3
2.3.1
Pin Descriptions
VCC Digital supply voltage.
2.3.2
GND Ground.
2.3.3
Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 78. special features of the
2.3.4
Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 79. special features of the
2.3.5
Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
7
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on page 82. 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 83. 2.3.7 special features of the
Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 86. special features of the
2.3.8
Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface.
2.3.9
Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various ATmega640/1280/1281/2560/2561 as listed on page 90. special features of the
2.3.10
Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
8
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 92. 2.3.11 Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 94. 2.3.12 Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter. Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port K also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 96. 2.3.13 Port L (PL7..PL0) Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 98. 2.3.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in System and Reset Characteristics on page 372. Shorter pulses are not guaranteed to generate a reset. 2.3.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.16 XTAL2 Output from the inverting Oscillator amplifier.
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2.3.17 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter.
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3. Resources
A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr.
4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85C or 100 years at 25C.
6. Capacitive touch sensing

The AtmelQTouch Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing APIs to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Atmel website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library User Guide - also available for download from the Atmel website.
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7. Register Summary
Address
(0x1FF) ... (0x13F) (0x13E) (0x13D) (0x13C) (0x13B) (0x13A) (0x139) (0x138) (0x137) (0x136) (0x135) (0x134) (0x133) (0x132) (0x131) (0x130) (0x12F) (0x12E) (0x12D) (0x12C) (0x12B) (0x12A) (0x129) (0x128) (0x127) (0x126) (0x125) (0x124) (0x123) (0x122) (0x121) (0x120) (0x11F) (0x11E) (0x11D) (0x11C) (0x11B) (0x11A) (0x119) (0x118) (0x117) (0x116) (0x115) (0x114) (0x113) (0x112) (0x111) (0x110) (0x10F) (0x10E) (0x10D) (0x10C) (0x10B) (0x10A) (0x109) (0x108) (0x107) (0x106) (0x105) (0x104) (0x103) (0x102) (0x101)
Name
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR3 UBRR3H UBRR3L Reserved UCSR3C UCSR3B UCSR3A Reserved Reserved OCR5CH OCR5CL OCR5BH OCR5BL OCR5AH OCR5AL ICR5H ICR5L TCNT5H TCNT5L Reserved TCCR5C TCCR5B TCCR5A Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PORTL DDRL PINL PORTK DDRK PINK PORTJ DDRJ PINJ PORTH DDRH
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Page
USART3 I/O Data Register UMSEL31 RXCIE3 RXC3 UMSEL30 TXCIE3 TXC3 UPM31 UDRIE3 UDRE3 UPM30 RXEN3 FE3 USBS3 TXEN3 DOR3 USART3 Baud Rate Register High Byte UCSZ31 UCSZ32 UPE3 UCSZ30 RXB83 U2X3 UCPOL3 TXB83 MPCM3 USART3 Baud Rate Register Low Byte
222 227 227 239 238 238
Timer/Counter5 - Output Compare Register C High Byte Timer/Counter5 - Output Compare Register C Low Byte Timer/Counter5 - Output Compare Register B High Byte Timer/Counter5 - Output Compare Register B Low Byte Timer/Counter5 - Output Compare Register A High Byte Timer/Counter5 - Output Compare Register A Low Byte Timer/Counter5 - Input Capture Register High Byte Timer/Counter5 - Input Capture Register Low Byte Timer/Counter5 - Counter Register High Byte Timer/Counter5 - Counter Register Low Byte FOC5A ICNC5 COM5A1 PORTL7 DDL7 PINL7 PORTK7 DDK7 PINK7 PORTJ7 DDJ7 PINJ7 PORTH7 DDH7 FOC5B ICES5 COM5A0 PORTL6 DDL6 PINL6 PORTK6 DDK6 PINK6 PORTJ6 DDJ6 PINJ6 PORTH6 DDH6 FOC5C COM5B1 PORTL5 DDL5 PINL5 PORTK5 DDK5 PINK5 PORTJ5 DDJ5 PINJ5 PORTH5 DDH5 WGM53 COM5B0 PORTL4 DDL4 PINL4 PORTK4 DDK4 PINK4 PORTJ4 DDJ4 PINJ4 PORTH4 DDH4 WGM52 COM5C1 PORTL3 DDL3 PINL3 PORTK3 DDK3 PINK3 PORTJ3 DDJ3 PINJ3 PORTH3 DDH3 CS52 COM5C0 PORTL2 DDL2 PINL2 PORTK2 DDK2 PINK2 PORTJ2 DDJ2 PINJ2 PORTH2 DDH2 CS51 WGM51 PORTL1 DDL1 PINL1 PORTK1 DDK1 PINK1 PORTJ1 DDJ1 PINJ1 PORTH1 DDH1 CS50 WGM50 PORTL0 DDL0 PINL0 PORTK0 DDK0 PINK0 PORTJ0 DDJ0 PINJ0 PORTH0 DDH0
165 165 165 165 164 164 165 165 163 163 162 160 158
104 104 104 103 103 103 103 103 103 102 103
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ATmega640/1280/1281/2560/2561
Address
(0x100) (0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0) (0xBF)
Name
PINH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UDR2 UBRR2H UBRR2L Reserved UCSR2C UCSR2B UCSR2A Reserved UDR1 UBRR1H UBRR1L Reserved UCSR1C UCSR1B UCSR1A Reserved UDR0 UBRR0H UBRR0L Reserved UCSR0C UCSR0B UCSR0A Reserved
Bit 7
PINH7 UMSEL21 RXCIE2 RXC2 UMSEL11 RXCIE1 RXC1 UMSEL01 RXCIE0 RXC0 -
Bit 6
PINH6 UMSEL20 TXCIE2 TXC2 UMSEL10 TXCIE1 TXC1 UMSEL00 TXCIE0 TXC0 -
Bit 5
PINH5 UPM21 UDRIE2 UDRE2 UPM11 UDRIE1 UDRE1 UPM01 UDRIE0 UDRE0 -
Bit 4
PINH4 UPM20 RXEN2 FE2 UPM10 RXEN1 FE1 UPM00 RXEN0 FE0 -
Bit 3
PINH3 -
Bit 2
PINH2 -
Bit 1
PINH1 -
Bit 0
PINH0 -
Page
103
USART2 I/O Data Register USART2 Baud Rate Register High Byte USBS2 TXEN2 DOR2 UCSZ21 UCSZ22 UPE2 UCSZ20 RXB82 U2X2 UCPOL2 TXB82 MPCM2 USART2 Baud Rate Register Low Byte
222 227 227 239 238 238 222 USART1 Baud Rate Register High Byte 227 227 UCSZ11 UCSZ12 UPE1 UCSZ10 RXB81 U2X1 UCPOL1 TXB81 MPCM1 222 USART0 Baud Rate Register High Byte 227 227 UCSZ01 UCSZ02 UPE0 UCSZ00 RXB80 U2X0 UCPOL0 TXB80 MPCM0 239 238 238 239 238 238
USART1 I/O Data Register USART1 Baud Rate Register Low Byte USBS1 TXEN1 DOR1 -
USART0 I/O Data Register USART0 Baud Rate Register Low Byte USBS0 TXEN0 DOR0 -
13
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
Address
(0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E) (0x7D)
Name
Reserved TWAMR TWCR TWDR TWAR TWSR TWBR Reserved ASSR Reserved OCR2B OCR2A TCNT2 TCCR2B TCCR2A Reserved Reserved OCR4CH OCR4CL OCR4BH OCR4BL OCR4AH OCR4AL ICR4H ICR4L TCNT4H TCNT4L Reserved TCCR4C TCCR4B TCCR4A Reserved Reserved OCR3CH OCR3CL OCR3BH OCR3BL OCR3AH OCR3AL ICR3H ICR3L TCNT3H TCNT3L Reserved TCCR3C TCCR3B TCCR3A Reserved Reserved OCR1CH OCR1CL OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L Reserved TCCR1C TCCR1B TCCR1A DIDR1 DIDR0 DIDR2
Bit 7
TWAM6 TWINT TWA6 TWS7 -
Bit 6
TWAM5 TWEA TWA5 TWS6 EXCLK -
Bit 5
TWAM4 TWSTA TWA4 TWS5 AS2 -
Bit 4
TWAM3 TWSTO TWA3 TWS4 TCN2UB -
Bit 3
TWAM2 TWWC TWA2 TWS3 OCR2AUB -
Bit 2
TWAM1 TWEN TWA1 OCR2BUB -
Bit 1
TWAM0 TWA0 TWPS1 TCR2AUB -
Bit 0
TWIE TWGCE TWPS0 TCR2BUB -
Page
269 266 268 269 268 266 184 191 191 191
2-wire Serial Interface Data Register
2-wire Serial Interface Bit Rate Register
Timer/Counter2 Output Compare Register B Timer/Counter2 Output Compare Register A Timer/Counter2 (8 Bit) FOC2A COM2A1 FOC2B COM2A0 COM2B1 COM2B0 WGM22 CS22 CS21 WGM21 CS20 WGM20 -
190 191
Timer/Counter4 - Output Compare Register C High Byte Timer/Counter4 - Output Compare Register C Low Byte Timer/Counter4 - Output Compare Register B High Byte Timer/Counter4 - Output Compare Register B Low Byte Timer/Counter4 - Output Compare Register A High Byte Timer/Counter4 - Output Compare Register A Low Byte Timer/Counter4 - Input Capture Register High Byte Timer/Counter4 - Input Capture Register Low Byte Timer/Counter4 - Counter Register High Byte Timer/Counter4 - Counter Register Low Byte FOC4A ICNC4 COM4A1 FOC4B ICES4 COM4A0 FOC4C COM4B1 WGM43 COM4B0 WGM42 COM4C1 CS42 COM4C0 CS41 WGM41 CS40 WGM40 -
164 164 164 164 164 164 165 165 163 163 162 160 158
Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte FOC3A ICNC3 COM3A1 FOC3B ICES3 COM3A0 FOC3C COM3B1 WGM33 COM3B0 WGM32 COM3C1 CS32 COM3C0 CS31 WGM31 CS30 WGM30 -
164 164 164 164 163 163 165 165 162 162 162 160 158
Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte FOC1A ICNC1 COM1A1 ADC7D ADC15D FOC1B ICES1 COM1A0 ADC6D ADC14D FOC1C COM1B1 ADC5D ADC13D WGM13 COM1B0 ADC4D ADC12D WGM12 COM1C1 ADC3D ADC11D CS12 COM1C0 ADC2D ADC10D CS11 WGM11 AIN1D ADC1D ADC9D CS10 WGM10 AIN0D ADC0D ADC8D
163 163 163 163 163 163 165 165 162 162 161 160 158 274 295 295
14
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
Address
(0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B)
Name
ADMUX ADCSRB ADCSRA ADCH ADCL Reserved Reserved XMCRB XMCRA TIMSK5 TIMSK4 TIMSK3 TIMSK2 TIMSK1 TIMSK0 PCMSK2 PCMSK1 PCMSK0 EICRB EICRA PCICR Reserved OSCCAL PRR1 PRR0 Reserved Reserved CLKPR WDTCSR SREG SPH SPL EIND RAMPZ Reserved Reserved Reserved SPMCSR Reserved MCUCR MCUSR SMCR Reserved OCDR ACSR Reserved SPDR SPSR SPCR GPIOR2 GPIOR1 Reserved OCR0B OCR0A TCNT0 TCCR0B TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR PCIFR
Bit 7
REFS1 ADEN
Bit 6
REFS0 ACME ADSC
Bit 5
ADLAR ADATE
Bit 4
MUX4 ADIF
Bit 3
MUX3 MUX5 ADIE
Bit 2
MUX2 ADTS2 ADPS2
Bit 1
MUX1 ADTS1 ADPS1
Bit 0
MUX0 ADTS0 ADPS0
Page
289 272, 290, 294 292 294 294
ADC Data Register High byte ADC Data Register Low byte XMBK SRE PCINT23 PCINT15 PCINT7 ISC71 ISC31 PRTWI CLKPCE WDIF I SP15 SP7 SPMIE JTD OCDR7 ACD SPIF SPIE SRL2 PCINT22 PCINT14 PCINT6 ISC70 ISC30 PRTIM2 WDIE T SP14 SP6 RWWSB OCDR6 ACBG WCOL SPE SRL1 ICIE5 ICIE4 ICIE3 ICIE1 PCINT21 PCINT13 PCINT5 ISC61 ISC21 PRTIM5 PRTIM0 WDP3 H SP13 SP5 SIGRD OCDR5 ACO DORD SRL0 PCINT20 PCINT12 PCINT4 ISC60 ISC20 PRTIM4 WDCE S SP12 SP4 RWWSRE PUD JTRF OCDR4 ACI MSTR SRW11 OCIE5C OCIE4C OCIE3C OCIE1C PCINT19 PCINT11 PCINT3 ISC51 ISC11 PRTIM3 PRTIM1 CLKPS3 WDE V SP11 SP3 BLBSET WDRF SM2 OCDR3 ACIE SPI Data Register CPOL CPHA SPR1 SPI2X SPR0 XMM2 SRW10 OCIE5B OCIE4B OCIE3B OCIE2B OCIE1B OCIE0B PCINT18 PCINT10 PCINT2 ISC50 ISC10 PCIE2 PRUSART3 PRSPI CLKPS2 WDP2 N SP10 SP2 PGWRT BORF SM1 OCDR2 ACIC XMM1 SRW01 OCIE5A OCIE4A OCIE3A OCIE2A OCIE1A OCIE0A PCINT17 PCINT9 PCINT1 ISC41 ISC01 PCIE1 PRUSART2 PRUSART0 CLKPS1 WDP1 Z SP9 SP1 RAMPZ1 PGERS IVSEL EXTRF SM0 OCDR1 ACIS1 XMM0 SRW00 TOIE5 TOIE4 TOIE3 TOIE2 TOIE1 TOIE0 PCINT16 PCINT8 PCINT0 ISC40 ISC00 PCIE0 -
38 37 166 166 166 193 166 134 116 116 117 114 113 115 50
Oscillator Calibration Register PRUSART1 PRADC CLKPS0 WDP0 C SP8 SP0 EIND0 RAMPZ0 SPMEN IVCE PORF SE OCDR0 ACIS0 -
57 56
50 67 14 16 16 17 17
332 67, 110, 100, 308 308 52 301 272 204 203 202 37 37
General Purpose I/O Register 2 General Purpose I/O Register 1 Timer/Counter0 Output Compare Register B Timer/Counter0 Output Compare Register A Timer/Counter0 (8 Bit) FOC0A COM0A1 TSM FOC0B COM0A0 COM0B1 COM0B0 EEPROM Data Register INT7 INTF7 INT6 INTF6 EEPM1 INT5 INTF5 EEPM0 INT4 INTF4 EERIE INT3 INTF3 EEMPE INT2 INTF2 PCIF2 EEPE INT1 INTF1 PCIF1 EERE INT0 INTF0 PCIF0 General Purpose I/O Register 0 WGM02 CS02 CS01 WGM01 PSRASY CS00 WGM00 PSRSYNC
133 133 133 132 129 170, 194 35 35 35 35 37 115 115 116
EEPROM Address Register High Byte
EEPROM Address Register Low Byte
15
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
Address
0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
TIFR5 TIFR4 TIFR3 TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA
Bit 7
PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7
Bit 6
PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6
Bit 5
ICF5 ICF4 ICF3 ICF1 PORTG5 DDG5 PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5
Bit 4
PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4
Bit 3
OCF5C OCF4C OCF3C OCF1C PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3
Bit 2
OCF5B OCF4B OCF3B OCF2B OCF1B OCF0B PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2
Bit 1
OCF5A OCF4A OCF3A OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1
Bit 0
TOV5 TOV4 TOV3 TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0
Page
166 167 167 193 167 134 102 102 102 101 102 102 101 101 102 101 101 101 101 101 101 100 100 100 100 100 100
Notes:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 4. When using the I/O specific commands IN and OUT, the I/O addresses $00 - $3F must be used. When addressing I/O registers as data space using LD and ST instructions, $20 must be added to these addresses. The ATmega640/1280/1281/2560/2561 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from $60 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
16
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
8. Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP EIJMP JMP RCALL ICALL EICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k
Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k Add two Registers
Description
Rd Rd + Rr
Operation
Flags
Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, H Z, C, N, V, S Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, C, N, V Z, C, N, V, H Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V Z, N, V None Z, C Z, C Z, C Z, C Z, C Z, C None None None None None None None None None I None Z, N, V, C, H Z, N, V, C, H Z, N, V, C, H None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 3 4 4 4 5 5 5 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers Ones Complement Twos Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Extended Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Extended Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd Rr Rd Rd K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF Rd Rd 0x00 Rd Rd Rd v K Rd Rd (0xFF - K) Rd Rd + 1 Rd Rd 1 Rd Rd Rd Rd Rd Rd Rd 0xFF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr
1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1

PC PC + k + 1 PC Z PC (EIND:Z) PC k PC PC + k + 1 PC Z PC (EIND:Z) PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd Rr Rd Rr C Rd K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1
R1:R0 (Rd x Rr) <<
BRANCH INSTRUCTIONS
17
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
Mnemonics
BRVS BRVC BRIE BRID SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH DATA TRANSFER INSTRUCTIONS MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM ELPM ELPM Rd, Z Rd, Z Rd, Z+ Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Extended Load Program Memory Extended Load Program Memory Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 R0 (RAMPZ:Z) Rd (RAMPZ:Z) None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 k k k k P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
Operands
Description
Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared Branch if Interrupt Enabled Branch if Interrupt Disabled Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG
Operation
if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0
Flags
None None None None None None Z, C, N, V Z, C, N, V Z, C, N, V Z, C, N, V Z, C, N, V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H
#Clocks
1/2 1/2 1/2 1/2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT AND BIT-TEST INSTRUCTIONS
18
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
Mnemonics
ELPM SPM IN OUT PUSH POP NOP SLEEP WDR BREAK Rd, P P, Rr Rr Rd
Operands
Rd, Z+ Store Program Memory In Port Out Port Push Register on Stack
Description
Extended Load Program Memory (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Operation
Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1
Flags
None None None None None None None
#Clocks
3 1 1 2 2 1 1 1 N/A
Pop Register from Stack No Operation Sleep Watchdog Reset Break
MCU CONTROL INSTRUCTIONS (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None
Note:
EICALL and EIJMP do not exist in ATmega640/1280/1281. ELPM does not exist in ATmega640.
19
2549NSAVR05/11
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9. Ordering Information
9.1 ATmega640
Power Supply Ordering Code ATmega640V-8AU ATmega640V-8AUR(4) ATmega640V-8CU ATmega640V-8CUR(4) ATmega640-16AU ATmega640-16AUR(4) ATmega640-16CU ATmega640-16CUR(4) Package(1)(3) 100A 100A 100C1 100C1 100A 100A 100C1 100C1 Operation Range Speed (MHz)(2)
1.8 - 5.5V
Industrial (-40C to 85C)
16
2.7 - 5.5V
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. See Speed Grades on page 369. 3. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 4. Tape & Reel
Package Type 100A 100C1 100-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 100-ball, Chip Ball Grid Array (CBGA)
20
2549NSAVR05/11
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9.2 ATmega1280
Power Supply Ordering Code ATmega1280V-8AU ATmega1280V-8AUR(4) ATmega1280V-8CU ATmega1280V-8CUR(4) ATmega1280-16AU ATmega1280-16AUR(4) ATmega1280-16CU ATmega1280-16CUR(4) Package(1)(3) 100A 100A 100C1 100C1 100A 100A 100C1 100C1 Operation Range
Speed (MHz)(2)
1.8V - 5.5V
16
2.7V - 5.5V
Notes:
21
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
9.3 ATmega1281
Power Supply Ordering Code ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) Package(1)(3) 64A 64A 64M2 64M2 64A 64A 64M2 64M2 Operation Range
Speed (MHz)(2)
1.8 - 5.5V
16
2.7 - 5.5V
Notes:
Package Type 64A 64M2 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9mm 9mm 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
22
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
9.4 ATmega2560
Power Supply Ordering Code ATmega2560V-8AU ATmega2560V-8AUR(4) ATmega2560V-8CU ATmega2560V-8CUR(4) ATmega2560-16AU ATmega2560-16AUR(4) ATmega2560-16CU ATmega2560-16CUR(4) Package(1)(3) 100A 100A 100C1 100C1 100A 100A 100C1 100C1 Operation Range
Speed (MHz)(2)
1.8V - 5.5V
16
4.5V - 5.5V
Notes:
23
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
9.5 ATmega2561
Power Supply Ordering Code ATmega1281V-8AU ATmega1281V-8AUR(4) ATmega1281V-8MU ATmega1281V-8MUR(4) ATmega1281-16AU ATmega1281-16AUR(4) ATmega1281-16MU ATmega1281-16MUR(4) Package(1)(3) 64A 64A 64M2 64M2 64A 64A 64M2 64M2 Operation Range
Speed (MHz)(2)
1.8V - 5.5V
16
4.5V - 5.5V
Notes:
Package Type 64A 64M2 64-lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 64-pad, 9mm 9mm 1.0mm Body, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)
24
2549NSAVR05/11
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10. Packaging Information
10.1 100A
PIN 1 B
PIN 1 IDENTIFIER
E1
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN 0.05 0.95 15.75 13.90 15.75 13.90 0.17 0.09 0.45 NOM 1.00 16.00 14.00 16.00 14.00 0.50 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.27 0.20 0.75 Note 2 Note 2 NOTE
A2
Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum.
E1 B C L e
2010-10-20 2325 Orchard Parkway San Jose, CA 95131 TITLE 100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 100A REV. D
25
2549NSAVR05/11
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10.2 100C1
0.12 Z
Marked A1 Identifier
SIDE VIEW
TOP VIEW
A A1
e
0.90 TYP
10
A
A1 Corner
9 8 7 6 5 4 3 2 1
0.90 TYP
B C D E F
COMMON DIMENSIONS (Unit of Measure = mm) D1 SYMBOL A A1 D E1 E D1 E1

BOTTOM VIEW
b
G H I J
MIN 1.10 0.30 8.90 8.90 7.10 7.10 0.35
NOM 0.35 9.00 9.00 7.20 7.20 0.40 0.80 TYP
MAX 1.20 0.40 9.10 9.10 7.30 7.30 0.45
NOTE
5/25/06 2325 Orchard Parkway San Jose, CA 95131 TITLE 100C1, 100-ball, 9 x 9 x 1.2 mm Body, Ball Pitch 0.80 mm Chip Array BGA Package (CBGA) DRAWING NO. 100C1 REV. A
26
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
10.3 64A
PIN 1 e
PIN 1 IDENTIFIER
E1
D1 D
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM 1.00 16.00 14.00 16.00 14.00 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
Notes: 1.This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
2010-10-20 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. C
27
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
10.4 64M2
Marked Pin# 1 ID
C
TOP VIEW
SEATING PLANE
A1 A3 A
K L D2
Pin #1 Corner
0.08 C
SIDE VIEW
1 2 3
Option A
Pin #1 Triangle
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL

Option B
Pin #1 Chamfer (C 0.30)
E2
MIN 0.80
NOM 0.90 0.02 0.20 REF
MAX 1.00 0.05
NOTE
A A1 A3 b
0.18 8.90 7.50 8.90 7.50
0.25 9.00 7.65 9.00 7.65 0.50 BSC
0.30 9.10 7.80 9.10 7.80
K b e
Option C
D
Pin #1 Notch (0.20 R)
D2 E E2 e L
BOTTOM VIEW
0.35 0.20
0.40 0.27
0.45 0.40
Notes: 1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD. 2. Dimension and tolerance conform to ASMEY14.5M-1994.
2010-10-20 TITLE 2325 Orchard Parkway 64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, San Jose, CA 95131 7.65 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 64M2 REV. E
28
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11. Errata
11.1 ATmega640 rev. B
Inaccurate ADC conversion in differential mode with 200 gain High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200 gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB. Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
11.2
ATmega640 rev. A
11.3
ATmega1280 rev. B
Inaccurate ADC conversion in differential mode with 200 gain High current consumption in sleep mode 1. Inaccurate ADC conversion in differential mode with 200 gain With AVCC <3.6V, random conversions will be inaccurate. Typical absolute accuracy may reach 64 LSB.
29
2549NSAVR05/11
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Problem Fix/Workaround None. 2. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.
11.4
ATmega1280 rev. A
11.5
ATmega1281 rev. B
30
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11.6 ATmega1281 rev. A
11.7
ATmega2560 rev. F
Not sampled.
11.8
ATmega2560 rev. E
No known errata.
11.9
ATmega2560 rev. D
Not sampled.
11.10 ATmega2560 rev. C

High current consumption in sleep mode 1. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.

Not sampled.
31
2549NSAVR05/11
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1.
Non-Read-While-Write area of flash not functional Part does not work under 2.4 volts Incorrect ADC reading in differential mode Internal ADC reference has too low value IN/OUT instructions may be executed twice when Stack is in external RAM EEPROM read from application code does not work in Lock Bit Mode 3
Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected. The problem is related to the speed of the part when reading the flash of this area. Problem Fix/Workaround - Only use the first 248K of the flash. - If boot functionality is needed, run the code in the Non-Read-While-Write area at maximum 1/4th of the maximum frequency of the device at any given voltage. This is done by writing the CLKPR register before entering the boot section of the code.
2. Part does not work under 2.4 volts The part does not execute code correctly below 2.4 volts. Problem Fix/Workaround Do not use the part at voltages below 2.4 volts. 3. Incorrect ADC reading in differential mode The ADC has high noise in differential mode. It can give up to 7 LSB error. Problem Fix/Workaround Use only the 7 MSB of the result when using the ADC in differential mode. 4. Internal ADC reference has too low value The internal ADC reference has a value lower than specified. Problem Fix/Workaround - Use AVCC or external reference. - The actual value of the reference can be measured by applying a known voltage to the ADC when using the internal reference. The result when doing later conversions can then be calibrated. 5. IN/OUT instructions may be executed twice when Stack is in external RAM If either an IN or an OUT instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. In some cases this will cause a problem, for example: - If reading SREG it will appear that the I-flag is cleared. - If writing to the PIN registers, the port will toggle twice. - If reading registers with interrupt flags, the flags will appear to be cleared.
32
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Problem Fix/Workaround There are two application work-arounds, where selecting one of them, will be omitting the issue: - Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions. - Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code. Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
11.13 ATmega2561 rev. F

Not sampled.
11.14 ATmega2561 rev. E

No known errata.
11.15 ATmega2561 rev. D

Not sampled.
11.16 ATmega2561 rev. C

High current consumption in sleep mode. 1. High current consumption in sleep mode If a pending interrupt cannot wake the part up from the selected sleep mode, the current consumption will increase during sleep when executing the SLEEP instruction directly after a SEI instruction. Problem Fix/Workaround Before entering sleep, interrupts not used to wake the part from the sleep mode should be disabled.

Not sampled.

Non-Read-While-Write area of flash not functional Part does not work under 2.4 Volts Incorrect ADC reading in differential mode Internal ADC reference has too low value IN/OUT instructions may be executed twice when Stack is in external RAM EEPROM read from application code does not work in Lock Bit Mode 3
33
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
1. Non-Read-While-Write area of flash not functional The Non-Read-While-Write area of the flash is not working as expected. The problem is related to the speed of the part when reading the flash of this area. Problem Fix/Workaround - Only use the first 248K of the flash. - If boot functionality is needed, run the code in the Non-Read-While-Write area at maximum 1/4th of the maximum frequency of the device at any given voltage. This is done by writing the CLKPR register before entering the boot section of the code. 2. Part does not work under 2.4 volts The part does not execute code correctly below 2.4 volts. Problem Fix/Workaround Do not use the part at voltages below 2.4 volts. 3. Incorrect ADC reading in differential mode The ADC has high noise in differential mode. It can give up to 7 LSB error. Problem Fix/Workaround Use only the 7 MSB of the result when using the ADC in differential mode. 4. Internal ADC reference has too low value The internal ADC reference has a value lower than specified. Problem Fix/Workaround - Use AVCC or external reference. - The actual value of the reference can be measured by applying a known voltage to the ADC when using the internal reference. The result when doing later conversions can then be calibrated. 5. IN/OUT instructions may be executed twice when Stack is in external RAM If either an IN or an OUT instruction is executed directly before an interrupt occurs and the stack pointer is located in external ram, the instruction will be executed twice. In some cases this will cause a problem, for example: - If reading SREG it will appear that the I-flag is cleared. - If writing to the PIN registers, the port will toggle twice. - If reading registers with interrupt flags, the flags will appear to be cleared. Problem Fix/Workaround There are two application workarounds, where selecting one of them, will be omitting the issue: - Replace IN and OUT with LD/LDS/LDD and ST/STS/STD instructions. - Use internal RAM for stack pointer. 6. EEPROM read from application code does not work in Lock Bit Mode 3 When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does not work from the application code.
34
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
Problem Fix/Workaround Do not set Lock Bit Protection Mode 3 when the application code needs to read from EEPROM.
35
2549NSAVR05/11
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12. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision.
12.1
Rev. 2549N-05/11
1. 2. 3. 4. 5. 6. 7. Added Atmel QTouch Library Support and QTouch Sensing Capablity Features Updated Cross-reference in Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0 on page 68 Updated Assembly codes in section USART Initialization on page 210 Added Standard Power-On Reset on page 372. Added Enhanced Power-On Reset on page 373. Updated Figure 32-13 on page 393 Updated Ordering Information on page 20 to include Tape & Reel devices.
12.2
Rev. 2549M-09/10
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Updated typos in Figure 26-9 on page 285 and in Figure 26-10 on page 285. Note is added below Table 1-1 on page 3. The values for typical characteristics in Table 31-9 on page 377 and Table 31-10 on page 378, has been rounded. Units for tRST and tBOD in Table 31-3 on page 372 have been changed from ns to s. The figure text for Table 31-2 on page 371 has been changed. Text in first column in Table 30-3 on page 336 has been changed from Fuse Low Byte to Extended Fuse Byte. The text in Power Reduction Register on page 54 has been changed. The value of the inductor in Figure 26-9 on page 285 and Figure 26-10 on page 285 has been changed to 10 H. Port A has been changed into Port K in the first paragraph of Features on page 275. Minimum wait delay for tWD_EEPROM in Table 30-16 on page 351 has been changed from 9.0ms to 3.6ms Dimension A3 is added in 64M2 on page 28. Several cross-references are corrected. COM0A1:0 on page 130 is corrected to COM0B1:0. Corrected some Figure and Table numbering. Updated Section 10.6 Low Frequency Crystal Oscillator on page 45.
12.3
Rev. 2549L-08/07
1. 2. 3. 4. 5. 6. Updated note in Table 10-11 on page 47. Updated Table 10-3 on page 43, Table 10-5 on page 44, Table 10-9 on page 47. Updated typos in DC Characteristics on page 367 Updated Clock Characteristics on page 371 Updated External Clock Drive on page 371. Added System and Reset Characteristics on page 372.
36
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
7. 8. 9. Updated SPI Timing Characteristics on page 375. Updated ADC Characteristics Preliminary Data on page 377. Updated ordering code in ATmega640 on page 20.
12.4
Rev. 2549K-01/07
1. 2. 3. 4. 5. Updated Table 1-1 on page 3. Updated Pin Descriptions on page 7. Updated Stack Pointer on page 16. Updated Bit 1 EEPE: EEPROM Programming Enable on page 36. Updated Assembly code example in Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. on page 63. Updated EIMSK External Interrupt Mask Register on page 115. Updated Bit description in PCIFR Pin Change Interrupt Flag Register on page 116. Updated code example in USART Initialization on page 210. Updated Figure 26-8 on page 284. Updated DC Characteristics on page 367.
6: 7. 8. 9. 10.
12.5
Rev. 2549J-09/06
1. 2. 3. 4. 5. 6. Updated on page 46. Updated code example in Moving Interrupts Between Application and Boot Section on page 109. Updated Timer/Counter Prescaler on page 186. Updated Device Identification Register on page 303. Updated Signature Bytes on page 338. Updated Instruction Set Summary on page 17.
12.6
Rev. 2549I-07/06
1. 2. Added Data Retention on page 11. Updated Table 16-3 on page 129, Table 16-6 on page 130, Table 16-8 on page 131, Table 17-2 on page 148, Table 17-4 on page 159, Table 17-5 on page 160, Table 20-3 on page 187, Table 20-6 on page 188 and Table 20-8 on page 189. Updated Fast PWM Mode on page 150.
3.
12.7
Rev. 2549H-06/06
1. 2. 3. Updated on page 46. Updated OSCCAL Oscillator Calibration Register on page 50. Added Table 31-1 on page 371.
37
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
12.8 Rev. 2549G-06/06
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Updated Features on page 1. Added Figure 1-2 on page 3, Table 1-1 on page 3. Updated on page 46. Updated Power Management and Sleep Modes on page 52. Updated note for Table 12-1 on page 68. Updated Figure 26-9 on page 285 and Figure 26-10 on page 285. Updated Setting the Boot Loader Lock Bits by SPM on page 324. Updated Ordering Information on page 20. Added Package information 100C1 on page 26. Updated Errata on page 29.
12.9
Rev. 2549F-04/06
1. 2. 3. 4. Updated Figure 9-3 on page 31, Figure 9-4 on page 31 and Figure 9-5 on page 32. Updated Table 20-2 on page 187 and Table 20-3 on page 187. Updated Features in ADC Analog to Digital Converter on page 275. Updated Fuse Bits on page 336.
12.10 Rev. 2549E-04/06

1. 2. 3. 4. 5. 5. 6. Updated Features on page 1. Updated Table 12-1 on page 62. Updated note for Table 12-1 on page 62. Updated Bit 6 ACBG: Analog Comparator Bandgap Select on page 273. Updated Prescaling and Conversion Timing on page 278. Updated Maximum speed vs. VCC on page 373. Updated Ordering Information on page 20.
12.11 Rev. 2549D-12/05

1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Advanced Information Status changed to Preliminary. Changed number of I/O Ports from 51 to 54. Updatet typos in TCCR0A Timer/Counter Control Register A on page 129. Updated Features in ADC Analog to Digital Converter on page 275. Updated Operation inADC Analog to Digital Converter on page 275 Updated Stabilizing Time in Changing Channel or Reference Selection on page 282. Updated Figure 26-1 on page 276, Figure 26-9 on page 285, Figure 26-10 on page 285. Updated Text in ADCSRB ADC Control and Status Register B on page 290. Updated Note for Table 4 on page 43, Table 13-15 on page 86, Table 26-3 on page 289 and Table 26-6 on page 295. Updated Table 31-9 on page 377 and Table 31-10 on page 378. Updated Filling the Temporary Buffer (Page Loading) on page 323. Updated Typical Characteristics on page 385. Updated Packaging Information on page 25. Updated Errata on page 29.
38
2549NSAVR05/11
ATmega640/1280/1281/2560/2561
12.12 Rev. 2549C-09/05
1. 2. 3. 4. 5. 6. 7. 8. Updated Speed Grade in section Features on page 1. Added Resources on page 11. Updated SPI Serial Peripheral Interface on page 195. In Slave mode, low and high period SPI clock must be larger than 2 CPU cycles. Updated Bit Rate Generator Unit on page 247. Updated Maximum speed vs. VCC on page 373. Updated Ordering Information on page 20. Updated Packaging Information on page 25. Package 64M1 replaced by 64M2. Updated Errata on page 29.
12.13 Rev. 2549B-05/05

1. 2. 3. 4. JTAG ID/Signature for ATmega640 updated: 0x9608. Updated Table 13-7 on page 81. Updated Serial Programming Instruction set on page 352. Updated Errata on page 29.
12.14 Rev. 2549A-03/05

1. Initial version.
39
2549NSAVR05/11
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com
Atmel Asia Limited Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369
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Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
2549NSAVR05/11

8-Bit Atmel Micro Controller

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8-Bit Atmel Micro Controller

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Features

Power Supervision POR/ BOD & RESET

Internal Bandgap reference

16 bit T/C 4 USART 1

Comparison Between ATmega1281/2561 and ATmega640/1280/2560

4. About Code Examples

6. Capacitive touch sensing

222 227 227 239 238 238

2-wire Serial Interface Data Register

2-wire Serial Interface Bit Rate Register

EEPROM Address Register High Byte

EEPROM Address Register Low Byte

1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1

R1:R0 (Rd x Rr) <<

BIT AND BIT-TEST INSTRUCTIONS

Pop Register from Stack No Operation Sleep Watchdog Reset Break

Industrial (-40C to 85C)

Industrial (-40C to 85C)

Industrial (-40C to 85C)

Industrial (-40C to 85C)

Industrial (-40C to 85C)

COMMON DIMENSIONS (Unit of Measure = mm) D1 SYMBOL A A1 D E1 E D1 E1

MIN 1.10 0.30 8.90 8.90 7.10 7.10 0.35

NOM 0.35 9.00 9.00 7.20 7.20 0.40 0.80 TYP

MAX 1.20 0.40 9.10 9.10 7.30 7.30 0.45

COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL

NOM 0.90 0.02 0.20 REF

MAX 1.00 0.05

0.18 8.90 7.50 8.90 7.50

0.25 9.00 7.65 9.00 7.65 0.50 BSC

0.30 9.10 7.80 9.10 7.80

11.10 ATmega2560 rev. C

11.11 ATmega2560 rev. B

11.13 ATmega2561 rev. F

11.14 ATmega2561 rev. E

11.15 ATmega2561 rev. D

11.16 ATmega2561 rev. C

11.17 ATmega2561 rev. B

11.18 ATmega2561 rev. A

12. Datasheet Revision History

12.10 Rev. 2549E-04/06

12.11 Rev. 2549D-12/05

12.13 Rev. 2549B-05/05

12.14 Rev. 2549A-03/05

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