DigitalLogicprimer:

IveusedLogicCircuitsbyNoelMorris,McGrawHillbuttherewouldbemanyotherbooks.

Decimalversusbinarynumbers
Decimalsystemradixorbaseisthenumber10,i.e.0,1,2,3,4,5,6,7,8,9intheunitscolumnthenuse
10scolumnand100scolumnandsoon,or100,then101then102etc.so251102x102+5x101+1x100
InOctalorbase8,thenumbersare0,1,2,3,4,5,6,7unitscolumnthenusethe8scolumnandthe
64scolumn,i.e.80,81,82etc.so25182x82+5x81+1x80128+40+1=16510
InHexadecimalorbase16anothercommonnumberingsystemthenumbersare
0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f,intheunitsor160columnthenfollowedbythe16sor161columnand
thenthe256scolumnor162,so25116512+80+1660810
Inbase2thenyousimplyhave0and1intheunitsor20column,then0or1inthe2sor21column
then0or1inthe4sor22column,andsoon.Changingtheconventionthathastheleastsignificant
bitontherightmostsidethenyouhavethefollowingresult.
NumberSystem
Base

Binary
2
24,23,22,21,20
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
10000
10001
10010
10011
10100
10101
10110
10111
11000

Octal
8
81,80
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
20
21
22
23
24
25
26
27
30

Decimal
10
101,100
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

Hexadecimal
16
161,160
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18

Whatsgoodaboutthebase8andbase16numbersystems,ormostcommonlyreferredtoasoctal
orhexadecimal,isthatyoucangodirectlyandquicklytothebase2system(whichisusedasthe
switchinputsorlogiclevelsintheunderlyinglogic):
i.e.82,then81,then80mapsontothebinarysystemascolumnsof000,000,000i.e.the100s,10s
andunitscolumnsinbase8,mapdirectlyontogroupsofthreezerosandlikewisethebase16
system161,160mapsdirectlytothebinarysystemingroupsof4zeros,theform0000,0000.
i.e.
162,161,160

82,81,80

0000,0000,0000

000,000,000

Forexamplethenumbers:8,9,10,11,14and20inhexadecimalconverttooctalandbinary,as
follows:
Base16Hexadecimal
161,160
Numbers
8
9
10
11
14
20

Base8Octal
82,81,80

010
011
020remember10hexis16dec
021
024
040remember20hexis32dec

Base2Binary
25,24,23,22,21,20

000,000,000,000,001,000
000,000,000,000,001,001
000,000,000,000,010,000
000,000,000,000,010,001
000,000,000,000,010,100
000,000,000,000,100,000

Anditisstraightforwardtogofrombinarytooctal(againingroupsof3):11011112=001,101,111
which=1,82+101,81+111,80or1578
Forbinarytohexyouwouldusegroupsof4,i.e.11011112=0110,1111=6f16
Orworkingbackwardsfromabovetable1000002=100,000=408or0010,0000=2016
Convertingbetweenotherradices
Base2tobase1011012=23+22+21+20or8s+4s+2s+1sor11012>1310
Base12tobase10i.e.1b2a12=123+122+121+120or1x123+11x122+2X12+10=334610

Converting20010toradix8keepdividingby8i.e.200/8gives25remainder0thendividethe25by
8giving3remainder1thentrytodividethe3by8giving0remainder3or310,i.e.:
8)200
8)25remainder0leastsignificantdigit
8)3remainder1
0

remainder3mostsignificantdigit

Answeris20010=3108i.e3x64+1x8+0

RepresentationsofLogicNetworks:
Therearethreemaintypesoflogicgates:NOT(ortheinverter),AND(anditsinverseorcomplement
NAND),&OR(anditscomplementtheNORgate)andtheselogicgatescanhaveonlyoneinputin
thecaseoftheNOTgateorinverterandtwoormoreinthecaseofthe,AND,NAND,ORorNOR
gatesandthediagramsareasfollows:

Thenumberoftransistorsusedtorealisetheselogicgatesis2n,wherenisthenumberoflogic
inputs.Strictlyspeakingthefaninandfanoutofaparticularlogicgatedescribesthenumberof
logiclines,orinputs,totheinputortheoutputofalogicgate,respectivelyandthisinturnrelates
tothenumberofotherlogicgateoutputsandinputsthatthelogicgateisconnectedto,and
thereforethecapacitance(viathetransistorgates)connectedtotheinputandtheoutputofa
particularlogicgate.Thisinturnrelatestothetimerequiredforthelogiclevelontheinputor
outputtoreachitsfinalvalueandinthecaseofCMOSthiswillbeeither0V(sometimesreferred
toasVSS)orVDD(whichisusuallythelogichighvalueeg5Vor3.3V).

Nowdevelopthetruthtablesforthedifferentgates,andtryextendingthistothethreeandpossibly
4inputversions(boring!)

Drawthetransistorleveldiagramforthetwoandpossiblythreeinputgatesshownabovenote
thatinthecaseoftheANDandORgatesyoumayalsoneedtouseaninverter!,andcheckby
inspectionthatthegatesoutputbehaviourwillindeedfollowthelogicfunctiondescribedbythe

gatebylookingatthetruthtable(theoutputcolumnbehaviourversusthelogicalfunctionforthe
inputvariables).

ThesimplesttwoinputgatestorealiseusingenhancementmodeMOSFETsaretheNORandNAND
gates.

LogicRulesorLaws
NOTNOTAor
A+0=A
A.0=0
A.1=A
A+1=1
A+A=A
A.A=A
1
.

Commutativelaw:

Associativelaw:......

. .

Distributivelaw:

. . ..

. . .

..

...

. . .

DeMorganstheorem:

. . .

..

Soifafunctionifgivenbyf,thenthiscanbereformulatedusingthetheoremsshownabove,eg.
.

Whichmayormaynothelp!
Memoryelementscanbedividedintovolatileandnonvolatiletypes,i.e.thosethatrequire
continuouspowerandthosethatdonotandcanretaintheirmemorystatewithouttheadditionof
power,eg.ThemagneticdomainsonaharddiscorthedualgateEEPROMtransistorfromlectures.

Thevolatiletypeofmemorycanbefurthersubdividedintotwofurthervariationsstaticand
dynamic.Thestatictypeofvolatilememoryrequiredcontinuous(i.e.stable)inputsandpower
supplyvoltages.Thedynamictypeofmemorystoresthelogicvalueforashorttimeintheabsence
ofadditionallogicalinputsorpowersupplies.Indynamicthelogicvalueisstoreddynamicallyasthe
chargeonacapacitor(andcanthusleakaway,ordecay,throughtheofftransistorsofthe
programminggateandthusrequiredperiodicrefreshment).

Inthecaseofthestaticmemoryelementthesimpleststaticmemorycellcanberepresentedinthe
formoftwocrosscoupledNORgates(ortwocrosscoupledNANDgatesprecededbyinverters).

ThisisoftenreferredtoasanSRflipfloporalatch.WhichstandsforSet,Resetwhicharesimply
theinputsandtheoutputsare,byconvention,referredtoastheQandnotQ.Thiscrosscouplingof
thetwogatesactslikewhatElectricalEngineerscallaBistablecircuit,which,asitsnamesuggests,
hastwobistablestates.Thereforedependingontheinput(setorreset)theoutputwillreflectthe
inputIfbothsetandresetarezerothentheoutputQorthequeuedstateofthelatchwillbe
retainedunchangedasbefore,butifS=1andR=0thentheQoutputofthelatchwillchangetothe
setvalue,i.e.1.IfS=0andR=1thenQwillbeforcedto0.
Thusthestateofthelatchdependsontheinputandthelatchcanbeeithersetorresetandthis
representsasinglebitofamemoryblockanarrayoftheselatchesiscalledaregisterandanarray
ofsuchlatchesorregisterscanmakeupablockofmemorywhichcanretaineitherabinary

numberrepresentingdataorabinarynumberwhichcanbetreatedasaninstruction.Thenthe
contentsoftheseregisterscanbeadded,subtracted,multipliedetcorotherwisemanipulated
UnfortunatelytheoutputofthissimpletypeoflatchisundefinedifbothS=1andR=1,sothisis
generallyavoided!andthiscanbeeasilydonebyusingonlyasinglesetlineandaninverterto
generatetheresetsignal,sothatthelatchiseithersetorresetthisisreferredtoasaDatalatch
(seeUyemurap424)whatdoesthislooklikeintermsoftheCMOStransistors?

Twocrosscoupledinverterscanalsoactasasimplelatchandatransmissiongatecanbeusedto
loaddataontothislatch.

Problems:
Drawboththegatelevelandthetransistorleveldiagramsforthefollowingtwologicexpressions.

1)

2)

. .

3) Writedownthelogicalfunctionrepresentedbythegateleveldiagramshownbelow.
ConstructannFETarraywhichwouldrealisethisfunctionthenusetheseriesparalleltrickto
realiseafullCMOSimplementationofthelogicfunction.