Catapult C Synthesis

Catapult C Synthesis:
A Game Changer for Full-Chip High-level Synthesis

Thomas Bollaert
Product Marketing Manager, Catapult C Design Creation and Synthesis Division
Agenda
Designing in the Digital Era The Case for High-Level Synthesis Catapult C Overview A Game Changing Technology A Game Changing Ecosystem Summary
2010 Mentor Graphics Corp. Company Confidential
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Designing in the Digital Era
Systems have evolved, design methodologies havent
1990
0.8m Directedtests 0.35m Codecoverage
2000
130nm Vera/E Assertions 65mm SystemVerilog
2010
32nm UVM
RTL
3 A Game Changer for Full-Chip High-level Synthesis www.mentor.com
The RTL Design and Verification Bottleneck

Significant manual step at the heart of the design process Disconnect between specification and implementation Verification problems backfire in later stages of the flow
Where most bugs are being introduced
RTL not guaranteed to meet requirements
Due to a broken design methodology
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The Catapult C Synthesis Opportunity

Automatic generation of high quality RTL from ANSI C/C++ and SystemC
Bridges the gap between specification and implementation
void func (short a[N], for (int i=0; i<N; i++) { if (cond) z+=a[i]*b[i]; else
Dramatically shortens the design cycle

Designs are correct-by-construction Manual errors are avoided Time-consuming iterations are eliminated
Differentiated and verified designs in silicon, 20x faster!
RTL
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Traditional Flow vs. Catapult C Approach

Functional Specification Architectural Specification Architectural Constraints C++ Functional Specification Catapult C Synthesis RTL Verification
RTL Coding and Optimization
RTLSynthesis RTL Debug
RTL Verification
Faster path to verified RTL Faster creation of derivatives Faster time to innovation
RTL Synthesis
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Requirements for Full-Chip HLS

Interconnect Synthesis Complex Interfaces
Bus Interface
Deinterlacer
Image Enhancer
Arbitrated Bus Interface
Local Cache Video Decoder Demux Memory Controller
Algorithmic Unit
7 A Game Changer for Full-Chip High-level Synthesis
Low-Power RTL
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Control Unit
Algorithmic Synthesis
Interactively explore microarchitectural solutions
// Source code int mac(char data[N], char coef[N]) { int accum=0; for (int i=0; i<N; i++) accum += data[i] * coef[i]; return accum; }
Source code remains unchanged Easily generate design variants Rapidly converge on optimal solution
Full control over the architecture

Area vs. Latency Parallelism vs. Throughput Memories vs. Registers
// Synthesis constraints directive set CLOCK_PERIOD 5 directive set UNROLL yes directive set PIPELINE_INIT_INTERVAL 1 directive set DESIGN_GOAL area
Advanced algorithmic optimizations

Deep scheduling heuristics Fine and coarse grain sharing Bit-width minimization Common sub expression analysis Carry-save-adder transformation
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Control-Logic Synthesis
Supports modeling, verification and synthesis of control-logic
Synchronous reactive systems Implicit control from ANSI C++ Explicit control from SystemC
switch ( state.read() ) { case write_rxbuffer : en_count = wrbuff; if (rxeof == 1) { state = read_rxbuffer; rxrdy = 1; load = 1; rst_count = 1; } break;
Specialized control-logic optimizations for superior QoR

Conditional feedback optimization Ramp-up logic removal 1-bit logic Flow control optimization Mux tree flattening
100% 90% 80% 70% 60% 50% 40% 30% Mux Logi c FSMComb FSMReg Regi s ters Functi ona l
Control-logic synthesis without area or timing compromise

20% 10% 0% w/oOpti mi za ti ons
default area
wi thOpti mi za ti areawithons optimizations
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Low-Power Optimization
Automates prevailing low-power design techniques
Multiple clock domains Multi-level clock-gating Memory access minimization Resource sharing Frequency exploration
D DIN EN CLK CLK
DOUT
Synthesizes power management infrastructure

No source code changes Design status indicators Global enables CDC synchronizers
DIN
DOUT
EN CLK
CLK
Avoids tedious and low-level manual transformations

Eliminates errors Saves time and effort
10
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Hierarchical and Interconnect Synthesis

Synthesizes pipelined and parallel hardware hierarchy from sequential source code Infers modules from C++ functions, loops or scopes
void top(int *a,int *b,int *c,int *z) { int t[N]; func1: for (int i=0; i<N; i++) t[i] = a[i]+b[i]; func2: for (int i=0; i<N; i++) z[i] = t[N-1-i]*c[i]; }
Simple and flexible coding style Most productive abstraction level High exploration potential
Automatically creates interconnect and control logic

FIFOs Shared RAMs Ping-pong buffers
ping
func1
pong
func2
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Complex Bus Interfaces / Cycle-Accurate

// cycle accurate bus master void bus_master::write (T addr, T data) { haddr.write(addr); hwrite.write(1); SC_MODULE(top) { public: sc_in<bool> sc_in<bool> bus_master wait(); // wait 1 clock cycle hwdata.write(data); clk; rst; bus_if; do { wait(); // wait 1 clock cycle } while (hready.read()==0); }
// Modular I/O
SC_CTOR(master) { SC_CTHREAD(proc, clk.pos()); reset_signal_is(rst,true); } void proc() { for (int addr=0; addr<IMG_SZ; addr++) { pixel = bus_if.read( OFFSET_A + addr ); gray = ((r * pixel.range( 7, 0)) + (g * pixel.range(15, 8)) + (b * pixel.range(23,16))); bus_if.write( OFFSET_B + addr, gray ); } } }
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Complex Bus Interfaces / TLM2.0

// TLM2.0 bus master void tlm_bus_master::transfer( unsigned adrs, unsigned &data, tlm::tlm_command cmd) { // Build a TLM2.0 generic payload tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; set_payload(trans, cmd, adrs, data); clk; rst; bus_if; // TLM2.0 Blocking transport call socket->b_transport( *trans, delay ); // Check response status and delay if ( trans->is_response_error() ) SC_REPORT_ERROR("TLM-2", "Response error from b_transport"); } void tlm_bus_master::write(T adrs, T data) { transfer(adrs, data, tlm::TLM_WRITE_COMMAND); }
SC_MODULE(top) { public: sc_in<bool> sc_in<bool> tlm_bus_master SC_CTOR(master) { SC_THREAD(proc); }
// Modular I/O
void proc() { for (int addr=0; addr<IMG_SZ; addr++) { pixel = bus_if.read( OFFSET_A + addr ); gray = ((r * pixel.range( 7, 0)) + (g * pixel.range(15, 8)) + (b * pixel.range(23,16))); bus_if.write( OFFSET_B + addr, gray ); } } }
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Taking HLS to the Next Level
ComplexBusInterfaces LowPowerOptimization ControlLogicSynthesis MultiBlockSynthesis OptimizationsforVideo OptimizationsforWireless BlockLevelSynthesis
2010
RTL
ComplexBus
BusInterfaceController
Processing Unit
Processing Unit
Processing Unit
ControlLogic
Power
2004
14
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Catapult ESL Synthesis Ecosystem
Spread Knowledge Facilitate Adoption Certify Flows Guarantee Success
15
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The High-Level Synthesis Blue Book

Comprehensive guide for designing hardware using C++ Targeted to RTL and systems designers moving to HLS Step-by-step approach from the basics of HLS to advanced case studies Detailed examples with source code and hardware diagrams
www.hlsbluebook.com
16
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Catapult C in TSMC Reference Flow 11

Validation of Catapult C flow by worlds #1 foundry TSMC-qualified 40nm and 65nm low-power process synthesis libraries for Catapult C Integration of TSMCs Memory Compiler in Catapult
TSMC HLS Requirement (Catapult) Language support (C++ or SystemC) Micro-architecture exploration TSMC Memory compiler integration Low-power AXI bus interface 65nm & 40nm library characterization
Completed for RF 11
17
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Complete Mentor ESL Demo Kit for RF 11
High-Level Synthesis Catapult C
ESL Design Vista
ESL Verification OVM Catapult + Vista + Questa OVM
ESL Synthesis : Architecture exploration, C++/SystemC ESL Design: System-level TLM modeling, power, debugging ESL Verification: Model and stimulus reuse from C++/TLM/RTL Standards-based: ANSI C++, OSCI TLM 2.0, SystemC, OVM
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Catapult C Adoption
NokiaSiemensNetworks Fraunhofer Fujitsu Qualcomm STMicroelectronics Ericsson Toshiba Thales Panasonic TexasInstruments KonicaMinolta STEricsson AlcatelLucent
Morethan100companiesworldwide ThousandsofASICtapeouts
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Leading the HLS Market and growing!
Mentor 42% Others 15%
+35%
Forte 25% Bluespec 18%
Mentor 51%
Forte 20% Bluespec 15%
Others 14%
ESL Synthesis Market 2007 (*)
ESL Synthesis Market 2008 (*)
MentorsrecentintroductionofSystemCsupporthas givenitacontrollingleadinESLSynthesis
GarySmith,March2010
Source: Gary Smith EDA, December 2009
20
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Catapult C Synthesis
Full-Chip HLS Solution
High-level synthesis for any design, for every designer
ANSI C/C++ and SystemC Algorithms, control-logic and interconnects Superior quality-of-results
CatapultCSynthesis
control algorithms
Immediate and Measurable Benefits

Fastest path to verified RTL More gates per engineer Positive ROI from 1st design
Tested, proven and adopted worldwide

#1 market share for past 3 years Hundreds of users and tape-outs
lowpower
21
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Thank you
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www.mentor.com/catapult
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Catapult C Synthesis

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Catapult C Synthesis:

A Game Changer for Full-Chip High-level Synthesis

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Designing in the Digital Era

Systems have evolved, design methodologies havent

2010 Mentor Graphics Corp. Company Confidential

The RTL Design and Verification Bottleneck

Where most bugs are being introduced

RTL not guaranteed to meet requirements

Due to a broken design methodology

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

The Catapult C Synthesis Opportunity

Bridges the gap between specification and implementation

Dramatically shortens the design cycle

Differentiated and verified designs in silicon, 20x faster!

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Traditional Flow vs. Catapult C Approach

RTL Coding and Optimization

RTLSynthesis RTL Debug

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Requirements for Full-Chip HLS

Arbitrated Bus Interface

Local Cache Video Decoder Demux Memory Controller

Full control over the architecture

Advanced algorithmic optimizations

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Specialized control-logic optimizations for superior QoR

Control-logic synthesis without area or timing compromise

20% 10% 0% w/oOpti mi za ti ons

wi thOpti mi za ti areawithons optimizations

2010 Mentor Graphics Corp. Company Confidential

D DIN EN CLK CLK

Synthesizes power management infrastructure

Avoids tedious and low-level manual transformations

2010 Mentor Graphics Corp. Company Confidential

Hierarchical and Interconnect Synthesis

Automatically creates interconnect and control logic

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Complex Bus Interfaces / Cycle-Accurate

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Complex Bus Interfaces / TLM2.0

SC_MODULE(top) { public: sc_in<bool> sc_in<bool> tlm_bus_master SC_CTOR(master) { SC_THREAD(proc); }

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

Taking HLS to the Next Level

ComplexBusInterfaces LowPowerOptimization ControlLogicSynthesis MultiBlockSynthesis OptimizationsforVideo OptimizationsforWireless BlockLevelSynthesis

A Game Changer for Full-Chip High-level Synthesis

Catapult ESL Synthesis Ecosystem

Spread Knowledge Facilitate Adoption Certify Flows Guarantee Success

A Game Changer for Full-Chip High-level Synthesis

2010 Mentor Graphics Corp. Company Confidential

The High-Level Synthesis Blue Book

A Game Changer for Full-Chip High-level Synthesis

Catapult C in TSMC Reference Flow 11

A Game Changer for Full-Chip High-level Synthesis