ANNA UNIVERSITY PREVIOUS YEAR QUESTION PAPER B.E/B.Tech Degree Examination,November/December 2009.

Seventh Semester Electronics and Communication Engineering EC 1401-VLSI DESIGN (Common to B.E.(Part-Time) Sixth Semester Regulation 2005) (Regulation 2004)

Part A-(10*2=20 marks) 1.What are the different MOS layers? 2.What are the two types of layout design rules? 3.Define rise time and fall time. 4.What is a pull down device? 5.What are the difference between task and function? 6.What is the difference between === and == ? 7.What is CBIC ? 8.Draw an assert high switch condition if input = 0 and input =1. 9.What do you mean by DFT? 10.Draw the boundary scan input logic diagram.

Part B - (5*16=80 marks)

11.a) Discuss the steps involved in IC fabrication process.(16) Or b) Describe n-well process in detail.(16)

12.a)i)Explain the DC characteristics of CMOS inverter with neat sketch.(8) ii)Explain channel length modulation and body effect.(8) Or b)i)Explain the different regions of operation in a MOS transistor.(10) ii)Write a note on MOS models.(6)

13.a)Explain in detail any five operators used in HDL .(16) Or b)i)Write the verilog code for 4 bit ripple carry full adder.(10) ii)Give the structural description for priority encoder using verilog.(6)

14.a)Explain in detail the sequence of steps to design an ASIC.(16)

Or b)Describe in detail the chip with programmable logic structures.(16)

15.a)Explain in detail Scan Based Test Techniques.(16) Or b)Discuss the three main design strategies for testability.(16 click here to read more: http://aimforhigh.blogspot.com/2011/02/ec-1401-vlsi-design-annauniversity.html#ixzz1j267az9z more question bank and prevoius year question paper

www.annauniv.edu/ BE ECE 6TH SEMESTER QUESTION BANK VLSI DESIGN

QUESTION BANK

SUBJECT CODE : EC 2354 SUBJECT NAME : VLSI DESIGN

PART - A ( 2 marks) 1. What are the different MOS layers? 2. What are the two types of layout design rules? 3. Define rise time and fall time. 4. What is a pull down device? 5. What is mean by Epitaxy ?

6. What is isolation? 7. What are the steps involved in manufacturing of IC? 8. What is the special feature of Twin-Tub process? 9. Draw the Isotropic etching process diagram. 10. What is silicide? 11. What is AOI? 12. Define fabrication process. 13. Draw the graph of n-MOS depletion mode. 14. Draw the Dc transfer characteristics curve. 11. Define noise margin. 15. Draw the symbol for tristate inverter. 16. Differentiate the nMOS from pMOS. 17. What are all the factors can be extracted from the Vth equation. 18. Define the Power dissipation 19. Define bit and byte. 20 Define FSM. 21 What do you mean by Data flow model? 22. Define Mealy network. 23. What is component in VHDL? 24 Which MOS can pass logic 1 and logic 0 strongly? 25 What is AOI logic function.

26 What are the methods for programming the PALs? 27 What are all the types of programming PALs? 28 Define PLD. 29 Draw the basic PLA. 30 Differentiate the PLA from the PAL. 31. Define test bench. 32. What is FPGA? 33. What is super buffer? 34. What is meant by Steering logic? 35. Give the advantages and disadvantages of SOI.

PART-B (16&8 Marks)

1. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well CMOS process to fabricate the n-switches. 2. Discuss the steps involved in IC fabrication process. 3. Describe n-well process in detail. 4. Explain the DC characteristics of CMOS inverter with neat sketch. 5. Explain channel length modulation and body effect. 6. Explain the different regions of operation in a MOS transistor. 7. Write a note on MOS models.

8. Explain in detail any five operators used in VHDL. 9. Write the VHDL code for 4 bit ripple carry full adder. 10. Give the structural description for priority encoder using VHDL. 11 List out the layout design rule. And draw the physical layout for one basic gate and two universal gates. 12 Explain the n MOS and p MOS enhancement transistor with its physical structure. 13. Derive and explain the (I) Threshold voltage equation, (II) MOS DC equation. 14. Explain the complimentary CMOS inverter DC characteristics. 15. Write short notes on (I) Noise Margin, (II) Rise Time, (III) Fall Time. 16. Develop the project using VHDL to realize the function of a ripple carry adder and draw its RTL. 17. Design a full adder by cascading two half adders and develop a project to realize it in model simulator 6.0. 18 Briefly explain the following terms (i) Design of switches with MOSFETs, (ii) Transmission gate, (iii) Muxs using TG. 19. Draw the physical layout for the following Boolean expression

a. y = (a +b) + c + de b. x = (lmnop) + q (r s + rs ) 20. Differenced the PALs from PLAs. And explain the 22V10 standard logic structure with the architecture. 21. Explain the methods used to programme the PALs with neat diagram. 22. Explain the Field programmable gate array with the architecture and logic blocks. 23. Draw and explain the typical architecture of PAL. 24. Explain test bench with an example and ways of generating waveforms. 25. Write a VHDL description to design Flip Flops( RS, JK, D, T) and write its test bench. 26. Write a VHDL description to design 8:1 MUX using two 4:1 MUX. 27. Write a VHDL description to design 8:1 MUX and DEMUX. 28. Write a VHDL description to design a undown counter and write its test bench. 29. Explain type,Operators, timing controls, Procedural assignments. 30 Draw and explain with diagrams tally circuits. 31. Draw and explain barrel shifters. 32. Explain with neat diagrams dynamic CMOS clocking. 33. Derive an expression for pull up and pull down ratio for transistors. 34. Describe in detail the chip with programmable logic structures. 35. Explain packages in vhdl with example. 36. With neat diagram explain finite state machine PLA. 37. Expain structured design of combinational circuits- EXOR Structure, Multiplex Structure.

39. Discuss the steps involved in fabrication of BICMOS technology.

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B.E/B.Tech Eighth (Regulation Electrical EC Time: 3 Answer PART 1. 2. 3. Compare

DEGREE

EXAMINATION

and 1461 hours A (10 enhancement what Define -ALL x and is a

2008 Semester 2004) Electronics Engineering VLSI DESIGN Maximum marks: 100 questions 2 =20 marks) modes problem super of operation. latch-up? buffer.

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depletion

4. Write down the pull-up to pull down ratio required for an nMOS inverter driven through one or more pass transistors. 5. 6. 7. 8. 9. 10. PART Write What are B the What are the are differences the between static and of PLA and of relational x a operators 16 full available = in dynamic memory cells? circuits? PAL. FPGA. adder. VHDL? 80)

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applications between PLD entity and

Tally and

Distinguish Compare the logical (5

11 (a) (i) Explain with neat diagrams the n-well process of CMOS fabrication. (10) (ii) Outline the major steps involved in nMOS fabrication. (6) (or)

(b) (i) Derive equations for the drain to source current of an nMOS transister in the nonsaturated and saturated regions of operation. (12) (ii) Draw and discuss the MOS transistor models. (4)

12. (a) (i) Derive the pull up to pull down ratio required for an nMOS inverter driven by another nMOS inverter. (8) (ii) Draw and explain with necessary layouts the different types of contacts cuts. (8) (or) (b) (i) Draw and explain the stick and layout diagrams of a two input nMOS NAND gate. (8) (ii) Give a brief account of BiCMOS and steering logic. (8)

13 (a) (i) Discuss the structured design approach stick diagrams for both nMOS (ii) Write a brief note (or) (b) (i) Draw and explain with necessary stick multiplexer.(8) (ii) Discuss the operation of a

for a parity generator. Draw and explain the and CMOS implimentations. (8) on dynamic technology. (8) diagram the design of a four way nMOS

barrel

shifter.

(8)

14. (a) (i) Draw an NMOS based PLA arrangement and illustrate how it can be used to implement multiple output functions of n variables in SOP form. (8) (ii) Explain the EPROM and EEPROM technology with necessary diagrams. (8) (or) (b) Explain the salient features of a field programmable gate array? Clearly bring out the architectural aspects, interconnect, logic and I/O details with suitable diagrams. (16) 15. (a) (i) Explain the syntax details of a VHDL subprogram. Write a VHDL subprogram to perform binary integer conversion. (8) (ii) Explain the application of packages in VHDL with a suitable example. (8) (or) (b) (i) Write a VHDL description of a test bench for a D flip flop. (8) (ii) Explain the modeling of a sequential circuit using VHDL. (8)