Sathish PG Project Report - Controller Area Network (CAN)

IMPLEMENTATION OF CAN FOR AUTOMOBILE APPLICATION
INTRODUCTION
Dept Of Electronics 1 SNR SONS College

INTRODUCTION
The CAN protocol is rapidly being adopted as the standard

communication platform in automobile and industrial network. CAN network
provide robust, reliable communication protocol with a speed up to 1 Mbps. CAN
usually consist of two wires arranged as a differential Pair. The data is impressed
on the CAN bus by making the voltage between these two wires different: either 2
volt or zero volts.
The main objective of the project, which is entitled as

“IMPLEMENTATION OF CAN FOR AUTOMOBILE APPLICATION”, is to
transmit the data without error, and to display it. The data, which is marked on the
CAN bus is received by the CAN controller via a CAN transceiver and the instant
data is displayed for further analysis of the CAN module.

ABOUT THE PROJECT

SYNOPSIS
The principal focus of our project falls on CAN (Controller Area Network). CAN
is one of the elevating serial communication protocol which efficiently supports
distributed real time control with a very level of security.
The project entitled “IMPLEMENTATION OF CAN FOR AUTOMOBILE

APPLICATION” is designed for the company PRICOL. The IMPLEMENTATION OF
CAN FOR AUTOMOBILE APPLICATION is an electronic system, takes advantage in
transfer various parameters without error which is impressed on the CAN bus, and in
addition the diagnosed data are displayed on the nodes.
For the efficient operation of this system, it requires CAN controller and CAN
transceiver. The software language like ‘C’ plays a splendid role in the proposed to ensure
the better possibility to provide a quality output with good accuracy.

ABOUT THE PROJECT
2.1 EXISTING SYSTEM
CAN (Controller area network), the leading network in power train, body
electronic applications, industrial applications, and even in medical applications. The
data, which is impressed on the CAN bus, is made to run between the CAN modules. But
there is no guarantee to give an assurance whether t data is transmitted continuously
across the CAN bus without error or not.
2.2 PROPOSED SYSTEM
proposed system is mainly designed transmit the data continuously without error
and to display it on the nodes. The identifier of the module, the frame type and the data
are displayed on the system. These tool makers the engineers to reliable about the data
transfer, which are displayed on the nodes.

1 INTRODUCTION
The Controller Area Network (CAN) is a serial communications protocol which
efficiently supports distributed realtime control with a very high level of security.
Its domain of application ranges from high speed networks to low cost multiplex wiring.
In automotive electronics, engine control units, sensors, anti-skid-systems, etc. are
connected using CAN with bitrates up to 1 Mbit/s. At the same time it is cost effective to
build into vehicle body electronics, e.g. lamp clusters, electric windows etc. to replace the
wiring harness otherwise required.
The intention of this specification is to achieve compatibility between any two
CAN implementations. Compatibility, however, has different aspects regarding e.g.
electrical features and the interpretation of data to be transferred. To achieve design
transparency and implementation flexibility CAN has been subdivided into different
layers.
• the (CAN-) object layer

• the (CAN-) transfer layer
• the physical layer
The object layer and the transfer layer comprise all services and functions of the data link
layer defined by the ISO/OSI model. The scope of the object layer includes
• finding which messages are to be transmitted
• deciding which messages received by the transfer layer are actually to be used,
• providing an interface to the application layer related hardware.
There is much freedom in defining object handling. The scope of the transfer layer
mainly is the transfer protocol, i.e. controlling the framing, performing arbitration, error
checking, error signalling and fault confinement. Within the transfer layer it is decided
whether the bus is free for starting a new transmission or whether a reception is just
starting. Also some general features of the bit timing are regarded as part of the transfer
layer. It is in the nature of the transfer layer that there is no freedom for modifications.
The scope of the physical layer is the actual transfer of the bits between the different
nodes with respect to all electrical properties. Within one network the physical layer,
ofcourse, has to be the same for all nodes. There may be, however, much freedom in
selecting a physical layer.
The scope of this specification is to define the transfer layer and the consequences of the
CAN protocol on the surrounding layers.

2 CAN OVERVIEW
CAN has the following properties
• prioritization of messages
• guarantee of latency times
• configuration flexibility
• multicast reception with time synchronization
• system wide data consistency
• multimaster
• error detection and signalling
• automatic retransmission of corrupted messages as soon as the bus is idle again
• distinction between temporary errors and permanent failures of nodes and
autonomous switching off of defect nodes
Application Layer
Object Layer
- Message Filtering
- Message and Status Handling
Transfer Layer
- Fault Confinement
- Error Detection and Signalling
- Message Validation
- Acknowledgment
- Arbitration
- Message Framing
- Transfer Rate and Timing
Physical Layer
- Signal Level and Bit Representation
- Transmission Medium

• The Physical Layer defines how signals are actually transmitted. Within this
specification the physical layer is not defined so as to allow transmission medium
and signal level implementations to be optimized for their application.
• The Transfer Layer represents the kernel of the CAN protocol. It presents
messages received to the object layer and accepts messages to be transmitted
from the object layer. The transfer layer is responsible for bit timing and
synchronization, message framing, arbitration, acknowledgment, error detection and
signalling, and fault confinement.
• The Object Layer is concerned with message filtering as well as status and
message handling.
The scope of this specification is to define the transfer layer and the consequences of the
CAN protocol on the surrounding layers.
HOW CAN WORKS

Messages
Information on the bus is sent in fixed format messages of different but limited length
When the bus is free any connected unit may start
to transmit a new message.
Information Routing
In CAN systems a CAN node does not make use of any information about the system
configuration (e.g. station addresses). This has several important consequences.
System Flexibility:
Nodes can be added to the CAN network without requiring
any change in the software or hardware of any node and application layer.
Message Routing:
The content of a message is named by an IDENTIFIER. The
IDENTIFIER does not indicate the destination of the message, but describes the
meaning of the data, so that all nodes in the network are able to decide by
MESSAGE FILTERING whether the data is to be acted upon by them or not.
Multicast:
As a consequence of the concept of MESSAGE FILTERING any
number of nodes can receive and simultaneously act upon the same message.
Data Consistency: Within a CAN network it is guaranteed that a message is
simultaneously accepted either by all nodes or by no node. Thus data
consistency of a system is achieved by the concepts of multicast and by error
handling.

Bit rate
The speed of CAN may be different in different systems. However, in a given system the
bitrate is uniform and fixed.
Priorities
The IDENTIFIER defines a static message priority during bus access.
Remote Data Request
By sending a REMOTE FRAME a node requiring data may request another node to send
the corresponding DATA FRAME. The DATA FRAME and the corresponding REMOTE
FRAME are named by the same IDENTIFIER.
Multimaster
When the bus is free any unit may start to transmit a message. The unit with the
message of higher priority to be transmitted gains bus access.
Arbitration
Whenever the bus is free, any unit may start to transmit a message. If 2 or more units start
transmitting messages at the same time, the bus access conflict is resolved by bitwise
arbitration using the IDENTIFIER. The mechanism of arbitration guarantees that neither
information nor time is lost. If a DATA FRAME and a REMOTE FRAME with the same
IDENTIFIER are initiated at the same time, the DATA FRAME prevails over the
REMOTE FRAME. During arbitration every transmitter compares the level of the bit
transmitted with the level that is monitored on the bus. If these levels are equal the unit
may continue to send. When a ’recessive’ level is sent and a ’dominant’ level is
monitored (see Bus Values), the unit has lost arbitration and must withdraw without
sending one more bit.
Safety
In order to achieve the utmost safety of data transfer, powerful measures for error
detection, signalling and self-checking are implemented in every CAN node.
Error Detection
For detecting errors the following measures have been taken:
- Monitoring (transmitters compare the bit levels to be transmitted with the bit
levels detected on the bus)
- Cyclic Redundancy Check
- Bit Stuffing
- Message Frame Check

Performance of Error Detection

The error detection mechanisms have the following properties:
- all global errors are detected.
- all local errors at transmitters are detected.
- up to 5 randomly distributed errors in a message are detected.
- burst errors of length less than 15 in a message are detected.
- errors of any odd number in a message are detected.
Total residual error probability for undetected corrupted messages: less than
message error rate * 4.7 * 10-11.
Error Signalling and Recovery Time
Corrupted messages are flagged by any node detecting an error. Such messages are
aborted and will be retransmitted automatically. The recovery time from detecting an
error until the start of the next message is at most 29 bit times, if there is no further error.
Fault Confinement
CAN nodes are able to distinguish short disturbances from permanent failures.
Defective nodes are switched off.
Connections
The CAN serial communication link is a bus to which a number of units may be
connected. This number has no theoretical limit. Practically the total number of units will
be limited by delay times and/or electrical loads on the bus line.
Single Channel
The bus consists of a single channel that carries bits. From this data resynchronization
information can be derived. The way in which this channel is implemented is not fixed in
this specification. E.g. single wire (plus ground), two differential wires, optical fibers, etc.
Bus values
The bus can have one of two complementary logical values: ’dominant’ or ’recessive’.
During simultaneous transmission of ’dominant’ and ’recessive’ bits, the resulting bus
value will be ’dominant’. For example, in case of a wired-AND implementation of the
bus, the ’dominant’ level would be represented by a logical ’0’ and the ’recessive’ level
by a logical ’1’. Physical states (e.g. electrical voltage, light) that represent the logical
levels are not given in this specification.

Acknowledgment
All receivers check the consistency of the message being received and will
acknowledge a consistent message and flag an inconsistent message.
Sleep Mode / Wake-up
To reduce the system’s power consumption, a CAN-device may be set into sleep mode
without any internal activity and with disconnected bus drivers. The sleep mode is
finished with a wake-up by any bus activity or by internal conditions of the system.
Onwake-up, the internal activity is restarted, although the transfer layer will be waiting
for the system’s oscillator to stabilize and it will then wait until it has synchronized itself
to the bus activity (by checking for eleven consecutive ’recessive’ bits), before the bus
drivers are set to "on-bus" again. In order to wake up other nodes of the system, which
are in sleep-mode, a special
wake-up message with the dedicated, lowest possible
IDENTIFIER (rrr rrrd rrrr; r = ’recessive’ d = ’dominant’) may be used.

MESSAGE TRANSFER
3.1 Frame Types
Message transfer is manifested and controlled by four different frame types:
A DATA FRAME carries data from a transmitter to the receivers.

A REMOTE FRAME is transmitted by a bus unit to request the transmission of the
DATA FRAME with the same IDENTIFIER.
An ERROR FRAME is transmitted by any unit on detecting a bus error.
An OVERLOAD FRAME is used to provide for an extra delay between the preceding
and the succeeding DATA or REMOTE FRAMEs.
DATA FRAMEs and REMOTE FRAMEs are separated from preceding frames by an
INTERFRAME SPACE.
3.1.1 DATA FRAME
A DATA FRAME is composed of seven different bit fields:
START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, DATA FIELD, CRC
FIELD, ACK FIELD, END OF FRAME. The DATA FIELD can be of length zero.

START OF FRAME
Marks the beginning of DATA FRAMES and REMOTE FRAMEs. It consists of a single
’dominant’ bit.
A station is only allowed to start transmission when the bus is idle (see BUS IDLE). All
stations have to synchronize to the leading edge caused by START OF FRAME (see
’HARD SYNCHRONIZATION’) of the station starting transmission first.
ARBITRATION FIELD
The ARBITRATION FIELD consists of the IDENTIFIER and the RTR-BIT.
IDENTIFIER
The IDENTIFIER’s length is 11 bits. These bits are transmitted in the order from ID-10
to ID-0. The least significant bit is ID-0. The 7 most significant bits (ID-10 - ID-4) must
not be all ’recessive’.
RTR BIT
Remote Transmission Request BIT In DATA FRAMEs the RTR BIT has to be
’dominant’. Within a REMOTE FRAME the RTR BIT has to be ’recessive’.
CONTROL FIELD
The CONTROL FIELD consists of six bits. It includes the DATA LENGTH CODE and
two bits reserved for future expansion. The reserved bits have to be sent ’dominant’.
Receivers accept ’dominant’ and ’recessive’ bits in all combinations.
DATA LENGTH CODE
The number of bytes in the DATA FIELD is indicated by the DATA LENGTH CODE.
This DATA LENGTH CODE is 4 bits wide and is transmitted within the CONTROL
FIELD.
DATA FIELD
The DATA FIELD consists of the data to be transferred within a DATA FRAME. It can
contain from 0 to 8 bytes, which each contain 8 bits which are transferred MSB first.
CRC FIELD
Contains the CRC SEQUENCE followed by a CRC DELIMITER.
CRC DELIMITER
The CRC SEQUENCE is followed by the CRC DELIMITER which consists of a single
’recessive’ bit.
ACK FIELD

The ACK FIELD is two bits long and contains the ACK SLOT and the ACK
DELIMITER. In the ACK FIELD the transmitting station sends two ’recessive’ bits. A
RECEIVER which has received a valid message correctly, reports this to the
TRANSMITTER by sending a ’dominant’ bit during the ACK SLOT (it sends ’ACK’).
ACK
ACK SLOT
All stations having received the matching CRC SEQUENCE report this within the ACK
SLOT by superscribing the ’recessive’ bit of the TRANSMITTER by a ’dominant’ bit.
ACK DELIMITER
The ACK DELIMITER is the second bit of the ACK FIELD and has to be a ’recessive’
bit. As a consequence, the ACK SLOT is surrounded by two ’recessive’ bits (CRC
DELIMITER, ACK DELIMITER).
END OF FRAME
Each DATA FRAME and REMOTE FRAME is delimited by a flag sequence
A Standard CAN (Version 2.0A)

Message Frame consists of seven different bit fields:
A Start of Frame (SOF) field - which indicates the beginning of a message frame.
An Arbitration field, containing a message identifier and the Remote Transmission
Request (RTR) bit. The RTR bit is used to discriminate between a transmitted Data Frame
and a request for data from a remote node.
Fig 3.CAN 2.0A Message Frame
A Control Field containing six bits:

* two reserved bits (r0 and r1) and
* a four bit Data Length Code (DLC). The DLC indicates the number of bytes in the Data
Field that follows
A Data Field, containing from zero to eight bytes.

The CRC field, containing a fifteen bit cyclic redundancy check code and a recessive
delimiter bit
The ACKnowledge field, consisting of two bits. The first is the Slot bit which is
transmitted as recessive, but is subsequently over written by dominant bits transmitted
from any node that successfully receives the transmitted message. The second bit is a
recessive delimiter bit
The End of Frame field, consisting of seven recessive bits.
Following the End Of Frame is the INTermission field consisting of three recessive bits.
After the three bit INTermission period the bus is recognised to be free. Bus Idle time
maybe of any arbitrary length including zero.
consisting of seven ’recessive’ bits.
2.0B Format
The CAN 2.0B format provides a twenty nine (29) bit identifier as opposed to the 11 bit
identifier in 2.0A.
Version 2.0B evolved to provide compatibility with other serial communications

protocols used in automotive applications in the USA. To cater for this, and still provide
compatibility with the 2.0A format, the Message Frame in Version 2.0B has an extended
format.
The differences are:
- In Version 2.0B the Arbitration field contains two identifier bit fields. The first (the base
ID) is eleven (11) bits long for compatibility with Version 2.0A. The second field (the ID
extension) is eighteen (18) bits long, to give a total length of twenty nine (29) bits.

- The distinction between the two formats is made using an Identifier Extension (IDE)
bit.
- A Substitute Remote Request (SRR) bit is also included in the Arbitration Field. The
SRR bit is always transmitted as a recessive bit to ensure that, in the case of arbitration
between a Standard Data Frame and an Extended Data Frame, the Standard Data Frame
will always have priority if both messages have the same base (11 bit) identifier.
All other fields in a 2.0B Message Frame are identical to those in the Standard format.
3.1.2 REMOTE FRAME

A station acting as a RECEIVER for certain data can initiate the transmission of the
respective data by its source node by sending a REMOTE FRAME.
A REMOTE FRAME is composed of six different bit fields:
START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, CRC FIELD,

ACKFIELD, END OF FRAME.
Contrary to DATA FRAMEs, the RTR bit of REMOTE FRAMEs is ’recessive’. There is
no DATA FIELD, independent of the values of the DATA LENGTH CODE which may
be signed any value within the admissible range 0...8. The value is the DATA LENGTH
CODE of the corresponding DATA FRAME.
The polarity of the RTR bit indicates whether a transmitted frame is a DATA FRAME
(RTR bit ’dominant’) or a REMOTE FRAME (RTR bit ’recessive’).
ERROR FRAME
The ERROR FRAME consists of two different fields. The first field is given by
the superposition of ERROR FLAGs contributed from different stations. The following
second field is the ERROR DELIMITER.
In order to terminate an ERROR FRAME correctly, an ’error passive’ node may need the
bus to be ’bus idle’ for at least 3 bit times (if there is a local error at an ’error passive’
receiver). Therefore the bus should not be loaded to 100%.

ERROR FLAG
There are 2 forms of an ERROR FLAG: an ACTIVE ERROR FLAG and a PASSIVE
ERROR FLAG.
1. The ACTIVE ERROR FLAG consists of six consecutive ’dominant’ bits.
2. The PASSIVE ERROR FLAG consists of six consecutive ’recessive’ bits unless it is
overwritten by ’dominant’ bits from other nodes.
An ’ ’error active’ station detecting an error condition signals this by transmission

of an ACTIVE ERROR FLAG. The ERROR FLAG’s form violates the law of bit stuffing
(see CODING) applied to all fields from START OF FRAME to CRC DELIMITER or
destroys the fixed form ACK FIELD or END OF FRAME field. As a consequence, all
other stations detect an error condition and on their part start transmission of an ERROR
FLAG. So the sequence of ’dominant’ bits which actually can be monitored on the bus
results from a superposition of different ERROR FLAGs transmitted by individual
stations. The total length of this sequence varies between a minimum of six and a
maximum of twelve bits.
An ’error passive’ station detecting an error condition tries to signal this by transmission
of a PASSIVE ERROR FLAG. The ’error passive’ station waits for six consecutive bits
of equal polarity, beginning at the start of the PASSIVE ERROR FLAG.
The PASSIVE ERROR FLAG is complete when these 6 equal bits have been detected.
ERROR DELIMITER
The ERROR DELIMITER consists of eight ’recessive’ bits. After transmission of an

ERROR FLAG each station sends ’recessive’ bits and monitors the bus until it detects a
’recessive’ bit. Afterwards it starts transmitting seven more ’recessive’ bits.

3.1.4 OVERLOAD FRAME
The OVERLOAD FRAME contains the two bit fields OVERLOAD FLAG and
OVERLOAD DELIMITER.
There are two kinds of OVERLOAD conditions, which both lead to the transmission of
an OVERLOAD FLAG:
1. The internal conditions of a receiver, which requires a delay of the next DATA
FRAME or REMOTE FRAME.
2. Detection of a ’dominant’ bit during INTERMISSION.
The start of an OVERLOAD FRAME due to OVERLOAD condition 1 is only allowed to

be started at the first bit time of an expected INTERMISSION, whereas OVERLOAD
FRAMEs due to OVERLOAD condition 2 start one bit after detecting the ’dominant’ bit.
At most two OVERLOAD FRAMEs may be generated to delay the next DATA or
REMOTE FRAME.
OVERLOAD FLAG
consists of six ’dominant’ bits. The overall form corresponds to that of the ACTIVE
ERROR FLAG.
The OVERLOAD FLAG’s form destroys the fixed form of the INTERMISSION field.
As a consequence, all other stations also detect an OVERLOAD condition and on their
part start transmission of an OVERLOAD FLAG. (In case that there is a ’dominant’ bit
detected during the 3rd bit of INTERMISSION locally at some node, the other nodes will
not interpret the OVERLOAD FLAG correctly, but interpret the first of these six
’dominant’ bits as START OF FRAME. The sixth ’dominant’ bit violates the rule of bit
stuffing causing an error condition).

OVERLOAD DELIMITER
consists of eight ’recessive’ bits. The OVERLOAD DELIMITER is of the same form as
the ERROR DELIMITER. After transmission of an OVERLOAD FLAG the station
monitors the bus until it detects a transition from a ’dominant’ to a ’recessive’ bit. At this
point of time every bus station has finished sending its OVERLOAD FLAG and all
stations start transmission of seven more ’recessive’ bits in coincidence.
Bit time
As defined in ISO11898, the nominal time for each bit in a CAN message frame is made
up of four non-overlapping time segments as shown below.
Fig 1. Bit time segments
Sync-seg is the segment that is used to synchronise the nodes on the bus. A bit edge
(if there is a data change) is expected during this segment.
Prop-Seg is a period of time that is used to compensate for physical delay times
within the network.
Phase-seg1 is a buffer segment that may be lengthened during resynchronisation to
compensate for oscillator drift and positive phase differences between the oscillators of
the transmitting and receiving node(s).
Phase-seg2 is a buffer segment that may be shortened during resynchronisation
(described below) to compensate for negative phase errors and oscillator drift.
The Sample point is always at the end of Phase-seg1 and is the time at which the bus
level is read and interpreted as the value of the current bit.
Whether transmitting or receiving, all nodes on a single CAN bus must have the same
nominal bit time. Bit time is programmable at each node on a CAN Bus and is a function
of the period of the oscillator local to each node, the value that is user-programmed into a
Baud Rate Prescaler (BRP) register in the controller at each node, and the programmed
number of time quanta per bit.
One time quanta (Also known as the system clock period) is defined as the period of the
local oscillator, multiplied by the value in the BRP.

Each of the four time segments in one bit is one or more time quanta long. As stated in
the Bosch CAN2 spec:
Sync-seg is always one time quantum long

Prop-seg is programmable from one to eight (or, optionally, more) time quanta long
Phase-seg1 is programmable from one to eight (or, optionally, more) time quanta
long
Phase-seg2 is the maximum of Phase-seg1 and the Information Processing Time
where the Information Processing Time is less than or equal to 2 time quanta.
Synchronisation
When any node receives a data frame or a remote frame, it is necessary for the receiver to
synchronise with the transmitter.
Because there is no explicit clock signal that a CAN system can use as a timing reference,
two mechanisms are used to maintain synchronisation.
The first is hard synchronisation and occurs at Start-of-Frame (SOF).
To compensate for oscillator drift, and phase differences between transmitter and receiver
oscillators, additional synchronisation is needed.
So - for subsequent bits in any received frame, if a bit edge does not occur in the Sync-
seg segment of bit time, resynchronisation is automatically invoked and will shorten or
lengthen the current bit time depending on where the edge occurs. The maximum amount
by which the bit time is lengthened or shortened is determined by a user-programmable
number of time quanta known as the Synchronisation Jump Width (SJW).
Error Detection
CAN implements five error detection mechanisms; three at the message level and two at
the bit level.
At the message level:
Cyclic Redundancy Checks (CRC)

Frame Checks
Acknowledgment Error Checks

At the bit level:
Bit Monitoring
Bit Stuffing
Cyclic Redundancy Check
Every transmitted message contains a 15 bit Cyclic Redundancy Check (CRC) code. The
CRC is computed by the transmitter and is based on the message content. All receivers
that accept the message perform a similar calculation and flag any errors.
Frame Check
There are certain predefined bit values that must be transmitted at certain points within
any CAN Message Frame.
If a receiver detects an invalid bit in one of these positions a Form Error (also known as a
Format Error) will be flagged.
Acknowledgement (ACK) Error Check

If a transmitter determines that a message has not been ACKnowledged then an ACK
Error is flagged.
Bit Monitoring
Any transmitter automatically monitors and compares the actual bit level on the bus with
the level that it transmitted. If the two are not the same, a bit error is flagged.
Bit Stuffing
CAN uses a technique known as bit stuffing as a check on communication integrity.
After five consecutive identical bit levels have been transmitted, the transmitter will
automatically inject (stuff) a bit of the opposite polarity into the bit stream.
Receivers of the message will automatically delete (de-stuff) such bits before processing
the message in any way.
Because of the bit stuffing rule, if any receiving node detects six consecutive bits of the
same level, a stuff error is flagged.

Error Frame
If an error is detected by any node, using any and all of the five mechanisms described
above, the node that detects the error aborts the transmission by sending an Error Frame.
This prevents any other node from accepting the message and ensures consistency of data
throughout the network.
Error Confinement
Error confinement is a mechanism which is understood to be unique to CAN and
provides a method for discriminating between temporary errors and permanent failures.
Temporary errors may be caused by, spurious external conditions, voltage spikes, etc.
Permanent failures are likely to be caused by bad connections, faulty cables, defective
transmitters or receivers, or long lasting external disturbances.
The general principle only is described here. More detailed information is available in the
ISO standard, and in the data sheets from the device manufacturers.
Error Counts
When an error is flagged, error counts are added to one of two dedicated error count
registers within each CAN controller on each node.
It's more complex than stated here, but - in principal - receive errors are given a
weighting of 1 and are accumulated in a Receive Error Count register; transmit errors are
given a weighting of 8 and accumulated in a Transmit Error Count register.
If errors continue to occur, the error counts continue to increase. Any good messages
decrement the Error Count registers and, if no further errors are detected, both Error
Counts go back to zero.
The accumulated error counts determine the error status of a node.
Error Active Mode

Nodes usually operate in a state known as Error Active mode. In this condition a node is
fully functional and both the Error Count registers contain counts of less than 127.
Error Passive Mode

If the count in either Error Count register in a node exceeds 127, the node will go from
Error Active mode to a heightened state of "alert" known as Error Passive mode.
Error Passive nodes can still transmit and receive messages but are restricted in relation
to how they flag any errors that they may detect.

The ISO standard (and some of the device data sheets) explain the precise mechanisms in
more detail.
Bus Off Mode

If an error condition persists, such that the Transmit Error Count of a device exceeds 255,
the device will take itself off the bus by going to BusOff mode. This means that a
permanently faulty device will cease to be active on the bus until reconnected under user
control, but communications between the other nodes can continue unhindered.
Error Detection Capabilities

Error detection on CAN is extremely thorough.
Global errors which occur at all nodes are 100% detectable.
For local errors (i.e. errors which may appear at only some nodes) the CRC check alone
has the following error detection capabilities:
Up to 5 single bit errors are 100% detectable, even if the errors are distributed
randomly within the code word
All single bit errors are detected if their total number within the code word is odd
The residual (undetected) error probability of the CRC check alone is 3 x 10 to the power
-5.
In conjunction with all the other error checking mechanisms, a more realistic value is 10
to the power -11.

BLOCK DIAGRAM AND BLOCK DIAGRAM

DESCRIPTION
BLOCK DIAGRAM

3.2 BLOCK DIAGRAM DESCRIPTION
LIST OF THE PARTS
3.2.1 PIC18F4580

3.2.2 High speed can transceiver
3.2.3 Proximity sensor
3.2.4 Temperature sensor
3.3.5 LCD display
3.3.6 Power supply unit
5.2 BLOCK DIAGRAM DESCRIPTION
The various blocks of the circuit are explained briefly as follows:
POWER SUPPLY UNIT:

The circuit works with a regulated 5V power supply.
HIGH SPEED TRANSCEIVER:

IC TJA 1050 is used as a high-speed transceiver. It is used as the interface
between the CAN protocol controller and the physical bus.
E_CAN MODULE:
PCI 18F4580 device contains CAN module. With a aid of CAN module peer
stations are connected via a serial bus.
3.2.1 PIC MICROCONTROLLER
INTRODUCTION OF MICROCONTROLLER:

PIC is a family of RISC micro controllers made by micro chip technology, rived
from the PIC1650 originally developed by general instruments micro electronics
division. Micro chip technology does not use PIC as an acronym; in fact the brand name
is PIC micro. It is generally regarded that PIC stands for peripheral interface controller,
although general instruments original acronym for the PIC1650 was programmable
intelligent computer.
The original PIC was build to be used with GI’s new 16 bit CPU, the CP1600.
While generally a good CPU, the CP1600 had poor input and output performance, and
the 8 bit PIC was developed in 1975 to improve performance of the over all system by off
loading input out put takes from the CPU. The PIC used simple micro code stored in
ROM to perform it takes and although the term wasn’t used at the time, it is a RISC
design that runs one instruction per cycle (4 oscillator cycles).
In 1985 general instruments spun of there micro electronics division and the new
owner ship canceled almost everything which by this time was mostly out of the date.
The PIC, however, was upgraded with EPROM to produce a programmable channel
controller, and today a huge variety of the PIC are available with varies on board
peripherals (serial communication modules UART, motor control kernels, ect) and
program memory from 512 words to 32k words and more (a word is one assembly
language instruction, varying from 12, 14, or 16 bit depending on the specific PIC
controller family).
Microcontroller is a general purpose device, which integrates a number of the

components of a microprocessor system on to single chip. It has inbuilt CPU, memory
and peripherals to make it as a mini computer. A microcontroller combines on to the same
microchip:
• The CPU core

• Memory (both ROM and RAM)

• Some parallel digital I/O
Microcontrollers will combine other devices such as:
• A timer module to allow the microcontroller to perform tasks for certain time
periods.
• A serial i/o port to allow data to flow between the controller and other devices
such as a PIC or another microcontroller.
• An ADC to allow the microcontroller to accept analogue input data for
processing.
Microcontrollers are:
• Smaller in size
• Consumes less power
• Inexpensive
Micro controller is a stand alone unit, which can perform functions on its own
without any requirement for additional hardware like I/O ports and external memory. The
heart of the microcontroller is the CPU core. In the past, this has traditionally been based
on a 8-bit microprocessor unit. For example Motorola uses a basic 6800 microprocessor
core in their 6805/6808 microcontroller devices.
In the recent years, microcontrollers have been developed around specifically

designed CPU cores, for example the microchip PIC range of microcontrollers.

PIC START PLUS PROGRAMMER:
The PIC start plus development system from microchip technology provides the
product development engineer with a highly flexible low cost microcontroller design tool
set for all microchip PIC micro devices. The pic start plus development system includes
PIC start plus development programmer and mplab IDE.
The PIC start plus programmer gives the product developer ability to program
user software in to any of the supported microcontrollers. The PIC start plus software
running under mplab provides for full interactive control over the programmer.
SPECIAL FEATURES OF PIC MICROCONTROLLER:
CORE FEATURES:
 High-performance RISC CPU

 Only 35 single word instructions to learn
 All single cycle instructions except for program branches which are two cycle
 Operating speed: DC - 20 MHz clock input
 DC - 200 ns instruction cycle
 Up to 8K x 14 words of Flash Program Memory,
 Up to 368 x 8 bytes of Data Memory (RAM)

 Up to 256 x 8 bytes of EEPROM data memory

 Interrupt capability
 Eight level deep hardware stack
 Direct, indirect, and relative addressing modes
 Power-on Reset (POR)
 Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
 Watchdog Timer (WDT) with its own on-chip RC Oscillator for reliable operation
 Programmable code-protection
 Power saving SLEEP mode
 Selectable oscillator options
 Low-power, high-speed CMOS EPROM/EEPROM technology
 Fully static design
 In-Circuit Serial Programming (ICSP) via two pins
 Only single 5V source needed for programming capability
 In-Circuit Debugging via two pins
 Processor read/write access to program memory
 Wide operating voltage range: 2.5V to 5.5V

 High Sink/Source Current: 25 mA
 Commercial and Industrial temperature ranges
 Low-power consumption:
< 2mA typical @ 5V, 4 MHz
 20mA typical @ 3V, 32 kHz
< 1mA typical standby current

PERIPHERAL FEATURES:
 Timer0: 8-bit timer/counter with 8-bit prescaler

 Timer1: 16-bit timer/counter with prescaler, can be incremented during sleep
 via external crystal/clock
 Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
 Two Capture, Compare, PWM modules
 Capture is 16-bit, max resolution is 12.5 ns,
 Compare is 16-bit, max resolution is 200 ns,
 PWM max. resolution is 10-bit
 10-bit multi-channel Analog-to-Digital converter
 Synchronous Serial Port (SSP) with SPI. (Master Mode) and I2C. (Master/Slave)
 Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with
 9- Bit addresses detection.
 Brown-out detection circuitry for Brown-out Reset (BOR)
ECAN Module Features:

• Message bit rates up to 1 Mbps
• Conforms to CAN 2.0B ACTIVE Specification
• Fully backward compatible with PIC18XXX8 CAN

Modules
• Three modes of operation:
- Legacy, Enhanced Legacy, FIFO

• Three dedicated transmit buffers with prioritization
• Two dedicated receive buffers
• Six programmable receive/transmit buffers
• Three full 29-bit acceptance masks
• 16 full 29-bit acceptance filters w/ dynamic association
• DeviceNet™ data byte filter support
• Automatic remote frame handling
• Advanced error management features
FEATURES OF MICROCONTROLLER
 Includes power full microchip PIC16F877A micro controller with 8Kb internal
flash program memory
 Operating speed at 20 MHz

 Direct in _circuit programming for easy program updates
 Upto 28 in put / output points with easy to connect standard headers
 RS232 connection with MAX232
 Internal EPROM
 8 channel 10 bit A/D converter
 One 16 bit Timer with Two 8 bit timers
 Power and programming LED’S
 Reset button
 Ideal as an interchangeable controller for real time systems.
LCD DISPLAY
LCD’s also are used as numerical indicators, especially in digital watches
where their much smaller current needs than LED displays (microamperes compared with
mill amperes) prolong battery life. Liquid crystals are organic (carbon) compounds,
which exhibit both solid and liquid properties. A ‘cell’ with transparent metallic

conductors, called electrodes, on opposite daces, containing a liquid crystal, and on which
light falls, goes ‘dark’ when a voltage is applied across the electrodes. The effect is due to
molecular rearrangement within the liquid crystal.
The LCD display used in this project consists of 2 rows. Each row consists
of maximum 16 characters. So using this display only maximum of 32 characters can be
displayed.
INTRODUCTION:
Crystalonics dot –matrix (alphanumeric) liquid crystal displays are available in
TN, STN types, with or without backlight. The use of C-MOS LCD controller and driver
ICs result in low power consumption. These modules can be interfaced with a 4-bit or 8-
bit micro processor /Micro controller.
The built-in controller IC has the following features:
 Correspond to high speed MPU interface (2MHz)
 80 x 8 bit display RAM (80 Characters max)
 9,920 bit character generator ROM for a total of 240 character fonts. 208
character fonts (5 x 8 dots) 32 character fonts (5 x 10 dots)
 64 x 8 bit character generator RAM 8 character generator RAM 8 character fonts
(5 x 8 dots) 4 characters fonts (5 x 10 dots)
 Programmable duty cycles

1/8 – for one line of 5 x 8 dots with cursor
 Wide range of instruction functions display clear, cursor home, display on/off,
cursor on/off, display character blink, cursor shift, display shift.

 Automatic reset circuit, that initializes the controller / driver ICs after power on.
FUNCTIONAL DESCRIPTION OF THE CONTROLLER IC
REGISTERS:
The controller IC has two 8 bit registers, an instruction register (IR) and a data
register (DR). The IR stores the instruction codes and address information for display
data RAM (DD RAM) and character generator RAM (CG RAM). The IR can be written,
but not read by the MPU.
The DR temporally stores data to be written to /read from the DD RAM or CG
RAM. The data written to DR by the MPU, is automatically written to the DD RAM or
CG RAM as an internal operation.
When an address code is written to IR, the data is automatically transferred from
the DD RAM or CG RAM to the DR. data transfer between the MPU is then completed
when the MPU reads the DR. likewise, for the next MPU read of the DR, data in DD
RAM or CG RAM at the address is sent to the DR automatically. Similarly, for the MPU
write of the DR, the next DD RAM or CG RAM address is selected for the write
operation.
The register selection table is as shown below:
RS R/W Operation
0 0 IR write as an internal operation

0 1 Read busy flag (DB7) and address counter

(DB0 to DB6)
1 0 DR write as an internal operation (DR to DD

RAM or CG RAM)
1 1 DR read as an internal operation (DD RAM

or CG RAM to DR)
BUSY FLAG:
When the busy flag is1, the controller is in the internal operation mode, and the
next instruction will not be accepted.
When RS = 0 and R/W = 1, the busy flag is output to DB7.
The next instruction must be written after ensuring that the busy flag is 0.
ADDRESS COUNTER:
The address counter allocates the address for the DD RAM and CG RAM
read/write operation when the instruction code for DD RAM address or CG RAM
address setting, is input to IR, the address code is transferred from IR to the address
counter. After writing/reading the display data to/from the DD RAM or CG RAM, the
address counter increments/decrements by one the address, as an internal operation. The
data of the address counter is output to DB0 to DB6 while R/W = 1 and RS = 0.
DISPLAY DATA RAM (DD RAM)

The characters to be displayed are written into the display data RAM (DD RAM),
in the form of 8 bit character codes present in the character font table. The extended
capacity of the DD RAM is 80 x 8 bits i.e. 80 characters.

CHARATCER GENERATOR ROM (CG ROM)
The character generator ROM generates 5 x 8 dot 5 x 10 dot character patterns

from 8 bit character codes. It generates 208, 5 x 8 dot character patterns and 32, 5 x 10
dot character patterns.
CHARACTER GENERATOR RAM (CG RAM)
In the character generator RAM, the user can rewrite character patterns by
program. For 5 x 8 dots, eight character patterns can be written, and for 5 x 10 dots, four
character patterns can be written.
INTERFACING THE MICROPROCESSOR / CONTROLLER:

The module, interfaced to the system, can be treated as RAM input/output,
expanded or parallel I/O.
Since there is no conventional chip select signal, developing a strobe signal for the enable
signal (E) and applying appropriate signals to the register select (RS) and read/write
(R/W) signals are important.
The module is selected by gating a decoded module – address with the host – processor’s
read/write strobe. The resultant signal, applied to the LCDs enable (E) input, clocks in the
data.
The ‘E’ signal must be a positive going digital strobe, which is active while data and
control information are stable and true. The falling edge of the enable signal enables the
data / instruction register of the controller. All module timings are referenced to specific
edges of the ‘E’ signal. The ‘E’ signal is applied only when a specific module transaction
is desired.
The read and write strobes of the host, which provides the ‘E’ signals, should not be
linked to the module’s R/W line. An address bit which sets up earlier in the host’s
machine cycle can be used as R/W.

When the host processor is so fast that the strobes are too narrow to serve as the ‘E’ pulse
a. Prolong these pulses by using the hosts ‘Ready’ input
b. Prolong the host by adding wait states
c. Decrease the Hosts Crystal frequency.
Inspite of doing the above mentioned, if the problem continues, latch both the data and
control information and then activate the ‘E’ signal
When the controller is performing an internal operation he busy flag (BF) will set and
will not accept any instruction. The user should check the busy flag or should provide a
delay of approximately 2ms after each instruction.
The module presents no difficulties while interfacing slower MPUs.
The liquid crystal display module can be interfaced, either to 4-bit or 8-bit MPUs.
For 4-bit data interface, the bus lines DB4 to DB7 are used for data transfer, while DB0
to DB3 lines are disabled. The data transfer is complete when the 4-bit data has been
transferred twice.
The busy flag must be checked after the 4-bit data has been transferred twice. Two more
4-bit operations then transfer the busy flag and address counter data.
For 8-bit data interface, all eight-bus lines (DB0 to DB7) are used.
3.2.7 POWER SUPPLY SECTION
BLOCK DIAGRAM

The ac voltage, typically 220V rms, is connected to a transformer, which steps that ac
voltage down to the level of the desired dc output. A diode rectifier then provides a full-
wave rectified voltage that is initially filtered by a simple capacitor filter to produce a dc
voltage. This resulting dc voltage usually has some ripple or ac voltage variation.
A regulator circuit removes the ripples and also remains the same dc value even if
the input dc voltage varies, or the load connected to the output dc voltage changes. This
voltage regulation is usually obtained using one of the popular voltage regulator IC units.
Block diagram (Power supply)
TRANSFORMER
The potential transformer will step down the power supply voltage (0-230V) to
(0-6V) level. Then the secondary of the potential transformer will be connected to the
precision rectifier, which is constructed with the help of op–amp. The advantages of

using precision rectifier are it will give peak voltage output as DC, rest of the circuits will
give only RMS output.
BRIDGE RECTIFIER
When four diodes are connected as shown in figure, the circuit is called as bridge
rectifier. The input to the circuit is applied to the diagonally opposite corners of the
network, and the output is taken from the remaining two corners.
Let us assume that the transformer is working properly and there is a positive
potential, at point A and a negative potential at point B. the positive potential at point A
will forward bias D3 and reverse bias D4.
The negative potential at point B will forward bias D1 and reverse D2. At this
time D3 and D1 are forward biased and will allow current flow to pass through them; D4
and D2 are reverse biased and will block current flow.
The path for current flow is from point B through D1, up through RL, through
D3, through the secondary of the transformer back to point B. this path is indicated by the
solid arrows. Waveforms (1) and (2) can be observed across D1 and D3.
One-half cycle later the polarity across the secondary of the transformer reverse,
forward biasing D2 and D4 and reverse biasing D1 and D3. Current flow will now be
from point A through D4, up through RL, through D2, through the secondary of T1, and
back to point A. This path is indicated by the broken arrows. Waveforms (3) and (4) can
be observed across D2 and D4. The current flow through RL is always in the same
direction. In flowing through RL this current develops a voltage corresponding to that

shown waveform (5). Since current flows through the load (RL) during both half cycles
of the applied voltage, this bridge rectifier is a full-wave rectifier.
One advantage of a bridge rectifier over a conventional full-wave rectifier is that

with a given transformer the bridge rectifier produces a voltage output that is nearly twice
that of the conventional full-wave circuit.
This may be shown by assigning values to some of the components shown in

views A and B. assume that the same transformer is used in both circuits. The peak
voltage developed between points X and y is 1000 volts in both circuits. In the
conventional full-wave circuit shown—in view A, the peak voltage from the center tap to
either X or Y is 500 volts. Since only one diode can conduct at any instant, the maximum
voltage that can be rectified at any instant is 500 volts.
The maximum voltage that appears across the load resistor is nearly-but never
exceeds-500 v0lts, as result of the small voltage drop across the diode. In the bridge
rectifier shown in view B, the maximum voltage that can be rectified is the full secondary
voltage, which is 1000 volts. Therefore, the peak output voltage across the load resistor is
nearly 1000 volts. With both circuits using the same transformer, the bridge rectifier
circuit produces a higher output voltage than the conventional full-wave rectifier circuit.
IC VOLTAGE REGULATORS
Voltage regulators comprise a class of widely used ICs. Regulator IC units
contain the circuitry for reference source, comparator amplifier, control device, and
overload protection all in a single IC. IC units provide regulation of either a fixed positive

voltage, a fixed negative voltage, or an adjustably set voltage. The regulators can be
selected for operation with load currents from hundreds of milli amperes to tens of
amperes, corresponding to power ratings from milli watts to tens of watts.
CIRCUIT DIAGRAM (POWER SUPPLY)
A fixed three-terminal voltage regulator has an unregulated dc input voltage, Vi,

applied to one input terminal, a regulated dc output voltage, Vo, from a second terminal,
with the third terminal connected to ground.
The series 78 regulators provide fixed positive regulated voltages from 5 to 24
volts. Similarly, the series 79 regulators provide fixed negative regulated voltages from 5
to 24 volts.

• For ICs, microcontroller, LCD --------- 5 volts

• For alarm circuit, op-amp, relay circuits ---------- 12 volts
THREE-TERMINAL VOLTAGE REGULATORS:
Fig shows the basic connection of a three-terminal voltage regulator IC to a load.

The fixed voltage regulator has an unregulated dc input voltage, VI, applied to one input
terminal, a regulated output dc voltage, VO, from a second terminal, with the third
terminal connected to ground. For a selected regulator, IC device specifications list a
voltage range over which the input voltage can vary to maintain a regulated output
voltage over a range of load current. The specifications also list the amount of output
voltage change resulting from a change in load current (load regulation) or in input
voltage (line regulation).
Fixed Positive Voltage Regulators:
IN OUT
7805
From GND
Transformer
secondry
GND
The series 78 regulators provide fixed regulated voltages from 5 to 24 V. Figure

19.26 shows how one such IC, a 7812, is connected to provide voltage regulation with
output from this unit of +12V dc. An unregulated input voltage Vi is filtered by capacitor
C1 and connected to the IC’s IN terminal. The IC’s OUT terminal provides a regulated +
12V which is filtered by capacitor C2 (mostly for any high-frequency noise). The third IC

terminal is connected to ground (GND). While the input voltage may vary over some
permissible voltage range, and the output load may vary over some acceptable range, the
output voltage remains constant within specified voltage variation limits. These
limitations are spelled out in the manufacturer’s specification sheets. A table of positive
voltage regulated ICs is provided in table 19.1.
TABLE 19.1 Positive Voltage Regulators in 7800 series
IC Part Output Voltage (V) Minimum Vi (V)
7805 +5 7.3
7806 +6 8.3
7808 +8 10.5
7810 +10 12.5

7812 +12 14.6
7815 +15 17.7

7818 +18 21.0
7824 +24 27.1

PROGRAM DEVELOPMENT

FLOWCHART AND
WORKING
DESCRIPTION
TRANSMISSION OF CAN DATA

RECEPTION OF DATA

6.3 WORKING DESCRIPTION
The main objective of the project is to monitor and displayed the data flow in the
CAN bus.

The hardware configuration of the high-speed transceiver is designed in such a

way to block the operation of transmitter and to act like a receiver.
The control data, which is confined in the bus, is received by the high speed CAN
transceiver. This data is fed to the CANRX pin of the PIC 18F4580.
The nature of the data is analysed. The analysis is done to identify whether it is an
11 –bit identifier or 29-bit identifier and also to recognize whether it is data frame or a
remove frame.
After analysis, the data and the analyzed result are transmitted to the system
through TX pin of the 18F4580. Each node receive the appropriate data and calculate it
then it displayed on nodes.
ALGORITHM

Step 1: start the process
Step 2: initialize the ports and peripherals
Step 3: Enable CAN
Step 4: Enable the appropriate registers
Step 5: Measure the speed & transmit
Step 6: Measure the fuel & transmit
Step 6: Receives corresponding nodes
Step 7: go to step 3 for continuous process
Step 8: end the process
SOFTWARE AND HARDWARE

DEVELOPMENT

6. SOFTWARE AND HARDWARE DEVELOPMENT

6.1 MPLAB IDE:
MPLAB is a windows-based Integrated Development Environment (IDE) for the

Microchip Technology Incorporated PIC Microcontroller families. MPLAB allows
writing, debugging and optimizing the PIC micro applications for firmware product
designs. MPLAB includes a text editor, simulator and project manager. MPLAB also
supports the MPLAB-ICE and PICMASTER emulators, PICSTART Plus, PROMATE II
programmers and other Microchip or third party, development system tools.
The organization of MPLAB tools by function helps make pull-down menus and
customizable quick keys easy to find and use. MPLAB tools allow assembling, compiling
and linking source code, and Debug the time with the MPLAB-ICE emulator. By using
the simulator timing measurements can be made.
 View variables in Watch windows

 Find quick answers to questions from the MPLAB on-line help and much more.
MPLAB is an easy-to-learn and use Integrated Development Environment (IDE).

The IDE provides firmware development engineers the flexibility to develop and debug
firmware for Microchip’s PIC Micro Windows 95, 98, NT and 2000. Not all hardware
components that function under the MPLAB IDE (such as emulators and device
programmers) function under all operating systems.
MPLAB PROVIDES A FUNCTION THAT ALLOWS:

• Create and Edit Source Files

• Group Files into projects
• Debug Source Code
• Debug Executable logic using the simulator or emulator(s)
• The MPLAB IDE allows creating and editing source code by providing with a
full- featured text editor.
Further, source code can be debugged with the aid of a Build Results generating
executable files. A Project Manager allows to group source files, precompiled object files,
libraries and linker script files into a project format. The MPLAB IDE also provides
feature-rich simulator and emulator environments to debug the logic of executables.
Some of the features are:
• A Variety of windows allowing to view the contents of all dates and program
memory locations source code, program memory and absolute listing windows
allowing to view the source code and its assembly-level equivalent separately and
together (Absolute Listing)
• The ability to step through execution, or apply break, Trace, Standard or Complex
Trigger points
The MPLAB IDE integrates several tools to provide a complete development

environment.
MPLAB PROJECT MANAGER:

Project manager is used to create a project and work with the specific files related
to the Project. When using a project, source code is rebuilt and downloaded to the
simulator or emulator with a single mouse click.
MPLAB EDITOR:
MAPAB Editor is used to create and edit text files such as source files, code and
linker script files.
MPLAB-SIM SIMULATOR:
The software simulator models the instruction execution execution I/O of the PIC
Microcontrollers (MCUs).
MPLAB-ICE EMULATORS:
The MPLAB-ICE emulator uses hardware to emulate PIC microcontroller in real
time, either with or without a target system.
MPLAB-ICE DEBUGGER:
The MPLAB-ICD is a Programmer for the PIC 16f87X family as well as an
in-circuit debugger. It programs hex files into the PIC16f87X and offers basic debugging
features like real-time code execution, stepping and break pints. MPASM Universal
Assembler/MPLINK Relocatable Linker/MPLIB Librarian the MPASM assembler allows
source code to be assembled without leaving MPLAB. MPLINK crates the final
application by linking Relocatable modules from MPASM and MPLAB-c17/c18. MPLIB
manages custom libraries for maximum code reuse.
6.2 CROSS COMPILER

The main advantage of using cross compliers is to reduce the time needed to
develop the program. By using a cross complier, the assembly code needed to perform
the desired function can be figure out. Another important advantage is that the
higher-level code is (generally) more portable.
Besides a potential increases in code size, there are other issues to be aware of.
When program timing is critical, clock cycles needed for any part of the program in the
assembly code should be know. This means writing the code in c and then compiling to
an .ASM file to see how the program is implemented. Along the same lines, the MPLAB
Simulator will not be available to help debug the C code. Normally software bugs are
known and documented by the manufacturer, with the bugs repaired in later versions of
the software.


HARDWARE DEVELOPMENT TOOLS

7. HARDWARE DEVELOPMENT TOOLS

7.1 PICSTART PLUS PROGRAMMER
The PICSTART Plus is a Microchip Microcontroller development

programmer that enables to program user software into PICmicro
Microcontroller devices (DIP packages only-adapters available for
PIC16C9XX and PIC17C7XX devices). The PICSTART Plus device programmer system
consists of the following:
PICSTART PLUS DEVICE PROGRAMMER:
 Rs-232 Interface cable to connect to any standard PC serial port

 MPLAB software, an Integrated Development environment including a text
editor, project manager, MPASM assembler and MPLAB-SIM simulator.
 Blank chips for programming
 9V power supply
The PICSTART Plus device Programmer is a device programmer system that has the
following features:
• Programs PICMicrocontroller, including Program memory, configuration bits and

ID locations
• Operates as a Windows application on a PC-compatible host system within the
MPLAB Integrated Development Environment
• Communicates with the PC via a standard RS-232 cable
• With MPLAB IDE, the user can create, display and edit files to be programmed
into PIC Micro controllerssystem

7.2 IN CIRCUIT DEBUGGER:

In Circuit Debugger is a technique where a monitor programs runs on the PIC
micro controller in the application circuit. The ICD board or the PIC keys connects to the
MCU and to the PC. From any of applications it is then possible to set breakpoints on the
MCU, run code, single step, examine registers on the real device and change their values.
The ICD makes debugging real time device and change their values. The ICD makes
debugging real time applications faster, easier and more accurate then simulation tools
available for the MCU.
The in-circuit debugger (ICD) is a cost-efficient alternative to an in-circuit
emulator (ICE). It can do many things that were previously done only with more
expensive hardware, but the cost benefits come with a trade-off of some of the
conveniences of an in-circuit emulator. If users are willing to design their application to
be ICD compatible, they can enjoy the benefits of a low-cost hardware debugger.
As opposed to and ICE, some of the requirements of the in-circuit

debugger are:
 The in-circuit debugger requires exclusive use of some hardware and software
resources of the target.
 The target PIC micro controller MCU must have a functioning clock and be
running.
 The ICD can debug only when all the links in the system are fully functional.
As emulator provides memory and a clock, and can run code even
without being connected to the target application board. During the development
t and debugging cycle, an ICE provides the most power to get the
system fully functional, whereas an ICD may not be able to debug

at all if the application does not run. In-circuit debug connector can be placed on the
application board and connected to an ICD even after the system on the application board
and connected to an ICD even after the system is in production, allowing easy testing,
debugging and reprogramming of the application. Even though an ICD has some
drawbacks in comparison to an ICE, in this situation it has some distinct advantages:
• A connection to the application after the production cycle does not require extraction
of the Micro controller in order to insert an ICE probe. The ICD can reprogram the
firmware in the target application without any other connections or equipment.

BIBLIOGRAPHY
BIBLIOGRAPHY

[1] Roy Choudhury. D., Shail Hain., “Linear Integrated Circuits”, New Age International
(P) Ltd., Newdelhi, 2000.
[2] PIC16F87X Data Sheet 28/40-Pin 8-Bit CMOS Flash Microcontrollers
Websites:
[3] www.equipment and machinery Blood Bank FDCA.com
[4] www.ti.com
[5] www.analogdevice.com
[6] www.electronics-lab.com
[7] www.alldatasheets.com
[8] www.

12. CONCLUSION
In this project is only used in experiment only, but it made some error occurs
in this system, when we applying in industrial than only we get original
result s.
The CAN diagnostic tool captures the control data, which runs across the
CAN bus between the CAN modules, and it displays the status of the control
data on the system, to identify the presence of faulty CAN module. This
CAN diagnostic tool will be vey much helpful in the R&D department of
automobile industries and also even in the medical applications. In the
emerging trend of technology and science, the application of this system is
marked as an essential one. The main highlights of this tool are its
simplicity, efficient performance and robustness.







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IMPLEMENTATION OF CAN FOR AUTOMOBILE APPLICATION

Dept Of Electronics 1 SNR SONS College

The CAN protocol is rapidly being adopted as the standard

The main objective of the project, which is entitled as

Dept Of Electronics 2 SNR SONS College

ABOUT THE PROJECT

Dept Of Electronics 3 SNR SONS College

The project entitled “IMPLEMENTATION OF CAN FOR AUTOMOBILE

Dept Of Electronics 4 SNR SONS College

ABOUT THE PROJECT

2.1 EXISTING SYSTEM

Dept Of Electronics 5 SNR SONS College

• the (CAN-) object layer

Dept Of Electronics 6 SNR SONS College

Dept Of Electronics 7 SNR SONS College

HOW CAN WORKS

Dept Of Electronics 8 SNR SONS College

Dept Of Electronics 9 SNR SONS College

Performance of Error Detection

Dept Of Electronics 10 SNR SONS College

Dept Of Electronics 11 SNR SONS College

A DATA FRAME carries data from a transmitter to the receivers.

Dept Of Electronics 12 SNR SONS College

Dept Of Electronics 13 SNR SONS College

A Standard CAN (Version 2.0A)

Fig 3.CAN 2.0A Message Frame

A Control Field containing six bits:

Dept Of Electronics 14 SNR SONS College

consisting of seven ’recessive’ bits.

Version 2.0B evolved to provide compatibility with other serial communications

The differences are:

Dept Of Electronics 15 SNR SONS College

3.1.2 REMOTE FRAME

A REMOTE FRAME is composed of six different bit fields:

START OF FRAME, ARBITRATION FIELD, CONTROL FIELD, CRC FIELD,

Dept Of Electronics 16 SNR SONS College

An ’ ’error active’ station detecting an error condition signals this by transmission

The ERROR DELIMITER consists of eight ’recessive’ bits. After transmission of an

Dept Of Electronics 17 SNR SONS College

3.1.4 OVERLOAD FRAME

The start of an OVERLOAD FRAME due to OVERLOAD condition 1 is only allowed to

Dept Of Electronics 18 SNR SONS College

Fig 1. Bit time segments

Dept Of Electronics 19 SNR SONS College

Sync-seg is always one time quantum long

The first is hard synchronisation and occurs at Start-of-Frame (SOF).

At the message level:

Cyclic Redundancy Checks (CRC)

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At the bit level:

Cyclic Redundancy Check

Acknowledgement (ACK) Error Check

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The accumulated error counts determine the error status of a node.

Error Active Mode

Error Passive Mode

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Bus Off Mode

Error Detection Capabilities

Global errors which occur at all nodes are 100% detectable.

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BLOCK DIAGRAM AND BLOCK DIAGRAM

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