Module EECT505 Microelectronic & FPGA Design Project

Group Project Specifications

Project Overview
31-Tap FIR Filter Design using MATLAB and Quantise the coefficients Behavioural / Structural Implementation in MATLAB/Simulink RTL description in VHDL using FPGA Advantage Simulation of the filter using ModelSIM Synthesis of design using Precision Synthesizer Implementation of design on an FPGA prototyping board Real-Time testing using audio file input and speaker output

Project Overview Extras

Changing the FIR filter coefficients from MATLAB to FPGA Testing the filter using sample audio files in MATLAB RTL description of the filter using FPGA Advantage Simulation and Synthesis of the filter using ModelSIM and Precision with sample audio files

Introduction
Linear phase Symmetric Coefficients No feedback Stable Tapped Delay Line (TDL) Structure
Magnitude, dB

FIR Filter, N=30, Cut-off=0.08

20

Finite Impulse Response (FIR) -20 Filter

-40

-60

-80

-100 -0.5

-0.4

-0.3

-0.2

-0.1 0 0.1 0.2 Normalised Frequency,

0.3

0.4

0.5

h ( n ) = bi ( n i )
i =0

Introduction Contd
Coefficient Quantisation
Quantisation Types Truncate Round
Sample Coefficients: -0.007192517686923 0.000210733651977 0.135310291445863 0.371671492589083 0.371671492589083 0.135310291445863 0.000210733651977 -0.007192517686923
Magnitude, dB

FIR Filter, N=30, Cut-off=0.08

20 Floating Point Rounded to 9 bits 0

-20

-40

-60

-80

-100 -0.5

-0.4

-0.3

-0.2

-0.1 0 0.1 0.2 Normalised Frequency,

0.3

0.4

0.5

Project Phases
Phase 1
The design / implementation and testing of the 31-tap FIR filter in MATLAB with:
Normalised Cut-off: 0.08 (3.84kHz), Fs:48kHz Quantised Filter Stop band attenuation < -40dB

Simulations of filter responses for fixed and floating point coefficients Establishing number of bits needed for the computation The design / implementation and testing of a parametrizable Ripple Carry Adder in VHDL to be used in the filter process later on

Deliverables
m-files for the designed filter

Project Phases
Simulation plots of the filters responses for fixed and floating point coefficients vhd files. The VHDL synthesis and synthesised simulation results, demonstrating correct operation.

Phase 2
The design, VHDL implementation and testing of the simple parametrizable State-Store for the FIR Filter in FPGA Advantage Synthesis and simulations of the n-stage State-Store Includes LAB 2 covering the design procedure

Deliverables
vhd files including Test Benches. The VHDL synthesis and synthesised simulation results.

Project Phases
Phase 3
Assembly of the complete FIR filter elements designed in Phases 1 and 2. The multipliers to be used are those provided in the IEEE std-logic 1164 libraries, and available on the XILINX Spartan 3 XC3S2000FG676 Synthesis and simulations of the 30th-order FIR filter. Implementation and real time testing of the design on the Avnet ADS-XLX-SP3-DEV2000-G prototyping board.

Project Phases
Phase 3 Contd.
Includes LAB 3 covering the design procedure.

Deliverables
vhd files including Test Benches. The VHDL synthesis and synthesised simulation results. The output file after passing through the FPGA prototyped filter complying with the results of Phase 1, to include impulse and step responses.