VON NEUMAN ARCHITECTURE

Microcontrollers based on the Von-Neumann architecture have a single data bus that is used to fetch both instructions and data. Program instructions and data are stored in a common main memory. When such a controller addresses main memory, it first fetches an instruction, and then it fetches the data to support the instruction. The two separate fetches slows up the controllers operation. Figure shows the Von-Neumann Architecture. The Von-Neumann architectures main advantage is that it simplifies the microcontroller design because only one memory is accessed. In microcontrollers, the contents of RAM can be used for data storage and program instruction storage. For example, the Motorola 68HC11 microcontroller uses VonNeumann architecture. Example: An Instruction Read a byte from memory and store it in the accumulator as follows: Cycle 1 :- Read instruction Cycle 2 :- Read data out of RAM and put into Accumulator

Figure : Von Neumann Architecture Block diagram

HARVARD ARCHITECTURE
The name Harvard Architecture comes from the Harvard Mark I relay-based computer. The most obvious characteristic of the Harvard Architecture is that it has physically separate signals and storage for code and data memory. It is possible to access program memory and data memory simultaneously. Typically, code (or program) memory is read-only and data memory is read-write. Therefore, it is impossible for program contents to be modified by the program itself. You can increase the throughput because while you are executing 1 instruction you can be fetching the next instruction.

Microcontrollers based on the Harvard Architecture have separate data bus and an instruction bus. This allows execution to occur in parallel. As an instruction is being prefetched, the current instruction is executing on the data bus. Once the current instruction is complete, the next instruction is ready to go. This pre-fetch theoretically allows for much faster execution than Von-Neumann architecture, on the expense of complexity. Figure shows the Harvard Architecture. The Harvard Architecture executes instructions in fewer instruction cycles than the Von-Neumann architecture. For example, the intel MCS-51 family of microcontrollers and PIC microcontrollers uses Harvard Architecture.

The same instruction (as shown under Von-Newman architecture) would be executed as follows: Cycle 1: - Complete previous instruction - Read the Move Data to Accumulator instruction Cycle 2: - Execute Move Data to Accumulator instruction - Read next instruction Hence each instruction is effectively executed in one instruction cycle.

Figure : Harvard Architecture Block diagram

Microprocessors/controllers based on Harvard architecture will have separate data bus and instruction bus. This allows the data transfer and program fetching to occur simultaneously in both buses. With Harvard architecture, the data memory can be read and written while the program memory is being accessed. These separated data memory and code memory buses allow one instruction to execute while the next instruction is fetched (pre-fetching). The pre-fetch theoretically allows much faster execution than Von-Neumann architecture

. In the Harvard architecture, program and data are stored and handled by different subsystems. The main disadvantage of this is that it has low operating bandwidth. This is the essential difference between the two architectures.

However, in some niches, particularly certain embedded applications where the program is more-or-less hard wired, task requirements are such that the Harvard architecture can provide distinct operational advantages. Under certain conditions, a Harvard computer can be much faster than a von Neumann computer because data and program do not contend for the same information pathway, and storing the program in an immutable read-only memory can result in vast reliability improvements.

The following table highlights the differences between Harvard and Von-Neumann Architecture

Harvard Architecture

Von-Neumann Architecture

Separate buses for instruction and data fetching Single shared bus for instruction and data fetching Easier to pipeline, so high performance can be achieved Comparatively higher costs Since data memory and program memory are stored in different locations, no chances for accidental corruption of program memory Low performance compared to Harvard architecture Cheaper Since data memory and program memory are stored physically in the same chip, chances for accidental corruption of program memory