Name: Rajat Chowdhry Roll Number: 520810922 Learning Center: 2017 Subject Code: BC0046 Subject: Microprocessor Assignment

No.: 1 Course: Bachelor Of Computer Application (II Semester) Date of Submission at the Learning Center: 8th Dec, 2009

Ques.1 Ans.

Convert the hexadecimal number BB895C to octal and decimal.

Ques.2 Ans.

Write an assembly program to find the Biggest between two numbers.

Ques. 3 Ans.

Explain the internal architecture of 8086.

The internal architecture of 8086. Except for the instruction register, this is actually a 6byte queue the control unit and working registers are divided into three groups according to their functions. There is a data group, which is essentially the set of arithmetic registers: the pointer groups, which include base and index, registers, but also contain the program counter and stack pointer: and the segment group, which is a set of special purpose base registers. All of the registers are 16 bits wide. The data group consists of the AX, BX, CX and DX registers these can be used to store both operands and results and each of them can be accessed as a whole or the upper and lower bytes can be\e accessed separately. For example either the 2 bytes in BX can be itself by specifying BH or BL respectively. In addition to serving as arithmetic registers, the BX, CX and DX registers play special addressing, counting, and I/O roles: BX may be used as a base registers in address calculations. CX we used as an implied counter by certain instructions. DX is used to hold the I/O address during certain I/O operations. The pointer and index group consists of the IP, SP, BP, SI and DI registers. The instruction pointer IP and SP registers are essentially the program counter and stack pointer registers, but the complete instruction and stack addresses are formed by adding the contents of these registers to the contents of the code segments (CS) and stack segment (SS) registers. BP is a base register for accessing the stack and may be used with other registers and/or a displacement that is part of the instruction. The SI and DI registers are for indexing. Although themselves may use them, they are often used with the BX or BP registers and/or a displacement. Except for the IP, a pointer can be used to hold an operand but must be accessed as a whole. To provide flexible base addressing and indexing, adding together a combination of the BX or BP register contents may form a data address, SI or DI register contents a displacement. The result of such an address computation is a called an effective address (EA) or offset. The word displacement is used to indicate a quantity that is added to the contents of a registers(s) to form an EA. The final data address, however, is determined by the EA and the appropriate data segment (DS), extra segment (ES), or stack segment (SS) register.

Ques.4 Ans.

Find the 2s compliment of the word in AX without using NEG instruction

The binary addition and subtraction instructions are defined. All of them affect all of the condition flags. They may use any of the addressing modes for one of the operands, but, except

when the source operand is immediate, one of the two operands must be a register. They, as well as the other binary arithmetic instructions, can operate on either bytes or words Name Mnemonic and Description Format Add ADD DST, SRC (DST) (SRC)+(DST) Add with carry ADC DST, SRC (DST) (SRC)+(DST)+(CF) Subtract SUB DST, SRC (DST) (DST)-(SRC) Subtract with borrow SBB DST, SRC (DST) (DST)-(SRC)-(CF) Flags: All condition flags are affected. Addressing modes: Unless the source operand is immediate, one of the operands Must be in a register. The other may have any addressing mode Signed mixed mode arithmetic involving extending the sign of the shorter number until the numbers have same length can form two different precisions. The CBW and CWD instructions are designed to aid the sign extension process. The CBW instruction extends the sign of byte in AL to yield an equivalent 2's complement one word result in AX, e.g., if the (AL) = C5, then after CBW is executed (AX) will be FFC5. Similarly, CWD extends the sign of the word in AX to DX, thus forming a double word in DX: AX. In both of these instructions the operand is implied by the op code and neither instruction affects the flags. The code needed to add the single-precision number in BX to the double-precision number in DP and DP + 2 and put the Result back into DP and DP+2. The INC, DEC and NEG instructions have only one operand; INC adds 1 to the operand, DEC subtracts 1 from the operand, and NEG negates the operand. They may employ any addressing mode other than the immediate mode. INC and DEC are used primarily for counting and indexing and are used extensively in looping. The CMP instruction is identical to SUB except. That the result is not stored anywhere. It is used only to set the flags and is normally placed just prior to a conditional jump instruction. It sets the flags according to the relationship between its operands and the branch is taken or not taken depending on the flags, i.e., according to the relative magnitudes of the operands being compared. Applications of the CMP instruction are considered later when jumps are introduced. The binary multiply and divide instructions. The multiply instructions may multiply bytes and produce a word result or multiply words and produce a double-word result. For a signed multiply, if the high-order byte (word) of the product is not simply the sign extension of the low-order byte (word), then both CF and OF are set to 1; otherwise they are both set to 0. For an unsigned multiply, both CF and OF are set to 1 if the high-order byte (or word) of the product is nonzero; otherwise both are cleared. By checking these flags it can be determined whether or not the magnitude of the product was small enough to fit into a single byte (word).

Ques.5 Ans.

Explain the concept of Linking and Relocation.

In constructing a program some program modules may be put in the same source module and assembled together; others may be in different source modules and assembled separately. If they are assembled separately, then an END statement must terminate the main module, which has the first instruction to be executed, with the entry point specified, and each of An END statement with no operand must terminate the other modules. In any event, the resulting object modules, some of which may be grouped into libraries, must be linked together to form a load module before the program can be executed. In addition to outputting the load module normally the linker prints a memory map that indicates where the linked object modules will be loaded into memory. After the load module has been created it is loaded into the memory of the computer by the

loader and execution begins. Although modules within the program can perform the I/O, normally I/O drivers that are part of the operating system do the I/O. All that appears in the user's program are references to the I/O drivers that cause the operating system to execute them. The general process for creating and executing a program is illustrated the process for a particular system may not correspond exactly to the one diagrammed in the figure, but the general concepts are the same. The arrows indicate that corrections may be made after anyone of the major Stages

Ques.6 Write a sequence of instructions using string instructions wherever necessary to check whether a byte stored in AL is present in array of 10 bytes stored in the memory. Store the number of occurrences of the byte in register AH. Ans.

Ques.7 Draw a flowchart showing a block of N bytes are input to memory using Programmed IO, using a block transfer

A resource of this type, which is commonly referred to as a serially reusable resource, must be protected from being simultaneously accessed and modified by two or more processes. A serially reusable resource may be a hardware resource (such as a printer, card reader, or tape drive), a file of data, or a shared memory area. For example, let us consider a personnel file that is shared by processes 1 and 2. Suppose that process 1 performs insertions, deletions, and changes, and process 2 puts the file in alphabetical order according to last names. If accessed sequentially, this file would both be updated by process 1 and then sorted by process 2, or vice versa. However, if both processes were allowed to access the file at the same time, the results would be unpredictable and almost certainly incorrect. The solution to this problem is to allow only one process at a time to enter its critical section of code, i.e., that section of code that accesses the serially reusable resource. Preventing two or more processes from simultaneously entering their critical sections for accessing a shared resource is called mutual exclusion. One way to attain mutual exclusion is to use flags to indicate when the shared resource is already in use. To examine how this is done and some of the problems associated with this approach let us consider the possibility of using only one flag. If there is only one flag and FLAG = 1 indicates that the resource is free and FLAG = 0 indicates it is busy, and then two processes that access the resource might be implemented as follows: Process 1 P1: TRY AGAIN1: TEST FLAG, 1 JZ TRYAGAIN1 MOV FLAG, 0 } Critical section in process 1 MOV FLAG, 1
Ans.

Process 2 P2: TRYAGAIN2: TEST JZ MOV MOV FLAG, 1 TRYAGAIN2 FLAG, 0 } Critical section in process 2 FLAG, 1

Where the first MOV instructions set the flag to 0 in an attempt to prevent the other process from entering the resource.

Ques. 8 Ans.

Explain 8284A clock generator.

A processor is in minimum mode when its MN /MX pin is strapped to +5 V. The definitions for pin: 24 through 31 for the minimum mode and a typical minimum mode configuration. The address must be latched since it is available only during the first part of the bus cycle. To signal that the address is ready to be latched a 1 is put on pin 25, the address latch enable (ALE) pin. Typically, the latching is accomplished using Intel 8282s. Because 8282 is an 8-bit latch, two of them is needed for a 16-bit address and three are needed if a full 20-bit address is used. In an 8086 system, BHE would also have to be latched. A signal on the STB pin latches the bits applied to the input data lines DI7-DI0. Therefore, STB is connected to the 8086's ALE pin and DI7-DIO is attached to eight of the address lines. An active low signal on the OE enables the latch's outputs DO7-DO0, and a 1 at this pin forces the outputs into their high-impedance state. In an 8086 single processor system that does not include a DMA controller this pin is grounded. If a system includes several interfaces, then drivers and receivers, which may not be needed on small, single-board systems, will be required for the data lines. The Intel IC device for implementing the transceiver (driver/receiver) block shown in Fig. 9.3 is the 8286 transceiver device. The 8286 contain 16 tractate elements, eight receivers, and eight drivers. Therefore, two 8286 ICs are needed in an 8086 system. Shows how 8286s are connected into a system and a logic diagram of one of its cells. The 8286 is symmetric with respect to its two sets of data pins, either the pins A7-A0 can be the inputs and B7-B0 the outputs, or vice versa: The output enable (OE) pin determines whether or not data are allowed to pass Through the 8286 and the transmit (T) pin controls the direction of the data flow. When OE = 1, data are not transmitted through the 8286 in either direction. If it is 0, then T = 1 causes A7-A0 to be the inputs and T = 0 results in B7-B0 being the inputs. In an 8086-based system the OE pin would be connected to the DEN pin, which is active low whenever the processor is performing an I/O operation. The A7-A0 pins are connected to the appropriate address/data lines and the T pin is tied to the processor's DT/R pin. Thus, when the processor is outputting the data flow is from A7- A0 to B7-B0, and when it is inputting the flow is in the other direction. The processor floats the DEN and DT/R pins in response to a bus request on The HOLD pin.

Ques. 9 Ans.

Explain Conditional branch Instructions with example

Ques. 10 Ans.

Explain the pin diagram of 8087 numeric Data processor.

The 8087 numeric data processor (NDP) is specially designed to perform arithmetic operations efficiently. It can operate on data of the integer, decimal, and real types, with lengths ranging from 2 to 10 bytes. The instruction set not only includes various forms of addition, subtraction, multiplication, and division, but also provides many useful functions, such as taking the square root, exponentiation, taking the tangent, and so on. As an example of its computing power, the 8087 can multiply two 64-bit real numbers in about 27 s and calculate a square root in about 36 s. If performed by the 8086 through emulation, the same operations would require approximately 2 ms and 20 ms, respectively. The 8087 provides a simple and effective way to enhance the performance of an 8086 based system, particular when an application is primarily computational in nature The address/data, status ready, reset, clock, ground, and power pins of the NDP have the same pin positions as those assigned to the 8086/8088. Among the remaining eight pins, four of them are not used. The other pins are connected as follows: the BUSY pin to the hosts TEST pin; the RQ/GT0 pin to the host's RQ/GT0 or RQ/GT1pin; the INT pin to the interrupt management logic (assuming the 8087 is enabled for interrupts); and the RQ/GT1could be connected to the bus request/grant pin of an independent processor such as an 8089. This simple interface allows an existing maximum mode 8086-based system to be easily upgraded by replacing the original CPU with a piggyback module, which consists of an 8086/8088 and an 8087.