Cell Library Design

CELL LIBRARY DESIGN

BY TEAM N8 MOHAMED RASHID KARIM RAJESH MANGALORE ANAND SUMANTH SHIVALINGAIAH UMAMAESH BALASHANMUGHAM VASILIS MYLONAKIS

M S c MI C RO E L E CT RO NI CS S YS T E M DE S I G N S CH O O L O F E L E C T R O NI C S A N D CO MP UT E R S CI E NC E U NI V E R S I T Y O F S O UT H A M PT O N , S O UT H A MP T O N
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TABLE OF CONTENTS
1. INTRODUCTION 2. DATASHEETS 2.1 Scannable D-type Flip Flop 2.2 ScannableRegister 2.3 Raw D-type Flip Flop 2.4 Two input Scan Multiplexer 2.5 Three input Scan Multiplexer 2.6 Standard Multiplexer 2.7 Full Adder 2.8 Half Adder 2.9 Left Buffer 2.10 Right End 2.11 Inverter 2.12 Buffer 2.13 Two input Nand 2.14 Two input Nor 2.15 Two input And 2.16 Two input Or 2.17 Three input Nand 2.18 Three input Nor 2.19 Four input Nand 2.20 Tristate Buffer () () () () () () () () ()
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2.21 TieHigh, TieLow, RowCrosser 3. SUMMARY 4. REFERENCES 5. APPENDIX A 6. APPENDIX B ()

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1. INRODUCTION
Microelectronics design usually requisites theoretical expertize from

understanding fundamental physics to engineering implementation of complex systems. This flow of skillsets can be visualized in three levels. Device Level: This involves studies in independent particle

approximation by itself, or in turn influences from ions [1] to solid state device characteristics. Circuit Level: Realising behaviour of logical families with timing, switching, and RTL considerations. System Level: Building custom designs in analogue or digital domain and simulating functionality of systems in structural and behaviour modular styles.

FIGURE 1: Abstract levels of Microelectronics System Design [2] Cell Library Design is one such part in System Level which has common logic gate families circuit symbols, schematic designs, stick diagrams, layouts,

optimized and characterized designs. Cell Library is adopted by most of the hardware designers in industries to build architecture of some standard cells and re-use it with minimal changes so as to lessen cost and time taken to build cells from root level. Based on the requirements, contents of the Cell Library can vary from the fundamental building blocks of logic gate family like INVERTER, AND, OR, NOR, NAND, XOR, XNOR to complex logical implementations like MUX, ENCODER, FLIPFLOPS. This semi -custom design model of Cell Library in VLSI provides range of the support for all the designs whe re designers choose their right choice and implement with less effort. Some cases, Cell Libraries are

utilized as reference manual to understand standard functionality of devices better.

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In this Report, detailed information of each individual cells design ed by the team is given with respect to the Cell specifications. Gate -level schematics, Stick Diagrams, Layout Diagrams, and Characterisation of some standard designs with H-Spice as well as Verilog simulation are described along with final results. The specified Gate level schematics are transformed to layout by drawing Stick Diagrams. The placement of the transistors from the schematic to stick diagram is implemented by using Gate Matrix Style. Its a technique which uses Boolean expressions to determine gate arrays to optimize layout. When complexity of the

circuit increases, the transistors sharing common gate connection: Gate Matrix style often gives more efficient use of area. The inputs and outputs are

represented by polysilicon and metal for other c onnections, although multiple transistors are allowed to use same polysilicon column in Stick Diagrams shown in this report [1]. The MOSFETs are developed by placing polysilicon in between diffusion layers, i.e. NMOS by n-diffusion layer represented as gr een, and PMOS by p-diffusion layer represented as yellow. The contacts are used to draw

connections to power rail (Vdd!) Ground rail (GND!) as well as other sources. Cell design is carried out in MAGIC as the VLSI Layout tool platform at 0.35u CMOS Technology. All the transistors size is fixed throughout design: [Width of pmos, Wp=2.0um, Width of nmos, Wn=1.2um, Length of pmos a nd nmos,

Lp=Ln=0.35um]. The working floor in the Layout was set to GRID 12 to align cell width, power rails to 1.2um. Metal1 is used as horizontal connections whereas Metal2 for vertical Input and Output connections. The heights of all cells are same 585 magic units, but width varies from one another to ensure proper placing and routing between interconnecting cells . Each cell has common alignment to origin (0, 0) as shown below [3 ].
I0 Scan ScanReturn Test Clock nReset Vdd!
N-well

I1

P-well

GND!

FIGURE 2: Generic view of any cell designed in the report

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The characterization of cells designed requires real -time simulation under faulty circumstances to determine their performance capabilities in hierarchical

conditions. Cell designs may be simulated using HSpice (analogue simulation) or System Verilog (digital simulation) [3]. Therefore, for any cell, Drive Inverters drive the inputs and Load Inverters load the outputs. The propagation delay, rise time, and fall-time delays are extracted for each output with HSpice simulations. The NC-Verilog digital simulator simulates the behaviour of a digital circuit to compute values of corresponding to each input and output states.

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2. DATASHEETS
Cell Name: XOR2 Cell Designer: Rajesh Mangalore Anand

Description: It is a 2 input logical gate that functions as exclusive OR, i.e. if two of the inputs are (0 , 0) or (1, 1), then it results 0 as output. TRUTH TABLE CELL SYMBOL CELLABSTRACT
A B Y

A 0 0 1 1

B 0 1 0 1

Y 0 1

A XOR2 B
GATE LEVEL CIRCUIT DIAGRAM

Scan ScanReturn Test Clock nReset Vdd!

30.65m
N-well

1
A
P-well

B
GND!

7.2m AREA = 4413.6m2

MEASUREMENT OF PARAMETERS

INPUT V/S OUTPUT A=>Y B=>Y

Propagation Delay(ps) Rise Time 260.7 256.6 Fall Time 198.9 197.7

VERILOG SIMULATION WAVEFORM

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Cell Name: HALFADDER

Cell Designer: Rajesh Mangalore Anand

Description: It is a 2 input logical circuit that generates only SUM=1, adding 0 and 1(vice-versa), and only CARRY=1, when both inputs are 1 and 1.

TRUTH TABLE

CELL SYMBOL

CELL ABSTRACT

A 0 0 1 1

B 0 1 0 1

S 0 1 1 0

C 0 0 0 1

HALF ADDER

Scan ScanReturn Test Clock C nReset Vdd!

30.65m
N-well

GATE LEVEL CIRCUIT DIAGRAM

A B S

P-well

GND!

10.8m
C

AREA = 6620.4m2

MEASUREMENT OF PARAMETERS

INPUT V/S OUTPUT A=>S B=>S A=>C B=>C

Propagation Delay(ps) Rise Time 198.5 184.3 223.8 232.1 Fall time 221.6 219.5 192.8 186.1

VERILOG SIMULATION WAVEFORM

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Cell Name: TRISTATE BUFFER

Cell Designer: Rajesh Mangalore Anand

Description: It is a three state logic gate in which output follow the respective input only when ENABLE is HIGH.

TRUTH TABLE

CELL SYMBOL

CELL ABSTRACT

A 0 1 0 1

ENABLE 0 0 1 1

Y Z Z 0
GATE LEVEL CIRCUIT DIAGRAM

ENABLE

TRISTATE BUFFER

ENABLE

Scan ScanReturn Test Y Clock nReset Vdd!

30.65m

N-well

1
A Y ENABLE
GND! P-well

8.4m AREA = 5149.2m2

MEASUREMENT OF PARAMETERS

INPUT V/S OUTPUT A=>Y ENABLE=>Y

Propagation Delay(ps) Rise Time 263.8 222.3 Fall Time 188.0 143.7

VERILOG SIMULATION WAVEFORM

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Cell Name: NAND2

Cell Designer: Rajesh Mangalore Anand

Description: It is a 2 input negated logic gate of 2 inputs AND gate that outputs 0 only when two inputs are 1. TRUTH TABLE CELL SYMBOL CELL ABSTRACT

A 0 0 1 1

B 0 1 0 1

Y 1 1 1 0
A NAND2 B Y
Scan ScanReturn Test Clock nReset Vdd!

30.65m

GATE LEVEL CIRCUIT DIAGRAM

N-well

A B Y
GND! P-well

MEASUREMENT OF PARAMETERS

4.8m AREA = 2942.4m2

INPUT V/S OUTPUT A=>Y B=>Y

Propagation Delay(ns) Rise Time 126.7 121.5 Fall Time 125.6 134.3

VERILOG SIMULATION WAVEFORM

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Cell Name: TIEHIGH, TIELOW, ROWCROSSER Cell Designer: Rajesh Mangalore Anand Description: These are special standard cells facilitate in overcoming

Electrostatic Discharging and also involves in Automatic Routing and Placing. TieHigh is associated with power rail - Vdd, and TieLow with ground rail GND! respectively. Row-crosser is a connective cross port that allows

connection between two cell channels above or below it.

Vdd! Scan ScanReturn Test Clock nReset Vdd!

30.65m
N-well

GND! Scan ScanReturn Test Clock nReset Vdd!

30.65m
N-well

P-well

P-well

GND!

GND!

6m AREA = 3678m2
Scan ScanReturn Test Clock nReset Vdd!
30.65m
N-well

6m

cross

AREA = 3678m2

P-well

GND!

6m AREA = 3678m2

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3. SUMMARY
Each extracted cell (.ext format) was transformed to simulate in SystemVerilog mode as well as Spice mode. Care was taken to generate output for all possible gray code inputs. The behaviour of each cell was thus analysed graphically. Characterization of cells was prime stage to know drive and load capabilities [3].

FIGURE 3: Characterization of any cell Propagation delays of output with respect to input for every cell were calculated and tabulated for loaded circuits as shown below [3].

FIGURE 4: Propagation Delay calculation [3] All individual cells designed later were butted based on the specified order to form all.mag (parent cell). These consist of paints, labels, and sub-cells. Clearing Sanity Checks for all.mag cell was underpinning as more time was spent to make it error-free. Each team member played an important role in working better Cell design. Perhaps, more emphasis would have been given in lessening the overall area of all.mag cell. With efficient use of Euler paths to deduce Gate Level Circuit diagram to Stick Diagram, smaller layout with least number of line of diffusions in transistors were designed. Design Rule Check (DRC) from Cadance Virtuoso and Mentor calibre was a new environment to work on as team had new experience in sorting out errs. Having brief description of errors in laboratory, XP_6 was solved by placing at least one p-well strap in p-well, whereas XP_4 warned less spacing of p-active in p-wells. R_27 showed that metal2 via is left alone in power rails, but resolved commandingly. Overall, it was a fruitful team effort to make Cell Design Data book.

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4. APPENDIX A
The division of labour in a team is always a tough task to work towards an objective till it is achieved. However, each member in our team was given clear idea what is expected from and how deadline is to be met! Team meetings were held regularly to discuss the progress of each work and suggestions were shared. The major cells were classified as below: Raw D-Type (rdtype): Two Scan Multiplexer (smux2, smux3): Full Adder (fulladder): Half Adder (halfadder): End of Row Cells (leftbuf, rigthend): Mohamed Rashid Karim Vasilis Mylonakis Sumanth Shivalingaiah Rajesh Mangalore Anand Umamahesh Balashanmugham

The Stick Diagram preparation, Layout Floor planning, Cell Characterization, Analogue Simulation (Hspice) as well as Digital Simulation (SystemVerilog) for above major cells was done by each of member as shown above respectively. Although, basic cells were taken up in such a way that work is distributed equally amongst all. There was room for each member to give relevant ideas, encourage challenging tasks, and criticize design rule violations which were accepted sportively. At last, creating all.mag combing all cells was done by one, with all teammates presence. Though, lots of care was taken while designing each cell, still many errors existed while butting all cells together. Design Rule Check (DRC) in Cadence Virtuoso and Mentor This crucial task

Calibre was very important stage to assess and correct flaw prone cells.

took time, but timely, the team cleared all errs to finish with error-free cell library. As a result, the cell library was created before the deadline and submitted. The Cell Design work carried out was documented with all technical evidences of each individual cell from introduction to layout, execution to simulation, optimization to characterization, and references to appendices. thoroughly by respective designers. Datasheets of each cell was prepared

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DIVISION OF LABOUR TASK ECS ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 rdtye smux2 smux3 mux2 fulladder halfadder xor2 inv nand2 nand3 nand4 nor2 nor3 and2 or2 trisbuf buffer leftbuf rigthend tiehigh tielow rowcrosser scandtype scanreg Verilog simulation Hspice characterization Final Report(words) Final Report(Figures) OVERALL EFFORT 100 100 100 100 100 100 100 20 20 30 20 20 PERCENTAGE EFFORT ON EACH TASK rma1g11 ss11g11 100 100 100 100 20 20 30 20 20 umb1g11 100 100 100 100 100 20 20 20 20 20 mrk1g11 100 50 50 20 20 10 20 20 vme2g11 100 100 100 100 100 50 50 20 20 10 20 20

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5. APPENDIX B
Cell Name: HALF ADDER The Boolean expression for Half Adder has two parts for Sum and Carry .i.e. Sum=A+B: Carry= AB. This equation is realized in the circuit using Euler Paths shown below. STICK DIAGRAM CIRCUIT SCHEMATIC

S C

S C

CIRCUIT FOR LOADED SIMULATION: Circuit shown below has two driving inverters for two inputs A and B, four loaded inverters for two outputs Sum (S) and Carry (C). When simulating this circuit, we are only looking for the characteristics of primary inputs A, B and outputs S, C of the cell under test, but not the behaviour of inverters.

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RESULTS OF LOADED SIMULATION:

HSpice simulator is used to evaluate behavioural characteristics like rise time, slew rate, duty cycle, frequency and many more [5]. Spice file (.sp) helps to prepare all input and output waveforms and also in calculating propagation delays, whereas, .tr0 file displays specified waveforms. cat. <cellname>.mt0 is used to calculate rise and fall delays[3]. The numerical calculations of propagation delay are tabulated in the HALFADDER Datasheet has two parameters. They are: Fall Time Propagation Delay: Measuring the change in output signal due to input signal fall at Vdd*50% of ouput to Vdd*50% of input Rise Time Propagation Delay: Measuring the change in output signal due to input signal rise at Vdd*50% of ouput to Vdd*50% of input

Here, we calculate the Time Delay in two terms as explained below. Fall Time Delay: Measuring the output signal triggered when signal falls at Vdd*10% and Vdd*90% Rise Time Delay: Measuring the output signal triggered when signal rises at Vdd*10% and Vdd*90%

Note: Vdd is set to 3.3V when written in .sp file Time Delay (ps) OUTPUT S C Rise Time 228.7 242.4 Fall Time 174.0 166.6

HSpice Simulation Waveform

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6. REFERENCES: 1. Atomic and Electronic Structure of solids, by Efthimios Kaxiras, Harvard University, Massachusetts. 2. Design of semi-custom IC, by Dr. Zhou Xing, Nanyang Technological University. 3. http://users.ecs.soton.ac.uk/bim/notes 4. HSPICE Simulation and Analysis User Guide by Synopsys 5.

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