EE141

1
Pass
Pass
-
-
Transistor
Transistor
Logic
Logic
EE141
2
Pass
Pass
-
-
Transistor Logic
Transistor Logic
I
n
p
u
t
s
Switch
Network
Out
Out
A
B
B
B
N transistors
No static consumption
Primary inputs drive the gate terminals + source-drain terminals. In contrast to static CMOS
primary inputs drive gate terminals.
EE141
3
Example: AND Gate
Example: AND Gate
B
B
A
F = AB
0
When B is 1, top device turns on and copies the input
A to output F. When B is low, bottom device turns on
and passes a 0.
The presence of the switch driven by B is essential to
ensure that the gate is static a low-impedance path
must exist to supply rails.
Adv.: Fewer devices to implement some functions.
Example: AND2 requires 4 devices (including inverter to
invert B) vs. 6 for complementary CMOS (lower total
capacitance).
NMOS is effective at passing a 0, but poor at pulling a node to Vdd. When the pass transistor a
node high, the output only charges up to V
dd
-V
tn
. This becomes worse due to the body effect.
The node will be charged up to V
dd
V
tn
(V
s
)
)) 2 2 ( (
0 f s f tn dd s
V V V V + +
EE141
4
NMOS
NMOS
-
-
Only Logic
Only Logic
0 0.5 1 1.5 2
0.0
1.0
2.0
3.0
Time [ns]
V
o
l
t
a
g
e
[
V
]
s
Out
In
V
s
is initially 0. V
s
will initially charge up quickly, but the tail end of the transient is slow. The
current drive of the transistor (gate-to-source voltage) is reduce significantly as V
s
approaches V
dd
-V
tn
(the current available to charge up node s is reduced drastically.
For cascading, the output of a pass transistor (#1) should not drive the gate of another MOS
device (#2). This will produce an output = V
dd
-V
tn1
-V
tn2
V
DD
In
Out
s
0.5m/0.25m
0.5m/0.25m
1.5m/0.25m
EE141
5
Energy Consumption
Energy Consumption
V
DD
In
Out
s
0.5m/0.25m
0.5m/0.25m
1.5m/0.25m
Pass transistors require lower switching energy to charge up a node, due to the reduces
voltage swing. The output node charges from 0 -> V
dd
-V
tn
, and the energy drawn from the
power supply for charging the output of a pass transistor is given by C
L
.V
dd
(V
dd
-V
tn
)
While lower switching power is consumed, it may consume static power when output is high
the reduced voltage level may be insufficient to turn off the PMOS transistor of the subsequent
CMOS inverter.
EE141
6
Complementary Pass Transistor Logic
Complementary Pass Transistor Logic
A
B
A
B
B B B B
A
B
A
B
F=AB
F= AB
F=A+B
F =A+B
B B
A
A
A
A
F=A
F= A
OR/NOR
EXOR/NEXOR AND/NAND
F
F
Pass-Transistor
Network
Pass-Transistor
Network
A
A
B
B
A
A
B
B
Inverse
(a)
(b)
Since circuit is differential, complimentary inputs and outputs are available. Although generating differential
signals require extra circuitry, complex gates such as XORs, MUXs and adders can be realized efficiently.
CPL is a static gate, because outputs are connected to Vdd or GND through a low-resistance path (high noise
resilience).
Design is modular all gates use same topology; only inputs are permuted. This facilitates the design of a
library of gates.
To accept and produce true
and complementary inputs
and outputs.
EE141
7
Main Problems of NMOS
Main Problems of NMOS
-
-
only Switch
only Switch
A = 2.5 V
B
C = 2.5
V
C
L
A = 2.5 V
C = 2.5 V
B
M
2
M
1
M
n
Threshold voltage loss causes
static power consumption + slower transition
V
B
does not pull up to 2.5V, but 2.5V -V
TN
EE141
8
NMOS Only Logic:
NMOS Only Logic:
Level Restoring Transistor
Level Restoring Transistor
M
2
M
1
M
n
M
r
Out
A
B
V
DD
V
DD
Level Restorer
X
Advantage: Full Swing. Eliminates static power in inverter + static power through level restorer and pass
transistor, since restorer is only active when A is high.
Restorer adds capacitance, takes away pull down current at X contention between M
n
and M
r
(slower
switching). Hence M
r
must be sized small. M
n
and M
r
must be sized such that the voltage at node X drops
below the threshold of the inverter V
M
, which is a function in the sizes of M
1
and M
2
.
EE141
9
Solution 2: Single Transistor Pass Gate with
Solution 2: Single Transistor Pass Gate with
V
V
T T
~0
~0
Out
V
DD
V
DD
2.5V
V
DD
0V
2.5V
0V
WATCH OUT FOR LEAKAGE CURRENTS
(DC Sneak path)
Use very low threshold values for NMOS
pass transistors, and standard high-
threshold devices for inverters.
Note: Body effect will still cause an
increase in the threshold voltage.
While these leakage paths are not critical
when the device is switching constantly,
they do pose a large energy overhead
when the circuit is in the ideal state.
EE141
10
Solution 3: Transmission Gate
Solution 3: Transmission Gate
A
B
C
C
A B
C
C
B
C
L
C= 0 V
A = 2.5 V
C = 2.5 V
NMOS passes a strong 0
PMOS passes a strong 1
Transmission gates enable rail-to-rail swing
These gates are particularly efficient in
implementing MUXs
A
M
2
M
1
B
S
S
S
F
V
DD
F=(AS+ BS)
6 devices vs. 8 for complementary CMOS
EE141
11
Another Example: Transmission Gate XOR
Another Example: Transmission Gate XOR
A
B
F
B
A
B
B
M1
M2
M3/M4
6 devices (including inverter for B) vs. 12 for
complementary CMOS
For B=1, M3 & M4 are off, M1 & M2 are on. F = AB
For B=0, M1 & M2 are off. M3 & M4 are on. F = AB
Regardless of the value of A & B, node F is
connected to V
dd
or GND (static gate)
EE141
12
Resistance of Transmission Gate
Resistance of Transmission Gate
V
out
0 V
2.5 V
2.5 V
R
n
R
p
0.0 1.0 2.0
0
10
20
30
V
out
, V
R
e
s
i
s
t
a
n
c
e
,

o
h
m
s
R
n
R
p
R
n
|| R
p
R
n
{(V
dd
-V
out
)/I
n
} & R
p
{(V
dd
-V
out
)/I
p
} are in parallel. The currents through devices are
dependent on value of V
out
and hence the operating mode of the transistors. During the low-
to-high transition, the pass transistors traverse through a number of operation modes.
Since V
d
and V
g
= V
dd
, the NMOS is either in saturation or off. The PMOS changes from
saturation to linear during the transient.
EE141
13
q V
out
< |V
tp
|: NMOS and PMOS saturated
q |V
tp
| < V
out
< V
dd
V
tn
: NMOS saturated, PMOS linear
q V
dd
-V
tn
< V
out
: NMOS cutoff, PMOS linear
R
eq
is relatively constant. Thus when analyzing transmission-gate networks, the
simplifying assumption that the switch has a constant resistive value is
acceptable.
( )
) (
1
2
) (
) (
2
tn dd n
out dd
out dd tn dd n
out dd
n
out dd
n
V V k V V
V V V V k
V V
I
V V
R

1
]
1

Similarly,
) (
1
tp dd p
p
out dd
p
V V k I
V V
R

V
out
0 V
2.5 V
2.5 V
R
n
R
p
0.0 1.0 2.0
0
10
20
30
V
out
, V
R
e
s
i
s
t
a
n
c
e
,

o
h
m
s
R
n
R
p
R
n
|| R
p
EE141
14
Delay in Transmission Gate Networks
Delay in Transmission Gate Networks
V
1 V
i-1
C
2.5 2.5
0 0
V
i V
i+1
C
C
2.5
0
V
n-1 V
n
C
C
2.5
0
In
V
1 V
i Vi+1
C
V
n-1 V
n
C
C
In
R
eq
R
eq
R
eq
R
eq
C C
(a)
(b)

+

n
k
eq eq p
n n
CR k CR t
0
2
) 1 (
69 . 0 69 . 0
t
p
is proportional to n
2
and increases rapidly with the number of switches in the
chain.
Solution: Insert buffers.
EE141
15
Delay Optimization
Delay Optimization
V
1 V
i-1
C
2.5 2.5
0 0
V
i V
i+1
C
C
2.5
0
V
n-1 V
n
C
C
2.5
0
In
V
1
V
i Vi+1
C
V
n-1 V
n
C
C
In
R
eq
R
eq
R
eq
R
eq
C C
(a)
(b)
C
Req Req
C C
R
eq
C C
Req Req
C C
Req
C
In
m
(c)
buf eq p
t
m
n m m
CR
m
n
t

,
_

+
1
]
1

+
1
2
) 1 (
69 . 0 Linear dependence on n instead of n
2
To find m
opt
, then yielding
eq
buf
opt
CR
t
m 7 . 1
0

m
t
p