Verilog

Verilog was designed in early 1984 by Gateway Design automation. Gateway Design automation and its Verilog based tools were later acquired by Cadence Design systems. Since then Cadence has been a strong force behind popularizing the Verilog hardware Description language. In 1990, OVI (Open Verilog International) was formed and Verilog was placed in public domain. It became IEEE standard in 1995. Verilog is used to model a system from algorithmic level to switch level of abstraction. It has a capability to describe behavioral, dataflow and structure of digital systems.

Module:
A basic unit of description in Verilog is module. It describes the functionality or structure of a design and also describes the ports through which it communicates externally with other modules.

Basic syntax of a module. module module-name (port-list)

declarations: reg, wire, parameter, input, output, inout function, task,. Statements Initial statement always statement module instantiation gate instantiation Continuous assignment

endmodule

Verilog code for a half adder Timescale 1ns/100ps Module halfadder (a, B, sum, carry); Input A, B; Output sum, carry Assign #2 sum = A ^ B; Assign #5 carry = A & B; Endmodule *** timescale is a compiler directive. Timescale 1ns/100ps means that one time unit is to be treated as 1 ns and that the time precision is to be 100 ps(all dealys must be rounded to 0.1ns) **** Assign #2 means assign after 2 time units or 2ns. Verilog code for a MUX (4 X 1)
module MUX (A, B, C, D, S, Q) INPUT A, B, C, D; INPUT [1:0] S; OUTPUT Q; WIRE A, B, C, D, S; REG Q; BEGIN : MUX If(S ==2b00) begin Q <= A; End Else If(S ==2b01) begin Q <= B; End Else If(S ==2b10) begin Q <= C; End Else If(S ==2b11) begin Q <= D; End End Endmodule **** 2b means 2 bit binary

Verilog code for a D flipflop Module DFF (clk, D, set, Q, Qbar) Input clk, D, set; Output Q, Qbar; Reg Q, Qbar Always Wait(set==1) Begin #3 Q =1; #2 Qbar =0; Wait(set==0) end Always @(negedge clk) begin if(set!=1) Begin #5 Q =D; #2 Qbar =-Q; End end Endmodule

Verilog code for a 4-bit up counter counter

module first_counter ( 10 clock , // Clock input of the design 11 reset , // active high, synchronous Reset input 12 enable , // Active high enable signal for counter 13 counter_out // 4 bit vector output of the counter 14 ); // End of port list 15 //-------------Input Ports----------------------------16 input clock ; 17 input reset ; 18 input enable ; 19 //-------------Output Ports---------------------------20 output [3:0] counter_out ; 21 //-------------Input ports Data Type------------------22 // By rule all the input ports should be wires 23 wire clock ; 24 wire reset ; 25 wire enable ; 26 //-------------Output Ports Data Type-----------------27 // Output port can be a storage element (reg) or a wire 28 reg [3:0] counter_out ; 29 30 //------------Code Starts Here------------------------31 // Since this counter is a positive edge trigged one, 32 // We trigger the below block with respect to positive 33 // edge of the clock. 34 always @ (posedge clock) 35 begin : COUNTER // Block Name 36 // At every rising edge of clock we check if reset is active 37 // If active, we load the counter output with 4'b0000 38 if (reset == 1'b1) begin 39 counter_out <= #1 4'b0000; 40 end 41 // If enable is active, then we increment the counter 42 else if (enable == 1'b1) begin 43 counter_out <= #1 counter_out + 1; 44 end 45 end // End of Block COUNTER 46 47 endmodule // End of Module counter