CLOCKLESS CHIPS 1 ABSTRACT Clock less approach, which uses a technique known as asynchronous logic, differs from conventional

computer circuit design in the switching on and off of digital circuits are controlled individually by specific pieces of data rather than by a tyrannical clock that forces all of the millions of the circuits on a chip to march in unison. It overcomes all the disadvantages of a clocked circuit such a slow speed, high power consumption, high electromagnetic noise etc. For these reasons the clock less technology is considered as the technology, which is, going to drive majority of electronic chips in the coming years. 2 A BRIEF HISTORY Years 1940 1960 1989 1990 1994 1997 1998 2001 History Alan Turing and other early computer developers consider and reject asynchronous designs, choosing to use clocks to ensure more reliable operation. The idea of clockless chips all but disappears, kept alive only by a few esoteric papers from academics. Caltech computer scientist Alain Martin builds the first clockless microprocessor. Computer graphics pioneer Ivan Sutherland writes a paper interest in clockless chip technology. The university of Manchester (England) begins an asynchronous research group. The Manchester group, led by Steve Furber, produces an asynchronous chip compatible with cell phones made by ARM. Intel develops an asynchronous, Pentium compatible test chip that runs three times as fast on half the power, as its synchronous equivalent. The device never makes it out of the lab. Philips introduces a commercial clockless chip, the first to market, which lets the companys pagers last nearly twice as long on the same battery power. Intel introduces the Pentium 4 microprocessor, which incorporates some clockless elements.

INTRODUCTION TO CONCEPT OF CLOCKS The clock is a tiny crystal oscillator that resides in the heart of every microprocessor chip. The clock sets the basic rhythm used throughout the machine. Crystals which tick up to 2 billion times each second in the fastest of todays desktop personal computers, dictate the timing of every circuit in every one of the chips that add, subtract, divide, multiply and move the ones and zeros that are the basic stuff of the information age. Computer chips of today are synchronous: they contain a main central clock which controls the timing of the entire chips and samples data in the registers at precisely timed intervals. One advantage of central clock is that, the clock signals to the devices of the chip when to input or output. This functionality of the synchronous design makes designing the chip much easier. There are problems that go along with the clock, however. Clock speeds are now in the gigahertz range and there is not much room for speedup before physical realities start to complicate things. With a gigahertz clock powering a chip, signals barely have enough time to make it across the chip before the next clock tick. At this point, speedup up the clock frequency could become disastrous. This is when a chip that is not constricted by clock speeds could become very valuable.

WORKING OF A SYNCHRONOUS CIRCUIT

This is the working model of a particular synchronous circuit. A synchronous circuit looks for a particular signal of the clock. In this case, the circuit is looking for the leading edge of the clock pulse. As we see in the figure, all actions in this circuit take place only on the leading edge of the clock cycle. Especially when transferring the data on to the registers the computations settle down and wait for the next leading edge of the clock to occur. Then only the data will be transferred to the next register. The figure gives a clear idea of how conventional chips operate under the control of a central clock, which samples data in the registers at precisely timed intervals. The only thing the designers have to think about is how to complete one operation during a single tick of the clock. It is extremely important to design the circuits in such a fashion that all the computations must settle down and be ready for the next logical operation before the next clock tick. 5 PROBLEMS OF SYNCHRONOUS CIRCUITS

5.1

LOW SPEED: One problem is speed. A chip can only work as fast as its slowest component. Therefore, if one part of the chip is especially slow, the other parts of the chip are forced to sit idle. This wasted computing time is obviously detrimental to the speed of the chip.

5.2

LOW PERFOMANCE: New problems with speeding up a clocked chip are just around the corner. Clock frequencies are getting so fast that signals can barely cross the chip on one clock cycle. When we get to the point where the clock cannot drive the entire chip, we'll be forced to come up with a solution. One possible solution is a second clock, but this will incur overhead and power consumption, so this is a poor solution. It is also important to note that doubling the frequency of the clock does not double the chip speed, therefore blindly trying to increase chip speed by increasing frequency without considering other options is foolish.

5.3

HIGH POWER DISSIPATION: The other major problem with a clocked design is power consumption. The clock consumes more power than another component of the chip. The most disturbing thing about this is that the clock serves no direct computational use. A clock does not perform operations on information; it simply orchestrates the computational parts of the computer.

5.4

HIGH ELECTROMAGNETIC NOISE: Since clock itself is crystal oscillator it is then associated with electromagnetic waves. These waves produce electromagnetic noise due to oscillations. Noise will also be accompanied by emission spectra. The higher the speed of clock is the higher number of oscillations per second and this leak high value of electromagnetic noise and spectra emission. This is not a good sign for design of mobile devices too.

CONCEPT OF CLOCKLESS CHIPS The main concept behind a clockless design is evident from the name itself. That is, they dont have a global clock which synchronizes its actions. So there must be some control mechanism which should synchronize the components inside a clockless chip to ensure correct working of the chip. The clockless chips rely up on handshaking signals, handoff signals & sometimes a local clock to synchronize the actions. By throwing out the clock, chip makers will be able to escape from the problems of the synchronous circuits. Clockless chips draw power only when there is useful work to do, enabling a huge savings in battery-driven devices; an asynchronous-chip-based pager marketed by Philips Electronics, for example, runs almost twice as long as competitors' products, which use conventional clocked chips. Instead of the entire chip running at the speed of its slowest components, it can run at the average speed of all components. At both Intel and Sun, this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. Another advantage of clockless chips is that they give off very low levels of electromagnetic noise. The faster the clock, the more difficult it is to prevent a device from interfering with other devices; dispensing with the clock all but eliminates this problem.

WORKING OF ASYNCHRONOUS CIRCUIT Clockless (also called asynchronous, self timed or event driven) chips dispense with the timepiece. The figure below gives an idea of working of an asynchronous circuit. In this particular scheme (which is called a duel rail circuit which will be discussed later), data moves instead under the control of local "handshake" signals (lines below) that indicate when work has been completed and is ready for the next logic operation.

As we can see above there is the usual logical circuitry and instead of a clock signal which controls the circuit, there are two lines on the top and bottom. The wires are used to transfer the data bits and the control bits together. So there is no separate control signal going across the circuit. The control signal is encoded within the data that is being transferred. This control signals act as handshaking and handoff signals which indicates when the component is ready for the next logical operation. 8 TYPES OF IMPLEMENTATIONS There are mainly three kinds of implementations of an asynchronous circuit. They are the following.

8.1

BOUNDED DELAY METHOD: The simplest implementation of asynchronous design is the BoundedDelay method. This design is very similar to synchronous design; in Bounded-Delay design we assume that we know the largest amount of time for each component to perform its task. Knowing the bounds of the delay time allows for computations to be sped up.

8.2

DELAY INSENSITIVE METHOD: The Delay-Insensitive method, which is quite the opposite of Bounded-Delay, does not assume any bounds on time. As a result, handshaking is needed between components.

8.3

NULL CONVENTIONAL LOGIC: This convention uses a NULL state when data is in the reset phase, as opposed to DATA in the set phase. The theory behind NCL is simple. If a gate has any inputs that are NULL, then this gate has an output which is NULL. Once the gate gets all its inputs, that are all its inputs are DATA, then the output of the gate is DATA. In this way, the gates do not need to be clocked because they do their computation as soon as possible.

MERITS OF ASYNCHRONOUS CIRCUITS There are mainly three advantages of clockless design. They are

9.1 INCREASE IN SPEED: The first of these advantages is speed. Chips can run at the average speed
of all its components instead of the speed of the slowest component, as was the case with a clocked design. The transistors on an asynchronous chip can swap information independently, without needing to wait for everything else. At both Intel and Sun micro systems, this approach has led to prototype chips that run two to three times faster than comparable products using conventional circuitry. Therefore the speed of an asynchronous design is not limited by the size of the chip. An example of how much an asynchronous design can improve speed is the asynchronous Pentium designed by Intel in 1997 that runs three times as fast as the synchronous equivalent.

9.2 REDUCED POWER CONSUMPTION: Another crucial advantage of clockless chips is the reduction
in power consumption. The reason for this is that asynchronous chips use power only during computations, while a clocked circuit is always running. The Intel Pentium referred above ran three times faster than clocked equivalent with half the power.

9.3 LESS ELECTROMAGNETIC NOISE: The third advantage of the clockless design is that it produces
less electromagnetic noise which interferes with the working frequencies of other signals. 10 APPLICATIONS: Clockless design is inevitable in the future of chip design because of the two major advantages of speed and power consumption, we see these designs as listed below:

10.1

LABs: Many prototypes will be necessary to create reliable designs. Manufacturing techniques must also be improved so the chips can be mass-produced.

10.2

MOBILE ELECTRONICS: This is an ideal place to implement a clockless chip because of the minimal power consumption. Also, low levels of electromagnetic noise creates less interference; less interference is critical in designs with many components packed very tightly, as is the case with mobile electronics.

10.3

PERSONAL COMPUTERS: Clockless designs will occur here last because of the competitive PC market. It is essential in that market to create an efficient design that is reasonably priced. A manufacturing cost increase of a couple cents per chip can cause an entire line of computers to fail because of the large cost increase passed onto the customer. Therefore, the manufacturing process must be improved to create a reasonably priced chip.

10.4 ENCRYPTION DEVICES: The reason for this is there are no regularly timed signals for hackers to
look for. This becomes even more critical as computer all over the world become more closely connected and are sharing confidential material. They will be also used in smart cars as they provide excellent security. 11 LIMITATIONS OF ASYNCHRONOUS CIRCUITS:

11.1

DESIGN DIFFICULTIES: The primary drawback to asynchronous design is that it is hard. Control logic must operate in fundamental mode, or a close variant (like burst mode), and the synthesis formalisms are unfamiliar. Architectural design has all the same challenges that concurrent software has; researchers have yet to make concurrent software design a turnkey affair, despite decades of attention. And of course, there is the basic obstacle that asynchronous design techniques have been out of favor since the 1980s, and are therefore not typically taught in universities. If a microprocessor design company today wanted to use asynchronous logic, they would have to begin by training their engineering staff in the basics.

11.2

LACK OF GOOD TOOLS: The predominance of CAD tools oriented towards synchronous design is another chicken-and-egg problem. However, most circuit simulation techniques are independent of synchrony, and existing tools can be adapted for asynchronous use. Also, previous academic design efforts have produced the first sprinkling of a dedicated tool base.

11.3

TESTING DIFFICULTIES: Testing asynchronous circuits presents several new challenges. For example, a common technique in synchronous testing is to slow or stop the clock, to allow the logic functions to be observed at human speeds. However, gating the request and/or acknowledge signals is a possibility, and it is at least conceivable that dropping Vdd to near the threshold could provide a useful slowing effect (and possibly more useful, since some of the slow-transition effects are preserved, unlike clock dividing). Additionally, asynchronous circuits have timing requirements that are more constrained than synchronous circuits. Whereas the latter simply have to compute a valid result before the clock edge, asynchronous circuits may have minimum delays too; the prototype delay in a bounded-delay design is such a circuit. Finally, related to the design difficulties, is the testing of the possible interleaving scenarios, as in concurrent software. these possibilities. Asynchronous control circuitry must be designed to handle a variety of contingencies regarding timing, and the testing harness must be able to cause at least most of

12 CONCLUSION : As has been studied that implementation of clockless chip in asynchronous circuit has much great advantage over clocked chips. The obvious reasons for their super performance and average speed, low power consumption, less heat and noise generated are in great demand of the current market of electronic and computing world. This is a very new area of research and design and testing but if more scientists and engineers are dedicated to this, then for surety it the future technology for mobile electronic devices. 13 REFERENCES:

1 2 3 4

Scanning the Technology: Applications of Asynchronous Circuits C. H. (Kees) van Computers without clocks Ivan E Sutherland and Jo Ebergen Scientific American, Is it time for Clockless chips? David Geer published by IEEE Computer Society, Guest Editors Introduction: Clockless VLSI Systems Soha Hassoun, Yong-Bin

Berkel, Mark B. Josephs, and Steven M. Nowick proceedings of IEEE, December 1998. August 2002. March 2005. Kim and Fabrizio Lombardi copublished by IEEE CS and IEEE November December 2005. 5 6 It's Time for Clockless Chips Claire Tristram from MIT Technology October 2001 Old tricks for new chips Apr 19th 2001 From The Economist print edition

Reference: http://www.seminarprojects.com/Thread-a-seminar-report-on-clockless-chips#ixzz1br56li20