-- This is a 8 Bit Wide 16 Bytes Deep FIFO.

-- I have not synthesized but i feel that there should be no problem LIbrary IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity fifo is Port ( Clk : in std_logic; Reset : in std_logic; WriteEnable : in std_logic; ReadEnable : in std_logic; DataIn : in std_logic_vector(7 downto 0); DataOut : out std_logic_vector(7 downto 0); FifoEmpty : out std_logic; FifoFull : out std_logic ); END fifo;-- entity declarations ends Architecture A_fifo of fifo is Component Rams Port ( Writeen Wclk Datain Addr Dataout ); END Component; Signal ReadPointer : std_logic_vector(3 downto 0); Signal WritePointer : std_logic_vector(3 downto 0); Signal ByteCounter : std_logic_vector(4 downto 0); Signal Signal Signal Signal WriteEnable_s Addr_s FifoFull_s FifoEmpty_s : : : : std_logic; std_logic_vector(3 downto 0); std_logic; std_logic; : in std_logic; : in std_logic; : in std_logic_vector(7 downto 0); : in std_logic_vector(3 downto 0); : out std_logic_vector(7 downto 0)

Begin FifoRam : Rams Port map ( Writeen Wclk Datain Dataout Addr ); ReadWriteFifoOut : Process(Clk,Reset) Begin IF ( Reset = '1') then ReadPointer <= "0000"; WritePointer <= "0000"; => WriteEnable_s, => Clk, => DataIn, => DataOut, => Addr_s

ByteCounter <= "00000"; ELSIF(Clk'event and Clk = '1') then IF ( WriteEnable = '1' and FifoFull_s = '0' and ReadEnable = '0') then WritePointer <= WritePointer + 1; ByteCounter <= ByteCounter + 1; END IF; IF ( ReadEnable = '1' and FifoEmpty_s = '0' and WriteEnable = '0') then ReadPointer ByteCounter <= ReadPointer + 1; <= ByteCounter - 1; END IF; END IF; END process;-- ReadWriteFifo Process ends ------------------------------------------------------------ Combinatorial Logic ----------------------------------------------------------FifoEmpty_s <= '1' when ( ByteCounter = "0000") else '0'; FifoFull_s <= ByteCounter(4); FifoFull <= FifoFull_s; FifoEmpty <= FifoEmpty_s; WriteEnable_s <= '1' when ( WriteEnable = '1' and FifoFull_s = '0') else '0'; when ( WriteEnable = '1') else ReadPointer; -----------------------------------------------------------END A_fifo;--Architecture Ends The following xnf File was used for Memory LCANET,6 PROG, MEMGEN, 5.2.0, "14-deep by 8-wide SYNC_RAM macro called 'sramd_s'" PART, 4013EPQ160 PWR,0,GND SYM,BANK0-00,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<0> PIN,O,O,DATAOUT<0> END SYM,BANK0-01,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> Addr_s <= WritePointer

PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<1> PIN,O,O,DATAOUT<1> END SYM,BANK0-02,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<2> PIN,O,O,DATAOUT<2> END SYM,BANK0-03,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<3> PIN,O,O,DATAOUT<3> END SYM,BANK0-04,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<4> PIN,O,O,DATAOUT<4> END SYM,BANK0-05,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<5> PIN,O,O,DATAOUT<5> END SYM,BANK0-06,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0 PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<6> PIN,O,O,DATAOUT<6> END SYM,BANK0-07,RAMS,INIT=0000,=NEQGATES:61,LIBVER=2.0.0

PIN,A0,I,ADDR<0> PIN,A1,I,ADDR<1> PIN,A2,I,ADDR<2> PIN,A3,I,ADDR<3> PIN,WE,I,WRITEEN PIN,WCLK,I,WCLK PIN,D,I,DATAIN<7> PIN,O,O,DATAOUT<7> END EOF -- This entities are not tested ---Behavioral Code For RAM Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; Entity Rams is Port ( Writeen : in std_logic; Wclk : in std_logic; Datain : in std_logic_vector(7 downto 0); Dataout : out std_logic_vector(7 downto 0); Addr : in std_logic_vector(3 downto 0) ); END Rams;-- Entity Ends Architecture Behave of Rams is Type Mem is array ( 15 downto 0) of std_logic_vector( 7 downto 0); Signal Memory : Mem; Begin Write_Process : Process(Wclk) Begin if (Wclk'event and Wclk = '1') then if ( Writeen = '1') then Memory(Conv_Integer(Addr)) <= Datain; end if; end if; end process; -- Write Process Ends Dataout <= Memory(Conv_Integer(Addr)); End Behave;-- Architecture Ends

-- Simple generic RAM Model --- +-----------------------------+ -- | -- | Copyright 2008 DOULOS designer : JK | |

-- +-----------------------------+

library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.Numeric_Std.all;

entity sync_ram is port ( clock we : in : in std_logic; std_logic; std_logic_vector; std_logic_vector;

address : in datain : in

dataout : out std_logic_vector ); end entity sync_ram;

architecture RTL of sync_ram is

type ram_type is array (0 to (2**address'length)-1) of std_logic_vector(datain'range); signal ram : ram_type; signal read_address : std_logic_vector(address'range);

begin

RamProc: process(clock) is

begin if rising_edge(clock) then if we = '1' then ram(to_integer(unsigned(address))) <= datain; end if; read_address <= address; end if; end process RamProc;

dataout <= ram(to_integer(unsigned(read_address)));

end architecture RTL;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ram_example is port (Clk : in std_logic; address : in integer; we : in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0) ); end ram_example; architecture Behavioral of ram_example is --Declaration of type and signal of a 256 element RAM

--with each element being 8 bit wide. type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); signal ram : ram_t := (others => (others => '0')); begin --process for read and write operation. PROCESS(Clk) BEGIN if(rising_edge(Clk)) then if(we='1') then ram(address) <= data_i; end if; data_o <= ram(address); end if; END PROCESS; end Behavioral;

3 bit magnitude comparator library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity comparator is port( a,b : in unsigned(2 downto compared a_eq_b : out std_logic; a_le_b : out std_logic; a_gt_b : out std_logic ); end comparator; 0); --3 bit numbers to be

--a equals b --a less than b --a greater than b

architecture gate_level of comparator is signal temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9 : std_ logic := '0'; BEGIN temp1 <= not(a(2) xor b(2)); temp2 <= not(a(1) xor b(1)); temp3 <= not(a(0) xor b(0)); --XNOR gate with 2 inputs. --XNOR gate with 2 inputs. --XNOR gate with 2 inputs.

temp4 temp5 temp6 temp7 temp8 temp9

<= <= <= <= <= <=

(not (not (not a(2) a(1) a(0)

a(2)) and b(2); a(1)) and b(1); a(0)) and b(0); and (not b(2)); and (not b(1)); and (not b(0));

a_eq_b <= a_le_b <= ; --for a a_gt_b <= ; --for a

temp1 and temp2 and temp3; -- for a equals b. temp4 or (temp1 and temp5) or (temp1 and temp2 and temp6) less than b temp7 or (temp1 and temp8) or (temp1 and temp2 and temp9) greater than b

end gate_level;
The testbench code for testing the design is given below:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY tb IS END tb; ARCHITECTURE behavior OF tb IS --Inputs signal a : unsigned(2 downto 0) := (others => '0'); signal b : unsigned(2 downto 0) := (others => '0'); --Outputs signal a_eq_b : std_logic; signal a_le_b : std_logic; signal a_gt_b : std_logic; signal i,j : integer; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.comparator PORT MAP ( a => a, b => b, a_eq_b => a_eq_b, a_le_b => a_le_b, a_gt_b => a_gt_b ); -- Stimulus process stim_proc: process begin

for i in 0 to 8 loop for j in 0 to 8 loop a <= to_unsigned(i,3); --integer to unsigned type conversion b <= to_unsigned(j,3); wait for 10 ns; end loop; end loop; end process; END; -----------------------------------------------------------------------------------------------------------------------------------------Here is the code for 4 : 1 MUX using case statements.The module contains 4 single bit input lines and one 2 bit select input.The output is a single bit line.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity multiplexer4_1 is port ( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; sel : in std_logic_vector(1 downto 0); bitout : out std_logic ); end multiplexer4_1; architecture Behavioral of multiplexer4_1 is begin process(i0,i1,i2,i3,sel) begin case sel is when "00" => bitout <= i0; when "01" => bitout <= i1; when "10" => bitout <= i2; when others => bitout <= i3; end case; end process; end Behavioral;
The testbench code used for testing the code is given below:

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS SIGNAL i0,i1,i2,i3,bitout : std_logic:='0'; SIGNAL sel : std_logic_vector(1 downto 0):="00"; BEGIN UUT : entity work.multiplexer4_1 port map(i0,i1,i2,i3,sel,bitout); tb : PROCESS BEGIN i0<='1'; i1<='0'; i2<='1'; i3<='0'; sel <="00"; wait for 2 ns; sel <="01"; wait for 2 ns; sel <="10"; wait for 2 ns; sel <="11"; wait for 2 ns; --more input combinations can be given here. END PROCESS tb; END;
Here is the code for 4 :1 DEMUX using case statements.The module has 4 single bit output lines and one 2 bit select input.The input line is defined as a single bit line.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux1_4 is port ( out0 : out std_logic; --output bit out1 : out std_logic; --output bit out2 : out std_logic; --output bit out3 : out std_logic; --output bit sel : in std_logic_vector(1 downto 0); bitin : in std_logic --input bit ); end demux1_4; architecture Behavioral of demux1_4 is begin

process(bitin,sel) begin case sel is when "00" => out0 <= bitin; out1 <= when "01" => out1 <= bitin; out0 <= when "10" => out2 <= bitin; out0 <= when others => out3 <= bitin; out0 0'; end case; end process; end Behavioral;

'0'; out2 <= '0'; out2 <= '0'; out1 <= <= '0'; out1

'0'; out3 <='0'; '0'; out3 <='0'; '0'; out3 <='0'; <= '0'; out2 <='

The testbench code used for testing the code is given below:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS SIGNAL out0,out1,out2,out3,bitin : std_logic:='0'; SIGNAL sel : std_logic_vector(1 downto 0):="00"; BEGIN UUT : entity work.demux1_4 port map(out0,out1,out2,out3,sel,bitin); tb : PROCESS BEGIN bitin <= '1'; sel <="00"; wait for 2 ns; sel <="01"; wait for 2 ns; sel <="10"; wait for 2 ns; sel <="11"; wait for 2 ns; --more input combinations can be given here. END PROCESS tb; END;

When you declare a RAM in your code, XST(Xilinx synthesizer tool) may implement it as either block RAM or distributed RAM. But if you want, you can force the implementation style to use block RAM or distributed RAM resources. This is done using the ram_style constraint. See the following code to understand how it is done:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity ram_example is port (Clk : in std_logic; address : in integer; we : in std_logic; data_i : in std_logic_vector(7 downto 0); data_o : out std_logic_vector(7 downto 0) ); end ram_example; architecture Behavioral of ram_example is --Declaration of type and signal of a 256 element RAM --with each element being 8 bit wide. type ram_t is array (0 to 255) of std_logic_vector(7 downto 0); signal ram : ram_t := (others => (others => '0')); begin --process for read and write operation. PROCESS(Clk) BEGIN if(rising_edge(Clk)) then if(we='1') then ram(address) <= data_i; end if; data_o <= ram(address); end if; END PROCESS; end Behavioral;

its a vhdl code for ram u may try dis sram -------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SRAM is generic( width: integer:=16; depth: integer:=16; addr: integer:=4); port ( clock: in std_logic;

enableram: in std_logic; readram: in std_logic; writeram: in std_logic; --Read_Addr: in std_logic_vector(addr-1 downto 0); --Write_Addr: out std_logic_vector(addr-1 downto 0); data_in: in std_logic_vector(width-1 downto 0); data_out: out std_logic_vector(width-1 downto 0)); end SRAM; -------------------------------------------------------------architecture behav of SRAM is -- use array to define the bunch of internal temparary signals type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; signal count1: std_logic_vector(15 downto 0):="0000000000000000"; signal write_addr: std_logic_vector(addr-1 downto 0); signal read_addr: std_logic_vector(addr-1 downto 0); begin -- Read Functional Section process(clock, readram,enableram) begin if (clock'event and clock='1') then count1<= count1+1; if (enableram='1') then if (readram='1') then if (count1="0000000000110001") then --49th clock pulse read_addr<="00000000"; -- buildin function conv_integer change the type -- from std_logic_vector to integer data_out <= tmp_ram(conv_integer(read_addr)); elsif (count1="0000000000110010") then --50th clock pulse read_addr<="00000001"; data_out <= tmp_ram(conv_integer(read_addr)); elsif (count1="0000000000110011") then --51th clock pulse read_addr<="00000010"; data_out <= tmp_ram(conv_integer(read_addr)); else data_out <= (data_out'range => 'Z'); end if; end if; end if; end if; end process; -- Write Functional Section process(clock, enableram,writeram) begin if (clock'event and clock='1') then count1<=count1+1;

if (enableram='1') then if (writeram='1') then if (count1="0000000000001000") then --16 th clock pulse write_addr<="00000000"; tmp_ram(conv_integer(write_addr)) <= data_in; elsif (count1="00000000000100000") then --32th clock pulse write_addr<="00000001"; tmp_ram(conv_integer(write_addr)) <= data_in; elsif (count1="00000000000110000") then --48st clock pulse write_addr<="00000010"; tmp_ram(conv_integer(write_addr)) <= data_in; end if; end if; end if; end if; end process; end behav;

-- 2:4 Decoder (ESD figure 2.5) -- by Weijun Zhang, 04/2001 --- decoder is a kind of inverse process -- of multiplexor ------------------------------------------------library ieee; use ieee.std_logic_1164.all; ------------------------------------------------entity DECODER is port( I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end DECODER; ------------------------------------------------architecture behv of DECODER is begin -- process statement process (I) begin -- use case statement case I is when "00" => O when "01" => O when "10" => O when "11" => O when others => end case; <= "0001"; <= "0010"; <= "0100"; <= "1000"; O <= "XXXX";

end process; end behv; architecture when_else of DECODER is begin -- use when..else statement O <= "0001" when "0010" when "0100" when "1000" when "XXXX"; I I I I = = = = "00" "01" "10" "11" else else else else

end when_else;

-- VHDL code for n-bit adder (ESD figure 2.5) -- by Weujun Zhang, 04/2001 --- function of adder: -- A plus B to get n-bit sum and 1 bit carry -- we may use generic statement to set the parameter -- n of the adder. -------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------entity ADDER is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); carry: out std_logic; sum: out std_logic_vector(n-1 downto 0) ); end ADDER; -------------------------------------------------------architecture behv of ADDER is -- define a temparary signal to store the result signal result: std_logic_vector(n downto 0); begin

-- the 3rd bit should be carry result <= ('0' & A)+('0' & B); sum <= result(n-1 downto 0); carry <= result(n); end behv;

-- n-bit Comparator (ESD book figure 2.5) -- by Weijun Zhang, 04/2001 --- this simple comparator has two n-bit inputs & -- three 1-bit outputs --------------------------------------------------library ieee; use ieee.std_logic_1164.all; --------------------------------------------------entity Comparator is generic(n: natural :=2); port( A: in std_logic_vector(n-1 downto 0); B: in std_logic_vector(n-1 downto 0); less: out std_logic; equal: out std_logic; greater: out std_logic ); end Comparator; --------------------------------------------------architecture behv of Comparator is begin process(A,B) begin if (A<B) then less <= '1'; equal <= '0'; greater <= '0'; elsif (A=B) then less <= '0'; equal <= '1'; greater <= '0'; else less <= '0'; equal <= '0'; greater <= '1'; end if; end process; end behv;

-- Simple ALU Module (ESD book Figure 2.5) -- by Weijun Zhang, 04/2001 --- ALU stands for arithmatic logic unit. -- It perform multiple operations according to -- the control bits. -- we use 2's complement subraction in this example -- two 2-bit inputs & carry-bit ignored --------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; --------------------------------------------------entity ALU is port( A: B: Sel: Res: in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); in std_logic_vector(1 downto 0); out std_logic_vector(1 downto 0)

); end ALU; --------------------------------------------------architecture behv of ALU is begin process(A,B,Sel) begin -- use case statement to achieve -- different operations of ALU case Sel is when "00" => Res <= A + B; when "01" => Res <= A + (not B) + 1; when "10" => Res <= A and B; when "11" => Res <= A or B; when others => Res <= "XX"; end case; end process; end behv;

-- Example of doing multiplication showing -- (1) how to use variable with in process -- (2) how to use for loop statement -- (3) algorithm of multiplication --- by Weijun Zhang, 05/2001 -------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -- two 4-bit inputs and one 8-bit outputs entity multiplier is port( num1, num2: in std_logic_vector(1 downto 0); product: out std_logic_vector(3 downto 0) ); end multiplier; architecture behv of multiplier is begin process(num1, num2) variable num1_reg: std_logic_vector(2 downto 0); variable product_reg: std_logic_vector(5 downto 0); begin num1_reg := '0' & num1; product_reg := "0000" & num2; -- use variables doing computation -- algorithm is to repeat shifting/adding for i in 1 to 3 loop if product_reg(0)='1' then product_reg(5 downto 3) := product_reg(5 downto 3) + num1_reg(2 downto 0); end if; product_reg(5 downto 0) := '0' & product_reg(5 downto 1); end loop; -- assign the result of computation back to output signal product <= product_reg(3 downto 0); end process; end behv;

-- Simple D Latch (ESD book Chapter 2.3.1) -- by Weijun Zhang, 04/2001 --

-- latch is simply controlled by enable bit -- but has nothing to do with clock sigal -- notice this difference from flip-flops -------------------------------------------library ieee ; use ieee.std_logic_1164.all; -------------------------------------------entity D_latch is port( data_in: enable: data_out: ); end D_latch; in std_logic; in std_logic; out std_logic

-------------------------------------------architecture behv of D_latch is begin -- compare this to D flipflop process(data_in, enable) begin if (enable='1') then -- no clock signal here data_out <= data_in; end if; end process; end behv;

-- D Flip-Flop (ESD book Chapter 2.3.1) -- by Weijun Zhang, 04/2001 --- Flip-flop is the basic component in -- sequential logic design -- we assign input signal to the output -- at the clock rising edge --------------------------------------------library ieee ; use ieee.std_logic_1164.all; use work.all; --------------------------------------------entity dff is port( data_in: clock: data_out: in std_logic; in std_logic; out std_logic

); end dff; ---------------------------------------------architecture behv of dff is begin process(data_in, clock) begin -- clock rising edge if (clock='1' and clock'event) then data_out <= data_in; end if; end process; end behv;

-- JK Flip-Flop with reset -- (ESD book Chapter 2.3.1) -- by Weijun Zhang, 04/2001 --- the description of JK Flip-Flop is based -- on functional truth table -- concurrent statement and signal assignment -- are using in this example ---------------------------------------------library ieee; use ieee.std_logic_1164.all; ---------------------------------------------entity JK_FF is port ( clock: J, K: reset: Q, Qbar: ); end JK_FF; in std_logic; in std_logic; in std_logic; out std_logic

----------------------------------------------architecture behv of JK_FF is -- define the useful signals here signal state: std_logic; signal input: std_logic_vector(1 downto 0); begin

-- combine inputs into vector input <= J & K; p: process(clock, reset) is begin if (reset='1') then state <= '0'; elsif (rising_edge(clock)) then -- compare to the truth table case (input) is when "11" => state <= not state; when "10" => state <= '1'; when "01" => state <= '0'; when others => null; end case; end if; end process; -- concurrent statements Q <= state; Qbar <= not state; end behv;

-- n-bit Register (ESD book figure 2.6) -- by Weijun Zhang, 04/2001 --- KEY WORD: concurrent, generic and range --------------------------------------------------library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; --------------------------------------------------entity reg is generic(n: natural :=2); port( I: in std_logic_vector(n-1 downto 0); clock: in std_logic; load: in std_logic; clear: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end reg; ----------------------------------------------------

architecture behv of reg is signal Q_tmp: std_logic_vector(n-1 downto 0); begin process(I, clock, load, clear) begin if clear = '0' then -- use 'range in signal assigment Q_tmp <= (Q_tmp'range => '0'); elsif (clock='1' and clock'event) then if load = '1' then Q_tmp <= I; end if; end if; end process; -- concurrent statement Q <= Q_tmp; end behv;

-- 3-bit Shift-Register/Shifter -- (ESD book figure 2.6) -- by Weijun Zhang, 04/2001 --- reset is ignored according to the figure --------------------------------------------------library ieee ; use ieee.std_logic_1164.all; --------------------------------------------------entity shift_reg is port( I: clock: shift: Q: ); end shift_reg; in std_logic; in std_logic; in std_logic; out std_logic

--------------------------------------------------architecture behv of shift_reg is -- initialize the declared signal signal S: std_logic_vector(2 downto 0):="111"; begin

process(I, clock, shift, S) begin -- everything happens upon the clock changing if clock'event and clock='1' then if shift = '1' then S <= I & S(2 downto 1); end if; end if; end process; -- concurrent assignment Q <= S(0); end behv;

-- VHDL code for n-bit counter (ESD figure 2.6) -- by Weijun Zhang, 04/2001 --- this is the behavior description of n-bit counter -- another way can be used is FSM model. ---------------------------------------------------library ieee ; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; ---------------------------------------------------entity counter is generic(n: natural :=2); port( clock: in std_logic; clear: in std_logic; count: in std_logic; Q: out std_logic_vector(n-1 downto 0) ); end counter; ---------------------------------------------------architecture behv of counter is signal Pre_Q: std_logic_vector(n-1 downto 0); begin -- behavior describe the counter process(clock, count, clear) begin if clear = '1' then Pre_Q <= Pre_Q - Pre_Q; elsif (clock='1' and clock'event) then

if count = '1' then Pre_Q <= Pre_Q + 1; end if; end if; end process; -- concurrent assignment statement Q <= Pre_Q; end behv;

-- a simple 4*4 RAM module (ESD book Chapter 5) -- by Weijun Zhang --- KEYWORD: array, concurrent processes, generic, conv_integer -------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------------entity SRAM is generic( width: depth: addr: port( Clock: Enable: Read: Write: Read_Addr: Write_Addr: Data_in: Data_out: ); end SRAM; integer:=4; integer:=4; integer:=2); in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(addr-1 downto 0); in std_logic_vector(addr-1 downto 0); in std_logic_vector(width-1 downto 0); out std_logic_vector(width-1 downto 0)

-------------------------------------------------------------architecture behav of SRAM is -- use array to define the bunch of internal temparary signals type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0); signal tmp_ram: ram_type; begin -- Read Functional Section process(Clock, Read) begin if (Clock'event and Clock='1') then

if Enable='1' then if Read='1' then -- buildin function conv_integer change the type -- from std_logic_vector to integer Data_out <= tmp_ram(conv_integer(Read_Addr)); else Data_out <= (Data_out'range => 'Z'); end if; end if; end if; end process; -- Write Functional Section process(Clock, Write) begin if (Clock'event and Clock='1') then if Enable='1' then if Write='1' then tmp_ram(conv_integer(Write_Addr)) <= Data_in; end if; end if; end if; end process; end behav;

-- 32*8 ROM module (ESD Book Chapter 5) -- by Weijun Zhang, 04/2001 --- ROM model has predefined content for read only purpose -------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ROM is port( Clock : Reset : Enable : Read : Address : Data_out: ); end ROM; in std_logic; in std_logic; in std_logic; in std_logic; in std_logic_vector(4 downto 0); out std_logic_vector(7 downto 0)

-------------------------------------------------------------architecture Behav of ROM is type ROM_Array is array (0 to 31) of std_logic_vector(7 downto 0); constant Content: ROM_Array := (

0 => "00000001", 1 => "00000010", 2 => "00000011", 3 => "00000100", 4 => "00000101", 5 => "00000110", 6 => "00000111", 7 => "00001000", 8 => "00001001", 9 => "00001010", 10 => "00001011", 11 => "00001100", 12 => "00001101", 13 => "00001110", 14 => "00001111", OTHERS => "11111111" );

-- Suppose ROM has -- prestored value -- like this table --------------

begin process(Clock, Reset, Read, Address) begin if( Reset = '1' ) then Data_out <= "ZZZZZZZZ"; elsif( Clock'event and Clock = '1' ) then if Enable = '1' then if( Read = '1' ) then Data_out <= Content(conv_integer(Address)); else Data_out <= "ZZZZZZZZ"; end if; end if; end if; end process; end Behav;

-- GCD design using FSMD (ESD book Figure 2.9) -- Weijun Zhang, 04/2001 --- GCD algorithm behavior modeling (GCD.vhd) -- the calculator has two 4-bit inputs and one output --- NOTE: idle state required to obtain -- the correct synthesis results -------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.all; -------------------------------------------------------------entity gcd is port( clk: in std_logic;

rst: go_i: x_i: y_i: d_o: ); end gcd;

in std_logic; in std_logic; in unsigned(3 downto 0); in unsigned(3 downto 0); out unsigned(3 downto 0)

-------------------------------------------------------------architecture FSMD of gcd is begin process(rst, clk) -- define states using variable type S_Type is (ST0, ST1, ST2); variable State: S_Type := ST0 ; variable Data_X, Data_Y: unsigned(3 downto 0); begin if (rst='1') then -- initialization d_o <= "0000"; State := ST0; elsif (clk'event and clk='1') then case State is when ST0 => -- starting if (go_i='1') then Data_X := x_i; Data_Y := y_i; State := ST1; else State := ST0; end if; when ST1 => -- idle state State := ST2; when ST2 => -- computation if (Data_X/=Data_Y) then if (Data_X<Data_Y) then Data_Y := Data_Y - Data_X; else Data_X := Data_X - Data_Y; end if; State := ST1; else d_o <=Data_X; -- done State := ST0; end if; when others => -- go back d_o <= "ZZZZ"; State := ST0; end case; end if; end process;

end FSMD; The below code help you to impliment multiport RAM using VHDL LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY au3_ram48x10_2 IS GENERIC ( ADDRESS_WIDTH : integer := 6; DATA_WIDTH : integer := 10) ; PORT( reset : IN std_logic; clk_311mhz : IN std_logic; enable : IN std_logic; wadd : IN std_logic_vector(5 downto 0); radda : IN std_logic_vector(5 downto 0); raddb : IN std_logic_vector(5 downto 0); data_in : IN std_logic_vector(9 downto 0); data_outa : OUT std_logic_vector(9 downto 0) ; data_outb : OUT std_logic_vector(9 downto 0) ); END au3_ram48x10_2 ; ARCHITECTURE rtl OF au3_ram48x10_2 IS TYPE RAM IS ARRAY(0 TO 2 ** ADDRESS_WIDTH - 1) OF std_logic_vector(DATA_WIDTH - 1 DOWNTO 0); SIGNAL ram_block : RAM; BEGIN PROCESS (clk_311mhz) BEGIN IF (clk_311mhz'event AND clk_311mhz = '1') THEN IF (enable = '1') THEN ram_block(to_integer(unsigned(wadd))) <= data_in; END IF; IF(reset = '1') THEN data_outa <= (others => '0'); data_outb <= (others => '0'); ELSE data_outa <= ram_block(to_integer(unsigned(radda))); data_outb <= ram_block(to_integer(unsigned(raddb))); END IF; END IF ; END PROCESS; END rtl;
library ieee; use ieee.std_logic_1164.all; entity serial_ram is

generic ( n : integer := 16 ); port ( data : in std_logic; clk : in std_logic; en_write : in std_logic; en_read : in std_logic; q: out std_logic ); end; architecture behavioral of serial_ram is signal memo : std_logic_vector(n-1 downto 0); begin write_data : process(clk,en_write) variable i : integer := 0; begin if (rising_edge(clk) and en_write = '1') then memo(i) <= data; i := i+1; end if; if (i=n) then i := 0; end if; end process; read_data : process(clk,en_read) variable k : integer := 0; begin if (rising_edge(clk) and en_read = '1') then q <= memo(k); k := k+1; end if; if (k=n) then k := 0; end if; end process; end behavioral;

Here is the code for 4 bit comparator using if .. elsif ... else statements.The module has two 4-bit inputs which has to be compared, and three 1-bit output lines.One of these output lines goes high depending upon whether the first number is equal to,less or greater than the second number.

--libraries to be used are specified here library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity compare is port( num1 : in std_logic_vector(3 downto 0); --input 1 num2 : in std_logic_vector(3 downto 0); --input 2 less : out std_logic; -- indicates first

number is small equal : greater : is bigger ); end compare;

out std_logic; -- both are equal out std_logic -- indicates first number

--architecture of entity architecture Behavioral of compare is begin process(num1,num2) begin -- process starts with a 'begin' statement if (num1 > num2 ) then --checking whether num1 is greater than num2 less <= '0'; equal <= '0'; greater <= '1'; elsif (num1 < num2) then --checking whether num1 is less than num2 less <= '1'; equal <= '0'; greater <= '0'; else --checking whether num1 is equal to num2 less <= '0'; equal <= '1'; greater <= '0'; end if; end process; -- process ends with a 'end process' statement end Behavioral;
The test bench program used for testing the design is given below:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --this is how entity for your test bench code has to be declared. entity testbench is end testbench; architecture behavior of testbench is --signal declarations. signal num1,num2 : std_logic_vector(3 downto 0) :=(others => '0'); signal less,equal,greater : std_logic:='0'; begin --entity instantiation

UUT : entity work.compare port map(num1,num2,less,equal,greater); --definition of simulation process tb : process begin num1<="0010"; --num1 =2 num2<="1001"; --num2 =9 wait for 2 ns; num1<="1001"; --num1 =9 num2<="0010"; --num2 =2 wait for 2 ns; num1<="1010"; --num1 =10 num2<="1010"; --num2 =10 --more input combinations can be given here. wait; end process tb; end;

Here is the code for 4 bit Ripple Carry Adder using basic logic gates such as AND,XOR,OR etc.The module has two 4-bit inputs which has to be added, and one 4-bit output which is the sum of the given numbers.Another output bit indicates whether there is a overflow in the addition,that means whether a carry is generated or not.

--libraries to be used are specified here library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity rc_adder is port( num1 : in std_logic_vector(3 downto 0); --4 bit input 1 num2 : in std_logic_vector(3 downto 0); -- 4 bit input 2 sum : out std_logic_vector(3 downto 0); -- 4 bit sum carry : out std_logic -- carry out. ); end rc_adder; --architecture of entity architecture Behavioral of rc_adder is --temporary signal declarations(for intermediate carry's). signal c0,c1,c2,c3 : std_logic := '0';

begin --first full adder sum(0) <= num1(0) xor num2(0); --sum calculation c0 <= num1(0) and num2(0); --carry calculation --second full adder sum(1) <= num1(1) xor num2(1) xor c0; c1 <= (num1(1) and num2(1)) or (num1(1) and c0) or (num2(1) and c0) ; --third full adder sum(2) <= num1(2) xor num2(2) xor c1; c2 <= (num1(2) and num2(2)) or (num1(2) and c1) or (num2(2) and c1) ; --fourth(final) full adder sum(3) <= num1(3) xor num2(3) xor c2; c3 <= (num1(3) and num2(3)) or (num1(3) and c2) or (num2(3) and c2) ; --final carry assignment carry <= c3; end Behavioral;
The test bench program used for testing the design is given below:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --this is how entity for your test bench code has to be declared. entity testbench is end testbench; architecture behavior of testbench is --signal declarations. signal num1,num2,sum : std_logic_vector(3 downto 0) :=(others => '0 '); signal carry : std_logic:='0'; begin --entity instantiation UUT : entity work.rc_adder port map(num1,num2,sum,carry); --definition of simulation process tb : process begin num1<="0010"; --num1 =2 num2<="1001"; --num2 =9 wait for 2 ns;

num1<="1010"; --num1 =10 num2<="0011"; --num2 =3 wait for 2 ns; num1<="1000"; --num1 =8 num2<="0101"; --num2 =5 wait for 2 ns; num1<="1010"; --num1 =10 num2<="0110"; --num2 =6 --more input combinations can be given here. wait; end process tb; end;
Here is the code for 3 : 8 Decoder using basic logic gates such as AND,NOT,OR etc.The module has one 3-bit input which is decoded as a 8-bit output.

--libraries to be used are specified here library IEEE; use IEEE.STD_LOGIC_1164.ALL; --entity declaration with port definitions entity decoder is port( input : in std_logic_vector(2 downto 0); --3 bit input output : out std_logic_vector(7 downto 0) -- 8 bit ouput ); end decoder; --architecture of entity architecture Behavioral of decoder is begin output(0) output(1) output(2) output(3) output(4) output(5) output(6) output(7) <= <= <= <= <= <= <= <= (not input(2)) and (not input(1)) and (not input(0)); (not input(2)) and (not input(1)) and input(0); (not input(2)) and input(1) and (not input(0)); (not input(2)) and input(1) and input(0); input(2) and (not input(1)) and (not input(0)); input(2) and (not input(1)) and input(0); input(2) and input(1) and (not input(0)); input(2) and input(1) and input(0);

end Behavioral;
The test bench program used for testing the design is given below:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; --this is how entity for your test bench code has to be declared. entity testbench is end testbench; architecture behavior of testbench is --signal declarations. signal input : std_logic_vector(2 downto 0) :=(others => '0'); signal output : std_logic_vector(7 downto 0) :=(others => '0'); begin --entity instantiation UUT : entity work.decoder port map(input,output); --definition of simulation process tb : process begin input<="000"; --input = 0. wait for 2 ns; input<="001"; --input = 1. wait for 2 ns; input<="010"; --input = 2. wait for 2 ns; input<="011"; --input = 3. wait for 2 ns; input<="100"; --input = 4. wait for 2 ns; input<="101"; --input = 5. wait for 2 ns; input<="110"; --input = 6. wait for 2 ns; input<="111"; --input = 7. wait; end process tb; end;

Here is a program for BCD to 7-segment display decoder. The module takes 4 bit BCD as input and outputs 7 bit decoded output for driving the display unit.A seven segment display can be used to display decimal digits.They have LED or LCD elements which becomes active when the input is zero.The figure shows how different digits are displayed:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is port ( clk : in std_logic; bcd : in std_logic_vector(3 downto 0); --BCD input segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output. ); end test; --'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7. architecture Behavioral of test is begin process (clk,bcd) BEGIN if (clk'event and clk='1') then case bcd is when "0000"=> segment7 <="0000001"; -- '0' when "0001"=> segment7 <="1001111"; -- '1' when "0010"=> segment7 <="0010010"; -- '2' when "0011"=> segment7 <="0000110"; -- '3' when "0100"=> segment7 <="1001100"; -- '4' when "0101"=> segment7 <="0100100"; -- '5' when "0110"=> segment7 <="0100000"; -- '6' when "0111"=> segment7 <="0001111"; -- '7' when "1000"=> segment7 <="0000000"; -- '8' when "1001"=> segment7 <="0000100"; -- '9' --nothing is displayed when a number more than 9 is given as input. when others=> segment7 <="1111111"; end case;

end if; end process; end Behavioral;

If you want a decimal number to be displayed using this code then convert the corresponding code into BCD and then instantiate this module for each digit of the BCD code. Here is a sample test bench code for this module:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; ENTITY test_tb IS END test_tb; ARCHITECTURE behavior OF test_tb IS signal clk : std_logic := '0'; signal bcd : std_logic_vector(3 downto 0) := (others => '0'); signal segment7 : std_logic_vector(6 downto 0); constant clk_period : time := 1 ns; BEGIN uut: entity work.test PORT MAP (clk,bcd,segment7); clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; stim_proc: process begin for i in 0 to 9 loop bcd <= conv_std_logic_vector(i,4); wait for 2 ns; end loop; end process; END;

Most of the modern communication protocols use some error detection algorithms. Cyclic Redundancy Check, or CRC, is the most popular one among these. CRC properties are defined by the generator polynomial length and coefficients. The protocol specification usually defines CRC in hex or polynomial notation. For example, CRC-8 used in ATM HEC field is represented as 0x07 in hex notation or as G(X)=X^8 + X^2 + X^1 +1. in the polynomial notation.The code given below is capable of computing ,CRC-8 for 32 bit input.The module need 32 clock cycles for the computation.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity crc32_8 is port ( clk : in std_logic; data_in : in std_logic_vector(31 downto 0); crcout : out std_logic_vector(7 downto 0) ); end crc32_8; architecture Behavioral of crc32_8 is signal crc_temp : std_logic_vector(7 downto 0) := "00000000"; signal counter1 : std_logic_vector(5 downto 0):="000000"; signal dtemp : std_logic_vector(31 downto 0):=(others => '0'); begin dtemp <= data_in; process(data_in,clk) begin if(data_in /= "00000000000000000000000000000000") then if(clk'event and clk='1') then --CRC calculation. Function used is : X^8 + X^2 + X^1 +1. --Edit the next 8 lines to compute a different CRC function. crc_temp(0) <= data_in(31conv_integer(counter1(4 downto 0))) xor crc_temp(7); crc_temp(1) <= data_in(31conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(0) ; crc_temp(2) <= data_in(31conv_integer(counter1(4 downto 0))) xor crc_temp(7) xor crc_temp(1) ; crc_temp(3) <= crc_temp(2); crc_temp(4) <= crc_temp(3); crc_temp(5) <= crc_temp(4); crc_temp(6) <= crc_temp(5); crc_temp(7) <= crc_temp(6); --CRC calculation is finished here. --counter increment. counter1 <= counter1 + '1'; end if; if(counter1 ="100000") then for 8 times. crcout <= crc_temp; crc_temp <="00000000"; counter1 <= "000000"; --counter for doing the CRC operation

else crcout <= "00000000"; --CRC output is zero during idle time. end if; else --CRC output is zero when input is not given or input is zero crcout <= "00000000"; crc_temp <="00000000"; counter1 <= "000000"; end if; end process; end Behavioral;

Here is a basic model of FIFO(first in first out) queue. I have made some assumptions about the operation of this FIFO.I have assumed that my writing speed is faster than my reading speed of the queue.The comments are provided where ever needed.The size of the FIFO is 256 * 8 bit.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fifo is port ( clk : in std_logic; enr : in std_logic; --enable read,should be '0' when not in use. enw : in std_logic; --enable write,should be '0' when not in use. dataout : out std_logic_vector(7 downto 0); --output data datain : in std_logic_vector (7 downto 0); --input data empty : out std_logic; --set as '1' when the queue is empty full : out std_logic --set as '1' when the queue is full ); end fifo; architecture Behavioral of fifo is type memory_type is array (0 to 255) of std_logic_vector(7 downto 0 ); signal memory : memory_type :=(others => (others => '0')); -memory for queue. signal readptr,writeptr : std_logic_vector(7 downto 0) :="00000000" ; --read and write pointers. begin process(clk)

begin if(clk'event and clk='1' and enr ='1') then dataout <= memory(conv_integer(readptr)); error <= '0'; readptr <= readptr + '1'; --points to next address. end if; if(clk'event and clk='1' and enw ='1') then memory(conv_integer(writeptr)) <= datain; writeptr <= writeptr + '1'; --points to next address. end if; if(readptr = "11111111") then --resetting read pointer. readptr <= "00000000"; end if; if(writeptr = "11111111") then --checking whether queue is full or not full <='1'; writeptr <= "00000000"; else full <='0'; end if; if(writeptr = "00000000") then --checking whether queue is empty or not empty <='1'; else empty <='0'; end if; end process; end Behavioral;
I have written a function for division of variables in VHDL.The function is based on "Restoring Division algorithm".You can learn more about the algorithm here.The function takes two unsigned numbers(dividend and divisor) of the same size and returns the quotient,which is also of unsigned type with the same size.The function is a generalized one and can be used for any size of inputs.

function variable variable variable variable

divide (a : UNSIGNED; b : UNSIGNED) return UNSIGNED is a1 : unsigned(a'length-1 downto 0):=a; b1 : unsigned(b'length-1 downto 0):=b; p1 : unsigned(b'length downto 0):= (others => '0'); i : integer:=0;

begin for i in 0 to b'length-1 loop p1(b'length-1 downto 1) := p1(b'length-2 downto 0); p1(0) := a1(a'length-1); a1(a'length-1 downto 1) := a1(a'length-2 downto 0); p1 := p1-b1; if(p1(b'length-1) ='1') then a1(0) :='0'; p1 := p1+b1;

else a1(0) :='1'; end if; end loop; return a1; end divide;

I have written a function for finding the square root of a unsigned number in VHDL.The function is based on "Non-Restoring Square Root algorithm".You can learn more about the algorithm from this paper.The function takes one unsigned number,which is 32 bit in size and returns the square root,which is also of unsigned type with 15 bit size.The block diagram of the algorithm is given below:

Here D is the unsigned input number.R is the remainder of the operation for non-perfect squares. Q contains the square root of 'D'. The function is given below:

library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; -- for UNSIGNED function variable variable variable input to variable sqrt ( d : UNSIGNED ) return UNSIGNED is a : unsigned(31 downto 0):=d; --original input. q : unsigned(15 downto 0):=(others => '0'); --result. left,right,r : unsigned(17 downto 0):=(others => '0'); adder/sub.r-remainder. i : integer:=0;

--

begin for i in 0 to 15 loop

right(0):='1'; right(1):=r(17); right(17 downto 2):=q; left(1 downto 0):=a(31 downto 30); left(17 downto 2):=r(15 downto 0); a(31 downto 2):=a(29 downto 0); --shifting by 2 bit. if ( r(17) = '1') then r := left + right; else r := left - right; end if; q(15 downto 1) := q(14 downto 0); q(0) := not r(17); end loop; return q; end sqrt;
The function can be used as follows in your main module:

--An example of how to use the function. signal a : unsigned(31 downto 0) :="0000000000000000000000000011001 0"; --50 signal b : unsigned(15 downto 0) :=(others => '0'); b <= sqrt ( a ); --function is "called" here. --b will contain the value "00000111" ( equals to 7) once the operation is done.

Here is a function for doing matrix multiplication in VHDL. For storing matrix elements I have declared the following data types:

type type type type type type

t11 is array (0 to numcols1-1) of unsigned(15 downto 0); t1 is array (0 to numrows1-1) of t11; t22 is array (0 to numcols2-1) of unsigned(15 downto 0); t2 is array (0 to numrows2-1) of t22; t33 is array (0 to numcols3-1) of unsigned(31 downto 0); t3 is array (0 to numrows3-1) of t33;

Depending upon the size of your matrix you have to set the values numcols1,numcols2,numcols3,numrows1,numrows2,numrows3 etc.Here for valid matrix multiplication, numcols1 = numrows2. For the resultant matrix, numrows3 = numrows1 and numcols3 = numcols2. The function is given below:

function matmul ( a : t1; b:t2 ) return t3 is variable i,j,k : integer:=0; variable prod : t3:=(others => (others => (others => '0'))); begin for i in 0 to numrows1-1 loop

for j in 0 to numcols2-1 loop for k in 0 to numcols1-1 loop prod(i)(j) := prod(i)(j) + (a(i)(k) * b(k)(j)); end loop; end loop; end loop; return prod; end matmul;
In the above function replace the names numrows1,numcols1,numcols2 etc with appropriate values. For example if I want to multiply a 4*3 matrix with 3*5 matrix then : numcols1=3, numcols2 =5 ,numcols3 = 5,numrows1=4 ,numrows2 =3 and numrows3=4. So the type declarations will look like this:

type type type type type type

t11 is array (0 to 2) of unsigned(15 downto 0); t1 is array (0 to 3) of t11; t22 is array (0 to 4) of unsigned(15 downto 0); t2 is array (0 to 2) of t22; t33 is array (0 to 4) of unsigned(31 downto 0); t3 is array (0 to 3) of t33;

In some designs you may need a Random Number Generator for generating random numbers.In C and other high level languages you have library functions for this kind of functions.In VHDL this is achieved by designing a pseudo random sequence generator (PRSG) of suitable length. The PRSG I have coded, will look like this:

The sequence generated by PRSG is not theoretically random,but for most practical applications the sequence can be considered as random.Because the period of the sequence is (2^n - 1).Where n is the number of shift registers used in the design.For 32 bit design the period is 4294967295.This is large enough for most of the practical applications. The module is written in a generic way.That means the value of 'n' can be specified at the time of compilation. Below is the code:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity random is generic ( width : integer := 32 ); port ( clk : in std_logic; random_num : out std_logic_vector (width-1 downto 0)

--

output vector ); end random; architecture Behavioral of random is begin process(clk) variable rand_temp : std_logic_vector(width-1 downto 0):=(width1 => '1',others => '0'); variable temp : std_logic := '0'; begin if(rising_edge(clk)) then temp := rand_temp(width-1) xor rand_temp(width-2); rand_temp(width-1 downto 1) := rand_temp(width-2 downto 0); rand_temp(0) := temp; end if; random_num <= rand_temp; end process;
The test bench for the code is given below:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS --Input and Output definitions. signal clk : std_logic := '0'; signal random_num : std_logic_vector(3 downto 0); -- Clock period definitions constant clk_period : time := 1 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: entity work.random generic map (width => 4) PORT MAP ( clk => clk, random_num => random_num ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; END;