Lab Session # 8 Latches, Gated Latches and Flip-Flops 1.

Introduction
In this experiment, the students will get introduced to the concept of sequential circuits: latches, gated latches and flipflops. In addition, students will use the bread board to connect different types of flip flops and analyze the behavior of each flip flop.

2. Objectives
By the end of this lab experiment, students will: Get familiar with latches and learn the difference between latches and gated latches. Get familiar with different types of flip flops and learn the difference between them. Understand the concept of storage elements.

3. Sequential Circuits
The digital circuits considered so far have been combinational circuits, where the outputs are entirely dependent on the values of the signals applied to the inputs. There exist another class of logic circuits in which the values of the outputs depend not only on the present values of the inputs but also on the past behavior of the circuit. Such circuits include storage elements that store the values of the logic signals. The contents (i.e. binary information) of the storage elements are said to represent the state of the circuit. When the circuit's inputs change values, the new input values either leave the circuit in the same state or cause it to change into a new state. Over time, the circuit changes through a sequence of states as a result of changes in the inputs. Circuits that behave this way are referred to as sequential circuits. A block diagram of a sequential circuit is shown in Figure 1. The sequential circuit receives binary information from external inputs. These inputs together with the present state of the storage elements, determine the binary value of the outputs. They also determine the condition for changing the state in the storage elements. The block diagram demonstrates that the outputs in a sequential circuit are a function not only of the inputs, but also of the present state of the storage elements. The next state of the storage elements is also a function of external inputs and the present state. Thus, a sequential circuit is specified by a time sequence of inputs, outputs and internal states.

Figure 1: Block Diagram of Sequential Circuit

There are two main types of sequential circuits and their classification depends on the timing of their signals. A synchronous sequential circuit is a system whose behavior can be defined from the knowledge of its signals at discrete

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instants of time. Storage elements observe inputs and can change state only in relation to a timing signal (clock pulses from a clock). The behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change; in other words, its behavior is immediately affected by the input signal changes. The storage elements commonly used in asynchronous sequential circuits are time-delay devices. The storage capability of a time-delay device is due to the time it takes for the signal to propagate through the device.

A synchronous sequential circuit employs signals that affect the storage elements only at discrete instants of time. Synchronization is achieved by a timing device called a clock generator that provides a periodic train of clock pulses. The clock pulses are distributed throughout the system in such a way that storage elements are affected only with the arrival of each pulse. Synchronous sequential circuits that use clock pulses in the inputs of storage elements are called clocked sequential circuits. In the same way that logic gates are the building blocks of combinatorial circuits, latches and flip-flops are the building blocks of sequential circuits. In addition, while logic gates have to be built directly from transistors, latches can be built from gates, and flip-flops can be built from latches. This fact will make it somewhat easier to understand latches and flip-flops as circuit elements. The output of both latches and flip-flops depends not only on the current inputs, but also on previous inputs and outputs. The difference between a latch and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always does.

4. Latches
Latches form the most basic type of flip-flops. This class is characterized by the fact that the timing of the output changes is not controlled. Although latches are useful for storing binary information and for the design of asynchronous sequential circuits, they are not practical for use in synchronous sequential circuits.

4.1 Basic Latch

Figure 2 represents a memory element built with NOR gates. Its inputs, Set and Reset, provides means for changing the state, Q, of the circuit. A more usual way of drawing this circuit is given in Figure 3 (a), where the two NOR gates are said to be connected in cross-coupled style. This circuit is referred to as basic latch. Its behavior is described by the table in Figure 3 (b). When both inputs, R and S, are equal to 0, the latch maintains its existing state. This state may be either Qa = 0 and Qb = 1, or Qa = 1 and Qb = 0, which is indicated in the table by stating that the Qa and Qb outputs have values 0/1 and 1/0, respectively.

Figure 2: A Memory element with NOR Gates

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Observe that Qa and Qb are complements of each other in this case. When R = 0 and S = 1, the latch is set into a state where Qa = 1 and Qb = 0. When R = 1 and S = 0, the latch is reset into a state where Qa = 0 and Qb = 1. The fourth possibility is to have R = S = 1. In this case, both Qa and Qb will be 0. The table in Figure 3 (b) resembles a truth table. However, since it does not represent a combinational circuit in which the values of the outputs are determined solely by the current values of the inputs, it is often called characteristic table rather than a truth table. Figure 3 (c) gives a timing diagram for the latch assuming that the propagation delay through the NOR gates is negligible. The initial assumption is that Qa = 0 and Qb = 1. The state of the latch remains unchanged until time t2, when S becomes equal to 1, causing Qb to change to 0, which in turn causes Qa to change to 1. The causality relationship is indicated by the arrows in the diagram. When S goes to 0 at t3, there is no change in the state because both S and R are then equal to 0. At t4, R = 1, which causes Qa to go to 0, which in turn causes Qb to go to 1. At t5, both S and R are equal to 1, which forces both Qa and Qb to be equal to 0. As soon as S returns to 0, at t6, Qb becomes equal to 1 again. At t8, S = 1 and R = 0, which causes Qb = 0 and Qa = 1. An interesting situation occurs at t10. From t9 to t10, Qa = Qb = 0 because R = S = 1. Now, if both R and S change to 0 at t10, both Qa and Qb will go to 1. But having both Qa and Qb equal to 1 will immediately force Qa = Qb = 0. There will be an oscillation between Qa = Qb = 0 and Qa = Qb = 1. If the delays through the two NOR gates are exactly the same, which never happens in real circuits, the oscillation will continue indefinitely.

Figure 3: A basic latch built with NOR gates

4.2 Gated Latch (Gated D Latch)

The gated D latch has a single data input, called D, and it stores the value on this input, under the control of a clock signal. Figure 4 (a) shows the circuit for a gates D latch. For convenience, two labels, S and R, are used to indicate the

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D and D' inputs to the NAND gates. If D = 1, then S = 1 and R = 0, which forces the latch into the state Q = 1. If D = 0, then S = 0 and R = 1, which causes Q = 0. Of course the changes in the state occur only when Clk = 1. It is important to observe that in this circuit, it is impossible to have the troublesome situation where S = R = 1. In the gated D latch, the output Q merely tracks the value of the input D while Clk = 1. As soon as Clk goes to 0, the state of the latch is frozen until the next time the clock signal goes to 1. Therefore, the gated D latch stores the value of the D input seen at the time the clock changes from 1 to 0. Figure 4 also shows the characteristic table, graphical symbol and timing diagram for the gated D latch. The timing diagram illustrates what happens if the D signal changes while Clk = 1. During the third clock pulse, starting at t3, the output Q changes to 1 because D = 1. But midway through, the pulse D goes to 0, which causes Q to go to 0. This value of Q is stored when Clk changes to 0. Now, no further change in the state of the latch occurs until the next clock pulse, at t4. The key point is to observe that as long as the clock has the value 1, the Q output follows the D input., but when the clock has the value 0, the Q output cannot change. The circuit is often called a transparent latch.

Figure 4: Gated D Latch

5. Flip-Flops
The storage elements used in clocked sequential circuits are called flip-flops. A flip-flop is a binary storage device capable of storing one bit of information. A sequential circuit may use many flip-flops to store as many bits as necessary. The block diagram of a synchronous clocked sequential circuit is shown in Figure 5. The outputs can come either from the combinational circuit or from the flip-flop or both. The flip-flops receive their inputs from the

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combinational circuit and also from a clock signal with pulses that occur at fixed intervals of time as shown in the timing diagram in Figure 5. The state of the flip-flops can change only during a clock pulse transition. When a clock pulse is not active, the feedback loop is broken because the flip-flop outputs cannot change even if the outputs of the combinational circuit driving their inputs change in value. Thus, the transition form one state to the next occurs only at predetermined time intervals dictated by the clock pulses.

Figure 5: Synchronous clocked sequential circuit

When latches are used for the memory elements in sequential circuits, a serious difficulty arises. Recall that latches have the property of immediate output responses (i.e., transparency). Because of this the output of a latch cannot be applied directly (or through logic) to the input of the same or another latch when all the latches are triggered by a common clock source. Flip-flops are used to overcome this difficulty. A Latch constantly stores its input while the Clk input is 1. In other words, it acts as a combinational circuit while the Clk is 1. A flip-flop is an edge triggered device, which means that the value stored in the flip-flop is only changed when the Clk changes from 0 to 1 (rising edge triggered) or 1 to 0 (falling edge triggered) , as shown in Figure 6, and is sensitive to its inputs only at this transition of the clock. Flip-flops can also include special input terminals for setting or clearing the flip-flop asynchronously. These inputs are usually called preset and clear, as shown in Figure 7, and they are useful for initialing the flip-flops before clocked operations are initiated. The difference in the types of flip flops is in the number of inputs and the manner in which the inputs affect the binary state. The following flip-flops will be covered in this lab: D flip-flop JK flip-flop T flip-flop Characteristic Table: The characteristics table is used in analysis since it defines the behavior and logical properties of a the flip-flop by describing its operation in a tabular form. It indicates the outputs resulting from each input combination and allow us to analyze circuits containing flip-flops. It defines the next state [Qt+1] as a Boolean function of the inputs and present state [Qt]. The characteristic table of the D flip-flop, Table 1, shows that the next state depends only on the D input and does not depend of the present state. Flip-flops have asynchronous inputs (preset and clear) that are

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used to force the flip-flop to a particular state independent of the clock. The input that sets the flip-flop to 1 is called preset and input that clears the flip-flop to 0 is called clear. The logical properties of the D, JK and T flip-flops are described in the characteristic tables, Table 1, 2 and 3, respectively. Note that the Clk arrow is drawn downwards indicating that these tables are for negative edge trigger flip-flops, as for the positive edge trigger flip-flops, the Clk arrow will be drawn upwards.

Figure 6: Clock Response in Latch and Flip-Flops

Figure 7: Negative and positive edge-triggered D flip-flops with Clear and Preset

5.1 D Flip-Flop
Figure 8 (a) shows the graphical symbol for a D flip-flop. This flip-flop has two inputs: D and clock. The D input is where the data or bit to be stored (either 0 or 1) is applied. The simplified characteristic table for the D flip-flop in Figure 8 (b) shows that the next state (Qt+1) of the D flip-flop is completely dependent on the input D and independent of the present state. When D = 0, then Qt+1 = 0, and when D = 1, then Qt+1 = 1.

Table 1: Characteristic table of Flipflops (Negative edge triggered)

D Flip-Flop

JK Flip-Flop

T Flip-Flop

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5.2 JK Flip-Flop
Figure 9 (a) shows the graphical symbol of the JK flip-flop. The simplified characteristic table for the JK flip-flop in Figure 9 (b) shows that the next state is equal to the present state when inputs J and k are both equal to 0 ( i.e. Qt+1 = Qt). When K = 1 and J = 0, the clock clears the flip-flop and Qt+1 = 0. With J = 1 and K = 0, the clock sets the flip-flop and Qt+1 = 1. When both J and K are equal to 1, the next state changes to the complement of the present state, and Qt+1 = Qt.

5.3 T Flip-Flop
Figure 10 (a) shows the graphical symbol of the T flip-flop. T flip-flop is a complementing flip-flop. The simplified characteristic table for the T flip-flop in Figure 10 (b) shows that when T = 0, the clock edge does not change the state; in other words, the state will remain the same as Qt+1 = Qt. When T = 1, the clock edge complements the present state; in other words, the new state will be Qt+1 = Qt'. Therefore, the overall operation of the circuit is that it retains its present state if T = 0, and it reverses its present state if T = 1.

Figure 9: JK Flip-Flop

Figure 8: D Flip-Flop

Figure 10: T Flip-Flop

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Figure 11 shows three different types of storage elements that are driven by the same data and clock inputs. The first element is a gated D latch, which is level sensitive. The second one is positive-edge-triggered D flip-flop and the third one is a negative-edge-triggered D flip-flop. The timing diagram shows how the operation of these storage elements different from each other.

Figure 11. Comparison of Level-Sensitive and Edge-Triggered D Storage Elements

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Student Name: Student ID:

Date:

Lab Exercise # 8
Problem Statement:
Connect the given circuits using the breadboard and the ICs provided to you by your instructor.

Design Procedure:
1. Connect a positive edge triggered D Flip-Flop (IC #: 7474) on the bread board as shown in Figure 1. Use the Push Button PB to create a trigger by connecting it to the flip flops clock input. Connect the input D to a switch and the outputs Q and Q to LEDs. Test the behavior of the D Flip-Flop by applying inputs at D and observing the outputs Q and Q.

Vcc Vcc

(PB is connected to a 10 K resistor to create the correct logic for the switch)

PRN

10K

SW1

(Q and Q connected to LEDs)

Q
CLRN

PB (NC)

Vcc

Figure 1: D Flip-Flop

2. Use negative edge triggered J-K Flip-Flop (IC #: 74LS76) to connect the circuit shown in Figure 2 on the bread board. Connect the TTL input to the flip flops clock input and set the signal to 1kHz. Connect the flip flop inputs J and K to input switches SW1 and SW2. Use channel 1 and channel 2 of the PicoScope to observe the input signal generated by the TTL and the output signal Q. Set the values of J and K to 1 and draw the generated signals on channel 1 and channel 2. Change the values of J and K and observe the resulting signals.

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Vcc
PRN

SW1 TTL (1 kHz) SW2

K
CLRN

Vcc

Figure 2: JK Flip-Flop

1. Ask your engineer to check your results, write his/her comments and sign below: .
. .

Engineer Signature: ....

Attachments:
Just submit your lab exercise sheet. No attachments for this lab.

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