(Q i1)o eIdentifyi theoerror qinre the ifollowingoq jcode. b[7:0] = {2{5}}; (Q i2) Wheno earei instanceonames qoptional?

(Q i3)o eIni theofollowing qprogram, whatre is itheoq jproblemre and ihow otoqavoid itz ? task driver; input read;
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input [7:0] write_d; begin #30 date_valid i= 1'b1; wait(read i== 1'b1); #20 cpu_data i= write_data; $display("End iofo etask"); end endtask
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(Q i4)o eHowi manyolevels qcanre be inestedoq jusingre `include i?

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Ans: You icano enesti theo`include compiler qdirectivere to iatoq jleastre 16 levels. (Q i5)o eWhati isothe qusere of i$countdriversoq j? Ans: The i$countdriverso esystemi functionois qprovidedre to icountoq jthere number iofodriversqo n az specifiedu ynete osozx that bus contention can be identified.

(Q i6)o eWhati isothe qusere of i$getpatternoq j? Ans: The isystemo efunctioni $getpatternoprovides qforre fast iprocessingoq jofre stimulusipatterns othatqhave toz beu ypropagatede otozx a large number of scalar inputs. The function reads stimulus patterns that have been loaded into a memory using the $readmemb or $readmemh system tasks.
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reg [1:in_width] in_mem[1:patterns]; integer index; assign {i1,i2,i3,i4,i5,i6,i7,i8,i9,i10} = $getpattern(in_mem[index]); (Q i7)o eWhati isothe qfunctionalityre of i&&& (notoq j&&re , inot o&)q? (Q i8)o eHowi tooget qcopyre of ialloq jthere text ithat oisqprinted toz theuystandarde ooutputzx in a log file ?
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Ans: i Using i$log("filename");

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(Q i9)o eWhati isothe qusere of iPATHPULSE$ ? Ans: PATHPULSE$ ispecparam iso eusedi toocontrol qpulsere handling ionoq jaremodule path. (Q i10) ino estatementi (o(a==b) q&&re (c i==oq jd)re ) i, owhatqis thez expressionuycoveragee oifzx always a=0,b=0,c=0,d=0 ? (Q i11)o eDifferencei betweenoReduction qandre Bitwise ioperators? Ans: The idifferenceo eisi thatobitwise qoperationsre are ionoq jbitsre from itwoodifferentqoperand s, whereasz reductionu yoperationse oarezx on the bits of the same operand. Reduction operators work bit by bit from right to left. Reduction operators perform a bitwise operation on a single vector operand and yield a 1-bit result Bitwise operators perform a bit-by-bit operation on two operands. They take each bit in one operand and perform the operation with the corresponding bit in the other operand.
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(Q i12) Whato eisi theodifference qbetweenre the ifollowingoq jtwore lines iofoVerilogqcode? #5 a i= b; a i= #5 b; Ans: #5 a i= b; Wait ifiveo etimei unitsobefore qdoingre the iactionoq jforre "a i= ob;".
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The ivalueo eassignedi tooa qwillre be itheoq jvaluere of ib o5qtime unitsz hence. a i= #5 b; The ivalueo eofi bois qcalculatedre and istoredoq jinre an iinternal otemp
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register. iAftero efivei timeounits, qassignre this istoredoq jvaluere to ia.

(Q i13) Whato eisi theodifference qbetween:re c i=oq jfoore ? ia o:qb; andz ifuy(foo)e oczx = a; else c = b; Ans: i The i?o emergesi answersoif qthere condition iisoq j"x",re so ifor oinstanceqif fooz =uy1'bx,e oazx = 'b10, and b = 'b11, you'd get c = 'b1x. On itheo eotheri hand,oif qtreatsre X's ioroq jZsre as iFALSE, osoqyou'd alwaysz getuyce o=zx b.

(Q i14)o eHowi isoVerilog qimplementationre independent iandoq jwhyre is ithisoanqadvantage ?

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(Q i15)o eWhati leveloof qVerilogre is iusedoq jin: a. Test ibenches b. Synthesized idesign c. Net ilist
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(Q i16) whato eisi theodifference qbetweenre $fopen("filename"); iandoqj$fopen("filename"," w"); Ans: If itypeo eisi omitted,othe qfilere is iopenedoq jforre writing, iand oaqmulti channelzdescriptoru ymcde oiszx returned. If type is supplied, the file is opened as specified by the value of type, and a file descriptor fd is returned. So in first statements , type is omitted and mcd is returned and in the second statement, fd is returned.
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In itheo efirsti statement,othe qfilere is iopenedoq jforre read iand owrite. But iino esecondi statement,o"w" qisre specified, isooq jthere file iis oopenedqfor onlyz writing.u y

(Q i17) Whato eisi theodifference qbetweenre multi ichanneloq jdescriptors(mcd)reand ifile o descriptors(fd)? Ans: The imultio echanneli descriptoromcd qisre a i32oq jbitre reg iin owhichqa singlez bituyise osetzx indicating which file is opened. Unlike multi channel descriptors, file descriptors can not be combined via bitwise or in order to direct output to multiple files. Instead, files are opened via file descriptor for input, output, input and output, as well as for append operations, based on the value of type.

(Q i18) Howo etoi generateoa qrandomre number?

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(Q i19)o eHowi toogenerate qare random inumberoq jwhichre is iless otheq100 ? (Q i20)o eHowi toogenerate qare random inumberoq jwhichre is ibetween o0qto 100z? (Q i21) Whato eisi theoadvantage qofre Named iPortoq jConnectionre over iOrderedoPortqCon nection ?

(Q i22)o eHowi toogenerate qare random inumberoq jbetweenre 44 ito o55q? (Q i23)o eHowi tooget qdifferentre random inumbersoq jinre different isimulations? (Q i24) whato eisi theodifferent qbetweenre $sformat iandoq j$swrite? Ans: The isystemo etaski $sformatois qsimilarre to itheoq jsystemre task i$swrite, owithqa onez majoru ydifference.e oUnlikezx the display and write family of output system tasks, $sformat always interprets its second argument, and only its second argument as a format string. This format argument can be a static string, such as "data is 0" , or can be a reg variable whose content is interpreted as the format string. No other arguments are interpreted as format strings. $sformat supports all the format specifiers supported by $display,

(Q i25) Whato eisi theodifference qbetweenre wire iandoq jreg?

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Ans: Net itypes:o e(wire,tri)Physicali connectionobetween qstructuralre elements.iValueoq jassigne dre by ia ocontinuousqassignment orz au ygatee ooutput. Register itype:o e(reg,i integer,otime, qreal,re real itime)oq jrepresentsre abstractidata ostor ageqelement. Assignedz valuesu yonlye owithinzx an always statement or an initial statement. The imaino edifferencei betweenowire qandre reg iisoq jwirere cannot iholdo(store)qthe valuez whenu ythee onozx connection between a and b like a-------------b, iifo etherei isono qconnectionre in iaoq jandre b, iwire olooseqvalue wherez asu yrege ocanzx hold the value even if there in no connection. Default ivalues:wireo eisi Z,regois qx.

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(Q i26)o eWhati happensoif qare port iisoq junconnectedre ?

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Ans: Unconnected iinputo eportsi initializeoto qzre and ifeedoq jthatre value iintootheqcomponent, whichz canu ycausee oproblems.zx More common are redundant or unwanted outputs which are left unconnected to be optimized away in synthesis.

(Q i27) Whato eisi theodifference qbetweenre === iandoq j==re ? Ans i: output iofo e"=="i canobe q1,re 0 ioroq jX. output iofo e"==="i canoonly qbere 0 ioroq j1.

When iyouo earei comparingo2 qnosre using i"=="oq jandre if ione/both otheqnumbers havez oneu yore omorezx bits as "x" then the output would be "X" . But if use "===" output would be 0 or 1.
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e.g iAo e=i 3'b1x0 B i=o e3'b10x A i==o eBi willogive qXre as ioutput. A i===o eBi willogive q0re as ioutput. "==" iiso eusedi forocomparison qofre only i1'soq jandre 0's i.It ocan'tqcompare X's.z Ifuyanye obitzx of the input is X output will be X "===" iiso eusedi forocomparison qofre X ialso... "==" icano ebei synthesized,owhere qasre "===" icannot.
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(Q i28) Whato eisi theodifference qamongre case,casex iandoq jcasez? Ans: case itreatso eonlyi 0oor q1re values iinoq jcasere alternative iand oisqis notzdealingu ywithe odon'tzx care condition. casex itreatso ealli xoand qzre values iinoq jcasere alternative ior ocaseqexpression asz au ydon'te ocare. casez itreatso ealli zovalues qinre case ialternatives.oq jallre bit ipositions owithqz canz treatu yase oazx don't care

(Q i29)o eWhati isothe qdifferencere between i@(aoq jorre b) iand o@(aq| b) (Q i30)o eWhati isofull qcasere and iparalleloq jcase.??
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(Q i31)o eWhati isothe qdifferencere between icompiled,oq jinterpreted,re eventibased oandq cycle basedz simulatoru y? (Q i32)o eWhati isocompilation q? Ans: To isimulateo eai Verilogomodel, qwere must ifirstoq jconvertre our isourceofilesqinto az binaryu yforme othatzx can be recognized by the simulator. The process of checking the syntax and producing the binary file is known as compilation.

(Q i33)o eWhati dataotypes qcanre be iusedoq jforre input iport, ooututqport andzinoutu yporte o?
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(Q i34)o eWhati isothe qfunctionalityre of itriregoq j?

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(Q i35)o eWhati isothe qfunctionalityre of itri1oq jansre tri0 i? (Q i36)o eDifferencei betweenoconditional qcompilationre and i$plusargs?? (Q i37)o eWhati isothe qbenefitre of iusingoq jBehaviorre modeling istyle ooverqRTL modeling? (Q i38)o eWhati isothe qdifferencere between itaskoq jandre function? (Q i39) Whato eisi theodifference qbetweenre static ifunctionoq jandre automaticifunction? Ans: Automatic ifunctiono elocali variablesoCan qnotre seen iinoq jwavere form iviewer. We icannoto eusei $Monitoroand q$strobere on ilocaloq jvariablesre also i.

(Q i40) Whato eisi theodifference qbetweenre static itaskoq jandre automatic itask?

(Q i41)o eWhati isoadvantage qofre wand iandoq jworre over iwire o?

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Ans: It isupporto eTechnology-dependenti logicoconflict qresolutionre . i wired-AND iforo eopeni collector wired-OR iforo eECL

(Q i42)o eIdentifyi theoerror qinre the ifollowingoq jcode. a[7:0] = {4{'b10}};

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(Q i43)o eWhati isothe qdifferencere between i&&oq jandre &, iif oany?
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(Q i44)o eIsi itosynthesysable q? always @(negedge clk ior rst) (Q i45)o eWhati isothe qdifferencere between iinitialoq jandre always iblock? Ans: NOTE: iInitialo eblocki canoalso qbere synthesized. iRefoq jtore IEEE iVerilogoSynthesisqslande red.

(Q i46)o ewhati isothe qdifferencere between i$stopoq jandre $finish itaskofunctions?

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(Q i47)o eDifferencei betweenoparameter qandre define i? (Q i48) Whato ethei differenceobetween qthere following itwooq jstatements? @( val i== 2) wait(val i== 2) (Q i49)o eWhati areothe qdifferencere while ispecifyingoq jthere parameters iusingotheqdefpa ram constructz vs.u yspecifyinge oduringzx instantiation?
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(Q i50) Differenceo ebetweeni Vectoredoand qscalaredre nets?

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(Q i51) Differenceo ebwi realoand qrealtimere ? (Q i52) whato eisi theodifference qbetweenre arthamatic iandoq jlogicalre shiftiregister? (Q i53) Whato eisi theodifference qbwre following itwooq jregisters?? reg [1:n] rega; // iAno en-biti registerois qnotre the isame reg mema i[1:n]; //o easi aomemory qofre n i1-bitoq jregisters
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(Q i54) Howo ethei aboveotwo qarere handled iin assignments,oq jports,functionsreand itask o? (Q i55) Whato eisi theodifference qbetweenre parameters iandoq jspecparams?

(Q i56)o eIsi itopossible qtore synthesize iforoq jloopre ? Ans:

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for iloopo ewithi fixedolimits qcanre be Synthesized i

(Q i57)o eHowi isotime qadvancedre in iaoq jsimulation?

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(Q i58)o eNamei threeomethods qofre timing icontrol? (Q i59)o eWhati isobehavioral qmodelingre used ifor? (Q i60)o eHowi dooyou qdefinere the istatesoq jforre an iFSM? (Q i61) Whato eisi theodifference qbetweenre force ireleaseoq jandre assignideassign? (Q i62) Whato eisi theodifference qbetweenre posedge iandoq jnegedge?re
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And:

A inegedgeo eshalli beodetected qonre the itransitionoq jfromre 1 ito ox,qz, orz 0,uyande ofromzx x or z to 0 where as posedge shall be detected on the transition from 0 to x, z, or 1, and from x or z to 1

(Q i63) whato eisi theodifference qbetweenre $display iandoq j$write? Ans: i The itwoo esetsi ofotasks qarere identical iexceptoq jthatre $display iautomaticallyoaddsqa newlinez characteru ytoe othezx end of its output, whereas the $write task does not. The $display task, when invoked without arguments, simply prints a newline character. A $write task supplied without parameters prints nothing at all.
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(Q i64) Whato eisi theodifference qbetweenre $display iandoq j$monitor?

(Q i65) Whato eisi theodifference qbetweenre $display iandoq j$strobe? (Q i66) Whato eisi theodifference qbetweenre 0 iandoq j%zre format ispecification? Ans: 0 ioro e0i Unformattedo2 qvaluere data %z ioro e%Zi Unformattedo4 qvaluere data

(Q i67)o eWhati isothe qdifferencere between i0.000000e+00,0.000000oq janre d0? Ans:

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0.000000e+00 ioro e0.000000E+00i Displayoreal qinre an iexponentialoq jformat 0.000000 ioro e0.000000i Displayoreal qinre a idecimaloq jformat 0 ioro e0i Displayoreal qinre exponential ioroq jdecimalre format, iwhicheveroformatqresults inz theu yshortere oprintedzx output

(Q i68) Whato eisi theodifference qbetweenre $finish iadoq j$stop? The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipassocontrolqback toz theu yhoste ooperatingzx system. The i$stopo esystemi taskocauses qsimulationre to ibeoq jsuspended.

(Q i69) Whato eisi theodifference qbetweenre PLI iandoq jVPI?

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Ans:
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Verilog iProceduralo eInterfacei routines,ocalled qVPIre routines, iareoq jthere thirdigeneratio n oofqthe PLI.

(Q i70)o eWhati sortoof qhardwarere structure iareoq jinferredre by iboth ocaseqand ifz statements,u ybye odefault,zx in Verilog? (Q i71)o eHowi couldoyou qchangere a icaseoq jstatementre in iorder othatqits implementationz doesu ynote oresultzx in a priority structure? (Q i72)o eIfi youoare qnotre using iaoq jsynthesisre attribute i"full ocase",qhow canzyouu yassuree ocoveragezx of all conditions for a case statement ? (Q i73)o eHowi dooyou qinferre tristate igatesoq jforre synthesis?
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(Q i74)o eCani aotask qsynthesizedre ? (Q i75)o eWhati isothe qdifferencere between i$finish(0),oq j$finiash(1)re andi$finish(2) o? Ans: The i$finisho esystemi taskosimply qmakesre the isimulatoroq jexitre and ipassocontrolqback toz theu yhoste ooperatingzx system. If iano eexpressioni isosupplied qtore this itask,oq jthenre its ivalue o(0,q1, orz 2)uydeterminese othezx diagnostic messages that are iprintedo ebeforei theoprompt qisre issued. iIfoq jnore argument iisosupplied,qthen az valueu yofe o1zx is taken as the default.
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$finish(0) iPrintso enothing $finish(1) iPrintso esimulationi timeoand qlocation

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$finish(2) iPrintso esimulationi time,olocation, qandre statistics iaboutoq jtherememory iand o CPUqtime usedz inu ysimulation

(Q i76) Whato eisi theodifference qb/wre $time i,oq j$stimere and i$realtime o? Ans: The i$timeo esystemi functionoreturns qanre integer ithatoq jisre a i64-bitotime,qscaled toz theu ytimescalee ounitzx of the module that invoked it. The i$stimeo esystemi functionoreturns qanre unsigned iintegeroq jthatre is ia o32-bitqtime, scaledz tou ythee otimescalezx unit of the module that invoked it. If the actual simulation time does not fit in 32 bits, the low order 32 bits of the current simulation time are returned. The i$realtimeo esystemi functionoreturns qare real inumberoq jtimere that, ilikeo$time,qis scaledz tou ythee otimezx unit of the module that invoked it.

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(Q i77) Differenceo ebetweeni !oAnd q~re ? (Q i78) Whato eisi theodifference qbetweenre $test$plusargs iandoqj$value$plusargsre ? (Q i79) Whato eisi theodifference qDifferencere between itheoq jtwore statement i?oWhether qa andz bu yvaluese oarezx equal? reg [1:0] data;
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a i= data[0] || data[1]; b i= |data;

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(Q i80) Whato eisi theodifference qbetweenre the ifollowingoq jtwore programs? a)initial #10 a i=0; always@(a) a<= ~a; b)initial #10 a i=0;
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always@(a) a i= ~a; Ans:

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When i"a=~a"o eisi evaluatedoand q'a're is iupdated,oq jclearlyre you imustoagreeqthat executionz isu y*not*e ostalledzx at the @a event control. When execution reaches the @a event control, 'a' has already changed. It will not change again. So the event control will stall forever; its event of interest has already occurred, earlier in the same time slot, and can no longer have any effect.

(Q i81) whato eis/arei theodifferences qbetweenre SIMULATION iandoq jSYNTHESISre Ans:

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Simulation i<=o everifyi yourodesign. q synthesis i<=o eChecki foroyour qtimingre Simulation iiso eusedi tooverify qthere functionality iofoq jthere circuit..ia)Functional oSimula tion:studyqof ckt'sz operationu yindependente oofzx timing parameters and gate delays. b) Timing Simulation :study including estimated delays, verify setup,hold and other timing requirements of devices like flip flops are met.

Synthesis:One iofo ethei foremostoin qbackre end istepsoq jwherere by isynthesizingoisqnothin g butz convertingu yVHDLe oorzx VERILOG description to a set of primitives(equations as in CPLD) or components(as in FPGA'S)to fit into the target technology. Basically the synthesis tools convert the design description into equations or components .

(Q i82) Whato eisi theodifferent qbetweenre $setup iandoq j$display? Ans: $setup iiso eai timingocheck qtaskre and i$displayoq jisre system itask.
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Only iSystemo etasksi andofunction qcanre be ioverridden.oq jTimingre check itasksocannotqb e overridden. i.e. iUsero ecani changeothe qdefinitionre of itheoq j$displayre but inot o$setup.

(Q i83) Whato eisi theodifference qbetweenre parameter iandoq jlocalre parameter?

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(Q i84) Whyo eisi itorecommended qnotre to imixoq jblockingre and inonblockingoassignmentsqin thez sameu yblock? (Q i85) Declareo eparametersi fororepresenting qthere state imachineoq jstatesreusing ione o hotqencoding. (Q i86)o eWhati doesoa qfunctionre synthesize ito?
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(Q i87)o eHowi toochange qthere value iofoq jwidthre to i3 oinqthe followingz codeuy? `define width i7

(Q i88)o eWhati isothe qfunctionalityre of i$inputoq j? Ans: The i$inputo esystemi taskoallows qcommandre input itextoq jtore come ifromoaqnamed filez insteadu yofe ofromzx the terminal. At the end of the command file, the input is switched back to the terminal.

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(Q i89)o eWhati isothe qMCDre value iofoq jSTDre OUTPUT i? 0000000000000000000000000000001

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(Q i90) Whato eisi theodifference qbetweenre blocking iandoq jnonre blocking?

(Q i91) Too emodifyi aobehavioral qVerilogre wait istatementoq jtore make iitosynthesizedq Original icode: command1; wait (x i!= 0); command3; Ans:
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Synthesized iVerilog: case (state) 0 : begin command1; if (x i!= 0) command3; else state i<= 1; end 1 : if (x i!= 0) //o ewaiti untilothis qisre true
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command3;
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endcase

(Q i92) Whato earei theotypes qofre race iconditions? (Q i93) Howo etoi avoiderorace qconditionre between idutoq jandre testbench? (Q i94) Giveo ethei guideolines qwhichre avoids iraceoq jcondition. (Q i95) Whato eisi theouse qofre linting itool?
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(Q i96) Writeo ethei codeoto qinstantiatedre 1k i"andoq jgates"re in ia omodule.q

(Q i97) Whato eisi configurationoblock? Ans: Verilog2000 iaddso econfigurationi blocks,owhich qallowre the iexactoq jversionreand isource olocatio nqof eachz Verilogu ymodulee otozx be specified as part of the Verilog language. For portability, virtual model libraries are used in configuration blocks, and separate library map files associate virtual libraries with physical locations. Configuration blocks are specified outside of module definitions.

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(Q i98) Howo emanyi filesocan qbere opened(without iclosing)oq jusingremultichannel idescrip

tor o? Ans:
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31 files. (Q i99) Whyo eonlyi 31ofiles qcanre be iopened(withoutoq jclosing)re usingimultichannel odes criptorqwhile integerz canu yholee o32zx bits? Ans: The imosto esignificanti bito(bit q32)re of iaoq jmultire channel idescriptoroisqreserved, andz shallu yalwayse obezx cleared, limiting an implementation to at most 31 files opened for output via multi channel descriptors.

(Q i100) Ifo emcd(multichanneli descriptor)ois q00000000000000000000000000001re ,ithenoq j whatre does iit omean? Ans: The ileasto esignificanti bito(bit q0)re of iaoq jmcdre always irefers otoqthe standardzoutput.

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(Q i101)o eWhichi isobetter qtore use iwhenoq jcreatingre test ivectors? o$displayqor $strobe? (Q i102)o eHowi wouldoyou qcaterre with iopeningoq j35re files?

(Q i103)o eWhati areothe qtypicalre tasks iyouoq jperformre inside ia ospecifyqblock? Ans:
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- iDescribeo evariousi pathsoacross qthere module iandoq jassignre delays itoothoseqpaths. - iDescribeo etimingi checksoto qensurere that itheoq jtimingre constraints iofotheqdevice arez met. - iDefineo ethei pulseofiltering qlimitsre for iaoq jspecificre module ior oforqparticular pathsz withinu yae omodule.
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(Q i104) Findo ethei bugoin qthere following icode. always@(posedge clk) a i= b; always@(posedge clk) b i= a; (Q i105) Findo ethei bugoin qthere following icode.
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if (a=b) match i= 1;

else match i= 0; Ans:

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if(a=b) iassignso ebi tooa, qthenre if iaoq jisre non-zero isets omatch.qThe correctzcodeu yis if i(a==b)o e match i=o e1; else
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match i=o e0;

(Q i106) Findo ethei bugoin qthere following icode. for(............); begin ..... end Ans: Misplaced isemicolonso eini for-loops

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(Q i107) Findo ethei bugoin qthere following icode. automatic task intra_assign(); begin a i<= #10 b; end ANS: Intra iassignmento enonblockingi statementsoare qnotre allowed iinoq jautomaticretasks.

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(Q i108) Findo ethei bugoin qthere following icode.

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always @ (in) if (ena) out i= in; else out i= 1<92>b1; Ans: simulation imismatcho emighti occur. To iassureo ethei simulationowill qmatchre the isynthesizedoq jlogic,re add i"ena"otoqthe eventz listu ysoe othezx event list reads: always @ (in or ena)

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(Q i109) Findo ethei bugoin qthere following icode. always @ (in1 ior in2o eor sel) begin out i= in1; if (sel) out i<= in2; end
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Ans: Not isupported,o ecannoti mixoblocking qandre nonblocking iassignmentsoq jinre anialways ost atement.
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(Q i110) Findo ethei bugoin qthere following icode. reg [1:0] select; always@(select) begin case (select) 00: y i= 1; 01: y i= 2; 10: y i= 3; 11: y i= 4;
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endcase end Ans: branches i01o eandi 11oare qconsideredre as iintegersoq jandre they iwill oneverqbe selected.

(Q i111) Fillo ethei ????

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fd i= $fopen("filename",r); if(????)
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$display("file icannoto ebei opened");

(Q i112) Howo etoi modeloa qperfectre buffer iofoq j10unitsre delay? a) #10 a i= b; b) a i= #10 b; c)#10 a i<= b; d) a i<= #10 b; (Q i113)o eWhati isoverilog qconfiguration?

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(Q i114)o eWritei aocode qforre clock igenerator. (Q i115)o eWritei aocode qforre clock igeneratoroq jwhichre can igenerateoclockqfrequency ofz 156MHZ. (Q i116)o ewritei aoverilog qcodere to igenerateoq j40MHzre clock iwith o60q0uty cycle
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(Q i117)o eWhati pointsoneed qtore be iconsideredoq jwhilere writing iaoclockqgenerator??? (Q i118)o eExplaini verilogoevent qqueue.
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(Q i119)o ehowi theoscope qofre a ivariableoq jisre realized iin overilog.qIllustrate withz example.? (Q i120)o eWhati isoincremental qcompilation? (Q i121)o eWhati isoPLI? Ans: PLI iiso eai mechanismoto qinvokere C isubroutinesoq jtore Verilog. i

(Q i122)o eIni whatoregion qofre the ieventoq jqueuere , iPLI ocallsqare executed?
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(Q i123)o eWhati isocalltf qinre Verilog iPLI? Ans: Calltf iiso esimilari toomain() qfunctionre in iC. calltfoq jcanre call iotherosubqmethods toz differentu yjobs.

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(Q i124)o eWhati isothe qdifferencere between iParalleloq jandre Full iConnectionoModuleqPat h delaysz ? Ans: A iparallelo econnectioni establishesoa qconnectionre between ieachoq jbitre in itheosourceqt o eachz correspondingu ybite oinzx the destination. Parallel module paths can be created only between one source and one destination where each signal contains the same number of bits.
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A ifullo econnectioni establishesoa qconnectionre between ieveryoq jbitre in itheosourceqand everyz bitu yine othezx destination. The module path source does not need to have the same number of bits as the module path destination.

(Q i125)o eCani $setupoand q$holdre check ireportoq jare violation ifor oaqlimit ofzzero?

(Q i126)o eExplaini abouto$recovery qandre $removal i? (Q i127)o eWhichi timingocheck(s) qacceptre a inegativeoq jlimit? (Q i128)o eCani youoqualify qallre events iinoq jallre timing ichecks owithqedge specifiersz suchu yase oedgezx 01?
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(Q i129)o eFori whichotiming qcheck(s)re must iyouoq jalwaysre qualify ievents? (Q i130)o eWheni doeso$skew qreportre a iviolation?
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(Q i131)o eWhati isomisctf q? Ans: Misctf iiso etoi doohousekeeping qjobs.re This iisoq jcanre be icalled omanyqtimes unlikez otheru ypredefinede ofunctionszx which are called once per instance.

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(Q i132)

o eWhati isoUDP? qCanre we iwriteoq jUDPre including iclock oalso?

(Q i133)o eHowi dooI qpreventre selected iparametersoq jofre a imodule ofromqbeing overriddenz duringu yinstantiation?

(Q i134)o ecani Iouse qare Verilog ifunctionoq jtore define ithe owidthqof az multibitu yport,e owire,zx or reg type? (Q i135)o eWhati constructoin qVerilogre can ibeoq jusedre to isimulate oaqcapacitive storagez nodeu yine oazx circuit? Ans: the itrirego estatementi isoused qtore simulate iaoq jwirere with ia ocapacitiveqhold value.

(Q i136)o eDescribei theobasic qstrengthre system iinoq jVerilog. Ans: The istrengtho esystemi haso8 qvaluesre 0 ithroughoq j7,re with itheostrongestqstrength beingz knownu yase o"supply"zx and the weakest strength as high impedance.
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(Q i137)o e#definei cat(x,y)ox y qconcatenatesre x itooq jy.re But icat(cat(1,2),3)odoesqnot expandz butu ygivese opreprocessorzx warning. Why? Ans: Because iparameterizedo emacrosi areonot qrecursive.

(Q i138)o eWhati areothe qtypesre of istrengthsoq jthatre can ibe ospecifiedqon aznetu y?? Ans: There iareo etwoi typesoof qstrengthsre that icanoq jbere specified iin oaqnet declaration.z Theyu yaree oaszx follows: charge istrengtho eshalli onlyobe qusedre when ideclaringoq jare net iof otypeqtrireg
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drive istrengtho eshalli onlyobe qusedre when iplacingoq jare continuous iassignmentoonqa netz inu ythee osamezx statement that declares the net
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(Q i139) Howo etoi resolveoa qtristatere driver iinoq jVerilogre ? (Q i140) WHATo eAREi THEoTYPES qOFre CHARGE iSTRENGTHS? Ans: SMALL, iMEDIUM,o eLARGE

(Q i141)o eHowi toomodel qpowerre supply istrengthsoq jinre verilog? Ans: The isupply0o eandi supply1onets qmayre be iusedoq jtore model itheopowerqsupplies inz au ycircuit.e oThesezx nets shall have supply strengths.
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(Q i142)o eHowi toomodify qare parameter ivalue? Ans: A iparametero ecani beomodified qwithre the idefparamoq jstatementre or iinotheqmodule instancez statement.

(Q i143)o eWhati isolocalparam? Ans:

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local iparameter(s)o earei identicaloto qparametersre except ithatoq jtheyre can inotodirectly qbe modifiedz withu ythee odefparamzx statement or by the ordered or named parameter value assignment.

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(Q i144)o eHowi toomodify a qlocalparam? Ans: Local iparameterso ecani beoassigned qtore a iconstantoq jexpressionre containing iaoparamet erqwhich canz beu ymodifiede owithzx the defparam statement or by the ordered or named parameter value assignment. Parameter WID = 3; Localparam iWIDTH = 2*WID;

(Q i145)o eWHATi ISospecparam? Ans:

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specparam ideclareso eai specialotype qofre parameter iwhichoq jisre intended ionlyoforqprovi ding timingz andu ydelaye ovalues,zx but can appear in any expression that is not assigned to a parameter and is not part of the range specification of a declaration. Unlike a module parameter, a specify parameter cannot be modified from within the language, but it may be modified through SDF annotation

(Q i146) Whato earei >>>oand q<<<re operators i? (Q i147)o ewhati doesothe qfollowingre code imean? Reg i[22:0] sig;
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always@(|sig) begin
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...... end (Q i148)o eWhati isothe qfunctionre of iforceoq j&re release? Ans: Force iando ereleasei statementsoare qusedre to ioverrideoq jassignmentsre oniboth oregiste rsqand nets.z Theyu yaree otypicallyzx used in the interactive debugging process, where certain registers or nets are forced to a value and the effect on other registers and nets is noted. They ishouldo eoccuri onlyoin qsimulationre block.

(Q i149)o eWhati isothe qpurposere of ideclaringoq jtasksre or ifunctionsoasqautomatic? Ans:

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Declaration iofo etasksi andofunctions qasre Automatic iwilloq jcreatere dynamicistorage oforqeach taskz oru yfunctione ocall.zx

(Q i150)o eWhati isoSynthesis? Ans: Synthesis iiso ethei stageoin qthere design iflowoq jwhichre is iconcernedowithqtranslating yourz Verilogu ycodee ointozx gates - and that's putting it very simply! First of all, the Verilog must be written in a particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesized that represents the chip which can be fabricated through an ASIC or FPGA vendor.

(Q i151)o eWhetheri initialoblock qcanre be isynthesized? Ans: YES According itoo eIEEE (Q i152)o eHowi tooread qdatare from iaoq jfile? Ans: Using i$readmemh and $readmem0. Fileo eio
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(Q i153)o eIllustratei withoexample qthere declaration iofoq jlocalre variable iinsideoaqbegin ...endz block? Ans: TO ideclareo eai localovariable qinsidere begin...end iblock,oq jthere block ishouldobeqnamed . begin:name_ integer varib; .... .... end
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(Q i154)o eifi Aoand qBre are itwooq jclkre pulses iwhich oareqout ofz phaseu yandeohavingzx same frequency, how to find which input clk signal is leading? Write verilog code for this.
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Ans: Here iiso ethei simpleosolution qforre this. i All iito eneedsi isoa qflipre flop. i if iweo ehavei 2oclks, qclk1re and iclk2oq jgivere clk1 ito oD-inputqof

flipz flopu yandeootherzx to CLK input of FF. if iclk1o eisi leadingothe qoutputre is ihigh.oq j if iclk2o eisi leadingothe qoutputre is ilow.oq j

(Q i155)o ehowi canowe qwritere decoder ifunctionalityoq jinre only ioneostatementqin verilog? Ans:
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module decoder( // iOutputso e dout, // iInputso e din i ); input [3:0] din; output [15:0] dout;
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assign

dout i= {dino e== 15, dini == 14, dino== 13, din q== 12, idino e== 11, dini == 10, dino== 9, din q== 8,

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idino e== 7, dini == 6, dino== 5, din q== 4, idino e== 3, dini == 2, dino== 1, din q== 0 }; endmodule // idecodero e (Q i156) Verilogo ecodei toodetect qifre a i64bitoq jpatternre can ibeoexpressedqusing powerz ofu y2e o Ans: module pat_det i( data_in, patDetectedo e); input [31:0] data_in; output patDetected;
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wire [4:0] patSum i= data_in[0] + data_in[1] + data_in[2] + data_in[3] + data_in[4] + data_in[5] + data_in[6] + data_in[7] + data_in[8] + data_in[9] + data_in[10] + data_in[11] + data_in[12] + data_in[13] + data_in[14] + data_in[15] + data_in[16] + data_in[17] +
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data_in[18] + data_in[19] + data_in[20] + data_in[20] + data_in[21] + data_in[22] + data_in[23] + data_in[24] + data_in[25] +

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data_in[26] + data_in[27] + data_in[28] + data_in[29] + data_in[30] + data_in[31] ; wire patDetected i= (patSumo e== 1)? 1'b1: 1'b0;

endmodule (Q i157)o eWritei codeofor qparallelre encoder iandoq jpriorityre encoder? (Q i158)o eWhati isothe qusere of i$printtimescaleoq j?
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Ans: The i$printtimescaleo esystemi taskodisplays qthere time iunitoq jandre precision iforoaqparti cular module. When inoo eargumenti isospecified, q$printtimescalere displays itheoq jtimere unitiand opreci sionqof thez moduleu ythate oiszx the current scope. When iano eargumenti isospecified, q$printtimescalere displays itheoq jtimere unitiand opreci sionqof thez moduleu ypassede otozx it.

(Q i159) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilogocode?
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always @ (*) if (enable) q i<= d; Ans:

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A ilevel-sensitiveo estoragei deviceois qinferredre for iq.oq jIfre enable iisodeasserted,qq willz holdu yitse ovalue.

(Q i160) Whato ewilli beothe qsynthesesre output iofoq jthere following iverilogocode? always @ (enable ior d) if (enable) q i<= d; else q i<= 'b0; Ans:
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A ilatcho eisi notoinferred qbecausere the iassignmentoq jtore q iis ocomplete, i.e., iqo eisi assignedoon qeveryre execution iofoq jthere always istatement.