VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN

MODEL EXAMINATION- (NOV DEC 2011) ELECTRONICS AND COMMUNICATION ENGINEERING

Third semester DIGITAL ELECTRONICS (SET 1) Max Mark: 100 Answer all questions 1. State Demorgans two laws for three variables. 2. List out the advantages and disadvantages of K-map method? 3. What is BCD adder? 4. Give other name for Multiplexer and Demultiplexer. 5. What do you mean by triggering of flip-flop? 6. What is an excitation table? 7. Differentiate ROM & PLDs 8. Differentiate volatile and non-volatile memory? 9. Define critical & non-critical race with example. 10. Differentiate Moore circuit and Mealy circuit? PART B (5*16=80marks) 11. (a) Use the Truth table method to prove ABC+B+BD+ABD+AC = B+C (Or) (b) Minimize the following using K map realization and verify the result using Tabular methods: m (0, 2, 4, 5, 6, 8, 10, 14, 15) 12. (a) Design a 4 bit carry look-ahead adder and compare its advantages over 4 bit parallel binary adder. (Or) (b) Construct a 5X32 decoder with four 3X5 decoders and a 2X4 decoder. Use block diagrams. 13. (a) Design a 3 bit asynchronous ripple counter using T flip flops and explain its operation. (Or) (b) Design a 3 bit universal shift register and explain its operation. 14. (a) Explain the read cycle and write cycle timing parameters with the help of timing diagrams. (Or) (b) Compare Static RAMs and Dynamic RAMs . 15. (a) What is meant by hazard free digital circuits? How the same can be realized? Explain with an example. (Or) (b) As asynchronous sequential circuit is described by the following excitation and output function y = x1x2+(x1+x2) y z = y i) Draw the logic diagram of the circuit and describe the behavior of the circuit. ii) Derive the transition table and output map. ALL THE BEST Time: 3 hrs PART A (10*2=20marks) Date: 14-10-11

VIVEKANANDHA COLLEGE OF ENGINEERING FOR WOMEN

MODEL EXAMINATION- (NOV DEC 2011) ELECTRONICS AND COMMUNICATION ENGINEERING

Third semester DIGITAL ELECTRONICS Max Mark: 100 Answer all questions 1. What are the universal gates? Why? 2. What are dont care conditions? 3. Define Combinational and sequential circuit. 4. What is meant by self-complementing code? 5. Give the excitation table of a JK and SR flip-flop. 6. What is synchronous and Asynchronous counter? 7. Draw the basic configuration of PAL and PLA. 8. Explain RAM. 9. How can a race be avoided? 10. Define primitive flow table? PART A (5*16=80marks) 11. (a) Simplify the following functions using tabulation method F(A,B,C,D) = m(2,3,7,9,11,13)+d(1,10,15) (Or) (b) Draw the circuit diagram of 2 inputs CMOS-NAND gate and explain their operation and characteristics. What are the different types of TTL gates available? Explain their operation taking suitable example. 12. (a) Draw the logic diagram of 6 bit binary to grade code converter. (Or) (b) Design a combinational circuit that detects an error in the representation of a decimal digit in BCD. 13. (a) Explain the working of BCD ripple counter with timing diagrams. (Or) (b) Design and explain the working of mod 7 up down counter. 14. (a) Draw the block diagram of a PLA and PAL devices and briefly explain each block. (Or) (b) Illustrate the concept of 16X8 bit ROM array with diagram. 15. (a) Discuss a method used for race free assignments with example. (Or) (b) Design a pulse mode circuit with three inputs x1, x2, x3 and one output z. The output z should change from 0 to 1, only for the input sequence x1-x2-x3.Also the output z should remain in 1 until x2 occurs. Use SR flip flop for the design. `ALL THE BEST Time: 3 hrs PART A (10*2=20marks) Date: 14-10-11