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ADCA / MCA (III year)

Term-End. Examination
June, 2OO7

CS-12: COIfiPUTER
ARCHTTECTURE
Time : 3 hours Maximum Marks : 75

Note r Qu estion nu mber I is compulsory. Ans wer any


three questionsfrom the rest.

1- (a) A two{evel memory systemhas 8 virtual pages on a


disk to be mapped into four page frarnesin the main
memory. The page trace is

1,0, 2,2, 1,7,6,7,0, 1,2,0, 3,0,4,5, 1,5, 2

Using circular FIFO page replacement policy,


compute the hit ratio in the main rnemory. Assume
the page frames are initially empty. 6

(b) why has shared virtual rnemory become a necessity


in building a scalable system with memories
physically distributed over a large number of
processingnodes ?

CS-12 P.T.O.
(c) Perform the data dependence analysis on the
following program :

5 1: A : C + E
3 2 : B : A x 4
5 3 : A : A + B
5 4 :D : A / 4
(d) What is meant by inclusioncoherenceand locality in
a memory hierarchy ? Explain through a diagram
and an example.
(e) Explain the support for data path MMU and TLB
for common and separatecache architectures.
(f) Define any three characteristicsof parallelalgorithms
which are machine implementable.

2. (a) A workstation uses a 15 MHz processor with a


claimed 10 MIPS rating to executea given program
rnix. Assume a one-cycle delay for each mernory
access.
(i) What is the effective CPI of this computer ?
(ii) Supposethe processoris being upgradedwith a
30 MHz clock. The speed of the memory
subsystem remains unchanged and two clock
cycles are neededWr memory access.If 300/o
of the instructions require one memory access
and another 5o/orequire two memory accesses
per instmction, what is the performanceof the
upgraded processor with a compatible
instruction set and equal instruction counts in
the given program mix ? 10

CS-12
(b) Explain the following terms \Ar.r.t. communication
patterns in messagepassingnetworks :

(il Channel traffic or network traffic

(ii) Network partitioning for multicasting


communications

3. (a) How much improvement in performance can be


achieved by inserting one unit of delay in the
following reservation table ?

\ime 0 1 2 3 4 5 6 7 8
Stag\

1 X X

2 X X

3 X X

4 X X

5 X

(b) Draw a diagram and explain multi-threaded


architecture and its computation model for a
massivelyparallel processingsystem. Also list all the
parametersused in it.

4. Explain the structuresand operational requirementsof the


instructionpipelinesusedin scalarRISC, superscalarRISC
and VLIW processors.What are the cycles per instruction
expectedfrom these processorarchitecfures? 75

CS-12 P.T.O.
5. (a) A computer system has a Iz8 byte cache. It uses
four-way set associativemapping with 8 bytes in
each block. The physicaladdresssizeis 32 bits and
the smallestaddressableunit is 1 byt".
(i) Draw a diagram showing organization of the
cache and indicatinghow the physicaladdresses
are relatedto cache addresses.
(ii) To what block frames of the cache can the
address000010AF16 be assigned?
(iii) If the addresses000010AFr6 and FFFFTfuyro
can be simultaneouslyassigned to the same
cache set, what values can the addressdigits x
and y have ?

(b) Fxplain six basic metrics affectingthe scalabilityof a


computer system.

CS.12 15,000

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