Abstract--This paper proposes the H-Bridge multilevel

circuits with sinusoidal pulse width modulation (SPWM) and

double carrier for each level with different phase shifts from
3.75
0
- 90
0
. Operating principle with switching functions is
analyzed from five to twenty five (odd) levels SPWM inverter
and simulated to alleviate harmonic components of output
voltage. By observing theTHD and fundamental component of
different levels the optimum level of inverter is obtained for a
constant 325V dc battery supply and for variable dc-supply by
keeping output as 230Vrms.

Index Terms--Cascaded H-Bridge, Double carrier,
Fundamental RMS voltage, Optimum multilevel inverter, Phase
shift and Total harmonic distortion.

I. INTRODUCTION
ULTILEVEL converters are increasingly being
considered for high power applications because of their
ability to operate at higher output voltages while producing
lower levels of harmonic components in the switched output
voltages. Numerous industrial applications have begun to
require higher power apparatus in recent years. Some medium
voltage motor drives and utility applications require medium
voltage and megawatt power level. For a medium voltage grid,
it is troublesome to connect only one power semiconductor
switch directly. As a result, a multilevel power converter
structure has been introduced as an alternative in high power
and medium voltage situations. A multilevel converter not
only achieves high power ratings, but also enables the use of
renewable energy sources. Renewable energy sources such as
photovoltaic, wind, and fuel cells can be easily interfaced to a
multilevel converter system for a high power application[1-3].
Harmonic reduction in controlling a VSI(Voltage Source
Inverter) with variable amplitude and frequency of the output
voltage is of importance and thus the conventional inverters
which are referred to as two-level inverters have required

Shelly Vadhera is Asstt. Prof. with the Department of Electrical
Engineering, National Institute of Technology, Kurukshetra, Haryana,
136119, India (e-mail: shelly_vadhera@rediffmail.com).
S. Ganesh Sankar is M.Tech Stident with the Department of Electrical
Engineering, National Institute of Technology, Kurukshetra, Haryana,
136119, India (e-mail: noteyganesh@yahoo.com).

978-1-4244-7882-8/11/$26.00 2011 IEEE

increased switching frequency alongwith various PWM(Pulse
Width Modulation) switching strategies. In the case of high
power / high voltage applications, however, the two-level
inverters have some limitations to operate at high frequency
mainly due to switching losses and constriction of device
rating itself. Moreover, the semiconductor switching devices
should be used in such a manner as problematic series /
parallel combinations to obtain capability of handling high
power. Nowadays the use of multilevel approach is believed to
be promising alternative in such a very high power conversion
processing system. Advantages of this multilevel
approachinclude good power quality, good electromagnetic
compatibility (EMC), low switching losses, and high voltage
capability.
II. MULTILEVEL INVERTER
A. Multilevel Concept
The concept of multilevel converters has been introduced
since 1975. The term multilevel began with the three-level
converter [4]. Subsequently, several multilevel converter
topologies have been developed. However, the elementary
concept of a multilevel converter to achieve higher power is to
use a series of power semiconductor switches with several
lower voltage dc sources to perform the power conversion by
synthesizing a staircase voltage waveform. Capacitors,
batteries, and renewable energy voltage sources can be used as
the multiple dc voltage sources. Recent advances in power
electronics have made the multilevel concept practical. It is
evident that the multilevel concept will be a prominent choice
for power electronic systems in future years, especially for
medium-voltage operation. Multi-level inverters arethe
modification of basic bridge inverters. They arenormally
connected in series to form stacks of level.
The topological structure of multilevel inverter must cope
with the following points.
1) It should have less switching devices as far as possible.
2) It should be capable of enduring very high input voltage
such as HVDC transmission for high power applications.
3) Each switching device should have lower switching
frequency owing to multilevel approach.
Two well-known multilevel converter topologies are the
Neutral Point Clamped (NPC) inverter and Cascaded inverter.
One of the major problems in electric power quality is the
harmonic contents. There are several methods of indicating
Simulink based Optimization of SPWM
Multilevel Inverter with Phase Shift and Dual
Carrier at Each Level
Shelly Vadhera and S. Ganesh Sankar
M

the quantity of harmonic contents. The most widely used
measure is the Total Harmonic Distortion (THD) [5]. The
PWM techniques for multilevel inverters have been developed
very intensively in recent years. Many carriers based and
sinusoidal PWM (SPWM) [6] techniques for multilevel
inverters have been properly deduced from that of two-level
inverter.
The H-Bridge multilevel circuits with SPWM for inverter,
operating principle with switching functions is analyzed for
five to twenty five (odd) [7] levels SPWM inverter [8]. Level-
5 to 25 (odd levels) [9] SPWM inverter are simulated to
alleviate harmonic components of output voltage. By
observing the THD and fundamentalcomponent of different
levels the optimum [10] level of inverter is obtained.
B. Quarter-Wave Symmetric Multilevel Waveform
The optimized harmonic stepped waveform is assumed to
be the quarter-wave symmetric. The first half cycle of the
quarter-wave symmetric waveform is depicted in Fig.1

Fig. 1. First half cycle of the quarter-wave symmetric waveform.

Here
1,2,3are corresponding(X-Axis)firing angles

1,

2,

3..
and voltage levels(Y-axis) V
1,
V
2,
V
3
.
The output voltage level is zero from t = 0 to t =
1
. At
t =
1
, the output voltage level is changed from zero to +V
1
,
and from +V
1
to + (V
1
+V
2
) at t =
2
. The process will be
repeated until t = /2, and the output voltage level becomes
+V
1
+V
2
++V
(S-1)
+V
s
. Then, in the second quarter, the level
of output voltage will be decreased to +V
1
+V
2
++V
(S-1)
at t
= -
s
. The process will be repeated until t = -
1
and output
voltage becomes zero again. In the second half of the
waveform, the process will be repeated except the amplitude
of the dc sources change from positive to negative. Similarly
for the next period the same cycle is repeated.
C. Fourier series Analysis
The Fourier series analysis of a multilevel wave is followed
by given Fourier coefficient equations (1-3).

a

ft sint ut

foi ouu n (1)

a
n
0, for even n (2)

b
n
0, for all n (3)
Here,
ft V
out
t
For all n, the Fourier series is given by equation (4)

let


Hence,

ft a

sin nt (5)

Here,
a

f sin u

Finally, the Fourier series of the quarter-wave
symmetric parallel connected multilevel waveform is written
as follows:
v

cosn

sin nt
Where,
k
is the switching angles, which must satisfy the
following condition

Where,
sis the number of H-bridgecells.
nis odd harmonic order.
E is the amplitude of dc voltages.
D. Total Harmonic Distortion (THD) Calculation
The total harmonic distortion (THD) is mathematically
given by
TBB

Where,
H
1
is the amplitude of the fundamental component, whose
Frequency is
0.
H
n
is the amplitude of the nth harmonic at frequency n
0.

The amplitude of the fundamental and harmonic
components of the quarter-wave symmetric multilevel
waveform can be expressed by equation (8).

(8)
0 2 4 6 8 10 12
0
1
2
3
4
5
6
trigger points
v
o
l
t
a
g
e
(
v
)


Theoretically, to get exact THD, infinite harmonics need to
be calculated. However, it is not possible in practice. The
acceptance of the n value in the multilevel inverters depends
upon how precise the THD is needed. Whereas upto n=63 is
reasonably accepted.
III. SIMULATION MODEL DIAGRAM FOR MULTILEVEL
INVERTER WITH A DUAL CARRIER IN EACH LEVEL
A. Seven Level Cascaded H-Bridge
The model for seven level H-Bridge [11] as shown in Fig.2.
isselected as the base model to simulate the remaining levels
upto 25 multilevel inverters.
Fig.2. Seven level single phase cascaded H-bridge.

The simulation diagram of trigger pulse generation for
seven level inverter for a above cascaded H-bridge in case of
dual carrier in each level is shown from Fig.3.1 to Fig 3.3. The
single carrier in each level is simply obtained by
disconnecting repetitive part.

Fig.3.1. Trigger pulse generation for seven level multilevel inverter with a
90
0
phase shift for first H-bridge.

Fig.3.2. Trigger pulse generation for seven level multilevel inverter with a
90
0
phase shift for second H-bridge.
4 Conn1
3 Conn2
2 Conn4
1 Conn3
g a
k
Gto9
g a
k
Gto8
g a
k
Gto7
g a
k
Gto6
g a
k
Gto5
g a
k
Gto4
g a
k
Gto3
g a
k
Gto2
g a
k
Gto11
g a
k
Gto10
g a
k
Gto1
g a
k
Gto
DC Vol tage Source2
DC Vol tage Source1
DC Vol tage Source
12 I62
11 I52
10 I32
9 I42
8 I61
7 t51
6 I41 5 I31
4 I12
3 I22
2 I21 1 I11
2
t21
1
t11
Sine Wave2
Si ne Wave
Saturati on1
Saturati on
Repeati ng
Sequence
Interpolated2
-1
Gai n2
-1
Gai n
Add7
Add6
Add4
Add2
Add1
Add
3.75deg
2
t41
1
t31
Si ne Wave3
Si ne Wave1
Saturati on3
Saturati on2
Repeati ng
Sequence
Interpol ated3
Repeati ng
Sequence
Interpol ated1
-1
Gai n3
-1
Gai n1
Add9
Add8
Add5
Add3
Add11
Add10

Fig.3.3. Trigger pulse generation for seven level multilevelinverter with a
90
0
phase shift for third H-bridge.

The reference sine wave with peak voltage of
3V,carrierwave levels[(0 1 0),(1 2 1) and (2 3 2) trigger pulse
generation for a seven level inverter are shown in Fig. 4.

Fig.4. Seven level inverter trigger pulse generaiton with reference wave
and different levels of carrier wave.

Similarly the results are obtained for 3.75
0
phase shift and
phase shift from 7.5
0
to 90
0
with a incremnet of 7.5
0
. The
results obtained had shown marginal difference for all cases
hence forth waveforms are represented for 90
0
phase shift only
in this paper .

Fig. 5. Simulation diagram for seven level H-bridge singlephase inverter.

However referring the generalized [12] structures of
multilevel inverter we can get the basic idea about pd (phase
disposition) [13], phase shift [14] and knowledge about [15],
[16] cascaded H-bridge[17].

Fig.6. Output waveforms of a seven level inverter for phase shift of 90
0
.
IV. OPTIMUM MULTILEVEL INVERTER
The multilevel concept was applied from levels 5 to 25
and optimum multilevel H-bridge inverter was found at 21
st

level. The Fig.7 represents the optimum multilevel inverter
simulation diagram whereas Fig.8 shows the waveforms for
output voltage, fundamental voltage and maximum voltage
values. Three phase output waveform for 21 level inverter is
shown in Fig.9.


2
t61
1
t51
Si ne Wave3
Si ne Wave1
Saturati on3
Saturati on2
Repeati ng
Sequence
Interpol ated3
Repeati ng
Sequence
Interpol ated1
-1
Gai n3
-1
Gai n1
Add9
Add8
Add5
Add3
Add11
Add10
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
0
2
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
0
2
V
o
l
t
a
g
e
(
v
)
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
0
2
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
0
2
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
0
2
Time(sec0
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-2
0
2
f(u) vmsin9wt0
t 11
t 21
t 31
t 41
t 51
t 61
tri ggeri ng pulse genrerator
si nu-pwm for phase-c[3.75]
v
+
-
Voltage Measurement
s
ig
n
a
l
T
H
D
Total Harmonic
Di storsi on
I
1
1
I
2
1
I
2
2
I
1
2
I
3
1
I
4
1
t
5
1
I
6
1
I
4
2
I
3
2
I
5
2
I
6
2
C
o
n
n
4
C
o
n
n
2
C
o
n
n
3
C
o
n
n
1
Subsystem
Scope
signal rms
RMS
s
ig
n
a
l
m
a
g
n
itu
d
e
a
n
g
le Fourier
0
Display1
0
Di splay
Cl ock
0 0.01 0.02 0.03 0.04 0.05 0.06
-300
-200
-100
0
100
200
300
Time(sec)
V
o
l
t
a
g
e
(
v
)


Fig.7. Optimum multilevel inverter for twenty one level.

Each sub blocks in first column of Fig.7 are for trigger
pulse generation and second blocks corresponds to H-bridge
cascaded blocks.


Fig. 8. Twenty one level output voltage with fundamental and maximum
voltage value.



Fig.9. Three phase output waveforms for twenty one level inverter.

Further in this paper different THD values and fundamental
RMS values for the fixed input voltage of 325V dc for both
single and dual carrier in each level along with modulation
index value of 1[18] have been obtained which are as shown
in TablesIand II. The paper also explores the THD values in
case of variable dc-supply in order to get the constant 230V
RMS voltage for dual carrier at each level and is framed in
Table III.

TABLE I
Vrms AND THD VALUES FOR SINGLE CARRIER AT EACH LEVEL.



TABLE II
Vrms AND THD VALUES FOR DUAL CARRIER AT EACH LEVEL WITH
90
0
PHASE SHIFT.












f(u) vmsi n9wt3
t11
t21
t31
t41
t51
t71
t81
t61
ni nel evel
v
+
-
Va
s
ig
n
a
l
T
H
D
Total Harmoni c
Di st orsi on3
t11
t21
t22
t12
Conn2
Conn1
Subsystem7
21
11
12
41
31
42
32
61
51
62
52
22
Conn1
Conn3
Conn2
Subsystem5
21
11
12
41
31
42
32
61
51
62
52
22
Conn1
Conn3
Conn2
Subsystem4
t 91
t101
t111
t121
t131
t141
t151
t161
Subsyst em3
21
11
12
41
31
42
32
61
51
62
52
22
Conn1
Conn3
Conn2
Subsystem2
t171
t181
t191
t201
Subsystem1
Scope1
Scope
signal rms
RMS
s
ig
n
a
l
m
a
g
n
itu
d
e
a
n
g
le Fouri er3
0
Di spl ay3
0
Di spl ay1
Cl ock3
0 0.01 0.02 0.03 0.04 0.05 0.06
-300
-200
-100
0
100
200
300
Time(sec)
V
o
l
t
a
g
e
(
v
)
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
-300
-200
-100
0
100
200
300
Time(sec)
V
o
l
t
a
g
e
(
v
)
Level V
RMS
(V) %THD
5 252.3 25.070
7 249.0 17.070
9 245.8 12.970
11 243.2 10.460
13 241.0 8.760
15 239.3 7.598
17 237.4 6.600
19 235.6 5.888
21 233.9 5.379
23 232.3 4.876
25 230.8 4.463
LEVEL V
RMS
(V) %THD
5 243.4 21.76
7 204.5 21.28
9 230.5 11.74
11 228.1 9.141
13 225.5 7.673
15 223.7 6.419
17 221.3 5.872
19 219.8 5.159
21 218.3 4.705
23 216.1 4.329
25 162.3 11.31

TABLE III
SELECTION OF INPUT DC SUPPLY VOLTAGE.



Fig.10. The output rms voltage v/s different multilevelinverterfor single and
dual carrier in each level with a constant input supply 325V.



Fig.11. The % THD v/s different multilevelinverter for single anddouble
carrier in each level with a constant input supply with 325V .


Fig.12. The DC- battery volatge required to maintain the constant output
voltage of 230Vrms in different multilevel inverters with a dual carrier at each
level.
V. CONCLUSION
The simulations have been carried for inverters from five
level to twenty five level. The important observations have
been made for single carrier at each level. By analyzing Table
I it is found that from level 5 to 21 the %THD values are
decreasing but those are more than 5%, which is undesirable
as per IEEE standard. It is further observed that at level
23
rd
and 25
th
level the THD values are even better and those
values are less than 5%, which are at par with IEEE standards.
Regarding the fundamental RMS voltage, it is observed that
at the 5
th
level the RMS voltage value is 252.3V. But the
desired value is to be 230 volts. So when the level is increased
from 5 to 25it is observed that the fundamental RMS value is
decreasing and by observing the Table I one can note that at
level 25
th
level the fundamental RMS voltage value is 230.8V,
which is near to the desired value, thus this is considered as
the optimum value.
If the THD values and the fundamental RMS values are
considered both together then one can see that at 23
rd
level the
THD value is 4.876% and the fundamental RMS voltage is
232.3V while at level 25 these values are 4.463% and 230.8V
respectively. So it is concluded that although in both level 23
rd

and 25
th
level values are less than 5% THD, but if RMS
voltage is taken into consideration the 25
th
level is rated as the
optimum level for inverter.
Further important observations have been made in case of
dual carrier at each level from Table II. The %THD values
decreases as compared to single carrier case. Whereas from
RMS voltage point of view a little decrement is observed that
can be compensated by increasing the input side dc-supply
voltage. For a constant dc-voltage of 325V supply the rms
output voltage of 230.5V is obtained at ninth level inverter but
here the %THD value is 11.74 so one can conclude that from
fundamentalrms voltage point of view ninth level inverter is
optimum inverter similarly from %THD point of view the
levels 21 and 23 are optimum inverters as shown in Table II.
5 10 15 20 25
160
180
200
220
240
260
INVERTER LEVEL
R
M
S

V
O
L
T
A
G
E
(
v
)
Single carrier in each level
Double Carrier in each level
5 10 15 20 25
0
5
10
15
20
25
30
INVERTER lEVEL
%
T
H
D
Single carrier in each level
Double Carrier in each level
5 10 15 20 25
300
350
400
450
500
INVERTER LEVEL
D
C

B
A
T
T
E
R
Y

V
A
L
U
E
(
V
) LEVEL DC-BATTERY(V) %THD
5 310 21.76
7 365 21.28
9 325 11.74
11 328 9.141
13 332 7.673
15 335 6.419
17 338 5.872
19 340 5.159
21 342 4.705
23 345 4.329
25 460 11.31

When both %THD and rms fundamental voltage values are to
be considered nearer to 230V rms and less than 5%
respectively then the input dc-supply voltage value increased
to 342V and 345V for 21
st
and 23
rd
level inverters respectively
as shown in Table III and Fig.11. So the 21
st
level inverter
with a dc-supply of 342V is giving the RMS output voltage
nearer to 230V and %THD is 4.705. According to the IEEE
standards these values are within the reasonable limits so
twenty first level inverter is optimum multilevel inverter. This
paper will help the researchers in selecting the multilevel
inverters with better THD values and fundamental RMS
voltages and henceforth will find wide applications in areas
where multilevel inverter are used.
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