Professional Documents
Culture Documents
by
Sheng-Yang Yu
2010
The Thesis Committee for Sheng-Yang Yu
Certifies that this is the approved version of the following thesis:
Isolated Multiple-Input Single Ended Primary Inductor Converter
(SEPIC) and Applications
APPROVED BY
SUPERVISING COMMITTEE:
Alexis Kwasinski
William Mack Grady
Supervisor:
Isolated Multiple-Input Single Ended Primary Inductor Converter
(SEPIC) and Applications
by
Sheng-Yang Yu, B.S.
Thesis
Presented to the Faculty of the Graduate School of
The University of Texas at Austin
in Partial Fulfillment
of the Requirements
for the Degree of
Master of Science in Engineering
The University of Texas at Austin
May 2010
iv
Acknowledgements
This thesis is a milestone of my two-year graduate life at The University of Texas
at Austin. First, I would like to thank my supervisor, Dr. Alexis Kwasinski, who advises
and enlightens me in the field of power electronics. I also want to thank Ruichen Zhao
and Chimaobi Onwuchekwa, who are the members of the power electronics research
group (PERG). Their offering of valuable discussions has significantly contributed to my
research and thesis. Also, I want to express my deeply appreciation to my friend, Yi-Han
Lin, who spends her precious time to peer proofreading my thesis.
Last, I would like to thank my parents for giving me every support I need to
fulfill my dream, and my wife, Yi-Chun Kao, who dedicates to my family with her
selfless love. I would to share all the happiness of my achievements that I have
accomplished with my upcoming baby.
May 6, 2010
v
Abstract
Isolated Multiple-Input Single Ended Primary Inductor Converter
(IMISEPIC) and Applications
Sheng-Yang Yu, M.S.E
The University of Texas at Austin, 2010
Supervisor: Alexis Kwasinski
This document explores the isolated multiple-input single ended primary inductor
converter (IMISEPIC) and discusses its application. This thesis proposes the following
control methods such as current feed-forward control, voltage feedback control and
maximum power point control to analyze the IMISEPIC. Zero-ripple technique is also
applied to IMISEPIC in order to increase the converters life-time. Design strategy and
concerns about the IMISEPIC are also presented, and simulations and circuit experiments
are conducted to verify the analysis. Finally, the discussion about control limitation is
used for future design consideration.
vi
Table of Contents
List of Tables ....................................................................................................... viii
List of Figures ........................................................................................................ ix
Chapter 1: Introduction ............................................................................................1
Chapter 2: The Isolated Multiple-Input Single Ended Primary Inductor Converter
(IMISEPIC) .....................................................................................................3
2.1 The IMISEPIC Circuit Operation Analysis ...........................................3
2.2 Different Driving Strategy for The I2ISEPIC ........................................9
2.3 The I2ISEPIC with Coupled Input Inductors.......................................10
Chapter 3: Control Methods and Zero-Ripple Current Technique of IMISEPIC ..12
3.1 Current Feed-forward Control .............................................................13
3.2 Voltage Feedback Control ...................................................................14
3.3 Ripple Current Correction (RCC) Control ...........................................15
3.4 Zero-Ripple Technique ........................................................................17
Chapter 4: Simulations ...........................................................................................20
4.1 The I2ISEPIC Modeling ......................................................................20
4.2 The Current Feed-forward Controller ..................................................21
4.3 The I2ISEPIC with Current Feed-forward Control .............................22
4.4 The Voltage Feedback Controller ........................................................27
4.5 The I2ISEPIC with Voltage Feedback Control ...................................28
4.6 The I2ISEPIC with Voltage Feedback and Current Feed-forward Control
..............................................................................................................30
4.7 Ripple Current Correlation (RCC) Controller .....................................32
4.8 The I2ISEPIC with Ripple Current Correlation and Voltage Feedback
Control .................................................................................................33
4.9 The I2ISEPIC with Zero-Ripple Technique ........................................37
Chapter 5: Circuit Design and Experiments ..........................................................39
5.1 The IMISEPIC Circuit Design .............................................................39
vii
5.2 The Efficiency of IMISEPIC ...............................................................41
5.3 The I2ISEPIC with Current Feed-forward Control .............................46
5.4 The I2ISEPIC with Voltage Feedback Control ...................................48
5.5 The I2ISEPIC with Current Feed-forward and Voltage Feedback Control
..............................................................................................................50
5.6 The I2ISEPIC with Ripple Current Correlation and Voltage Feedback
Control .................................................................................................52
Chapter 6: Conclusions ..........................................................................................55
Appendix ................................................................................................................57
References ..............................................................................................................61
Vita .......................................................................................................................65
viii
List of Tables
Table 1: The I2ISEPIC Efficiency Measurement ..................................................43
Table 2: The I2ISEPIC Efficiency Measurement with IGBTs ..............................43
ix
List of Figures
Figure 1: Isolated Multi-input SEPIC ......................................................................2
Figure 2: The I2ISEPIC ...........................................................................................3
Figure 3: The Remodeled I2ISEPIC ........................................................................4
Figure 4: Duty Cycles of S
1
and S
2
..........................................................................4
Figure 5: A Different Duty Cycles Driving Strategy ...............................................9
Figure 6: The I2ISEPIC with Coupled Input Inductors .........................................10
Figure 7: The I2ISEPIC with Remodeled Coupled Input Inductors ......................11
Figure 8: An Example of Multiple-input System ..................................................12
Figure 9: The I2ISEPIC with Current Feed-forward Control ................................13
Figure 10: The I2ISEPIC with Voltage Feedback Control ....................................14
Figure 11: An Example of PVs I-V and P-V Curve [12] .......................................15
Figure 12: An Active Filter for the I2ISEPIC ........................................................17
Figure 13: A Coupled Filter for the I2ISEPIC .......................................................18
Figure 14: The I2ISEPIC Model ............................................................................20
Figure 15: The Current Feed-forward Controller Block Diagram .........................21
Figure 16: Simulation Model of the I2ISEPIC with Current Feed-forward Control22
Figure 17: Small Signal Gain of i
L1
/FF ..................................................................23
Figure 18: Simplis Simulation Circuit for Frequency Response ...........................23
Figure 19: Loop Gain of I2ISEPIC with Current Feed-forward Control...............24
Figure 20: Startup Transient of I2ISEPIC with Current Feed-forward Control ....25
Figure 21: Steady State of I2ISEPIC with Current Feed-forward Control ............25
Figure 22: Load Response of I2ISEPIC with Current Feed-forward Control .......25
Figure 23: Dynamic Response of I2ISEPIC with Current Feed-forward Control .26
x
Figure 24: The Voltage Feedback Controller Block Diagram ...............................27
Figure 25: Simulation Model of I2ISEPIC with Voltage Feedback Control .........28
Figure 26: Startup transient of I2ISEPIC with Voltage Feedback Control ...........29
Figure 27: Load Response of I2ISEPIC with Voltage Feedback Control .............29
Figure 28: Dynamic Response of I2ISEPIC with Voltage Feedback Control .......29
Figure 29: Simulation Model of I2ISEPIC with Voltage Feedback Control and
Current Feed-forward Control ..........................................................30
Figure 30: Startup Transient of I2ISEPIC with Voltage Feedback Control and Current
Feed-forward Control........................................................................31
Figure 31: Steady State of I2ISEPIC with Voltage Feedback Control and Current
Feed-forward Control........................................................................31
Figure 32: Load Response of I2ISEPIC with Voltage Feedback Control and Current
Feed-forward Control........................................................................31
Figure 33: Simulation Block Diagram of Ripple Current Correlation Controller .32
Figure 34: I-V and P-V Curves of the Photovoltaic Simulation Model ................33
Figure 35: Voltage Feedback Controller Block .....................................................34
Figure 36: Simulation Model of I2ISEPIC with Voltage Feedback Control and RCC
Control ..............................................................................................35
Figure 37: Startup Transient of I2ISEPIC with Voltage Feedback Control and RCC
Control ..............................................................................................36
Figure 38: Steady State of I2ISEPIC with Voltage Feedback Control and RCC
Control ..............................................................................................36
Figure 39: The I2ISEPIC without Zero-Ripple Technique ....................................37
Figure 40: The I2ISEPIC with Zero-Ripple Technique .........................................38
Figure 41: Simulation Result of I2ISEPIC without Zero-Ripple Technique .........38
xi
Figure 42: Simulation Result of I2ISEPIC with Zero-Ripple Technique ..............38
Figure 43: Simulation Result of I2ISEPIC with Real Transformer Model ...........40
Figure 44: Simulation Circuit of I2ISEPIC with Real Transformer Model...........40
Figure 45: Transformer Winding and Flux Intensity Relationship ........................40
Figure 46: The I2ISEPIC Efficiency Test Circuit..................................................42
Figure 47: Driving Signal Waveform of I2ISEPIC ...............................................42
Figure 48: The I2ISEPIC Circuit with MOSFET in Series ...................................45
Figure 49: Current and Driving Waveforms of Improved I2ISEPIC Circuit ........45
Figure 50: Waveforms of Improved I2ISEPIC Circuit ..........................................45
Figure 51: Circuit Diagram of I2ISEPIC with Current Feed-forward Control ......46
Figure 52: Steady State Waveform of I2ISEPIC with Current Feed-forward Control
...........................................................................................................47
Figure 53: Load Response Waveform of I2ISEPIC with Current Feed-forward
Control ..............................................................................................47
Figure 54: Dynamic Response Waveform of I2ISEPIC with Current Feed-forward
Control ..............................................................................................47
Figure 55: Circuit Diagram of I2ISEPIC with Voltage Feedback Control ............48
Figure 56: Startup Waveform of I2ISEPIC with Voltage Feedback Control ........49
Figure 57: Load Response Waveform of I2ISEPIC with Voltage Feedback Control
...........................................................................................................49
Figure 58: Dynamic Response Waveform of I2ISEPIC with Voltage Feedback
Control ..............................................................................................49
Figure 59: Steady State Waveform of I2ISEPIC with Current Feed-forward and
Voltage Feedback Control ................................................................50
xii
Figure 60: Load Response Waveform of I2ISEPIC with Current Feed-forward and
Voltage Feedback Control ................................................................50
Figure 61: Dynamic Response Waveform of I2ISEPIC with Current Feed-forward
and Voltage Feedback Control..........................................................51
Figure 62: Circuit Diagram of I2ISEPIC with RCC and Voltage Feedback Control53
Figure 63: Steady State Waveform of I2ISEPIC with RCC and Voltage Feedback
Control ..............................................................................................54
Figure a1: State Variable Waveforms ....................................................................58
Figure a2: Mathcad Symbolic Solving Function for Solving I
L1,min
, I
L2,min
and I
Lm,min
...........................................................................................................60
1
Chapter 1: Introduction
The distributed generation (DG) was introduced by Edison in the 1880s [1]. With
this technique, a small power plant was built to generate direct current (DC) for lighting.
However, this low-voltage DC system (110V
dc
) can only supply the nearby loads because
of the high transmission losses. Also, no voltage transformation can easily be applied.
Therefore, this concept was displaced by traditional alternating current (AC) power plant
[2] in the late 1880s due to the disadvantages discussed above. AC power plants are still
the major power source in most countries, but the majorities of these power plants are not
renewable and in associated with significant pollution. Furthermore, CO
2
emissions from
traditional AC power plants may heighten concerns about global warming [3]. In
comparison with such power plants, DG power sources are more environmentally
friendly. Therefore, DG techniques have begun being reconsidered in recent years.
Renewable energy sources such as photovoltaic arrays (PVs), wind turbines and
fuel cells are DG sources [4]. Unlike traditional AC power systems, DG sources can
usually be installed close to the load and can be more customized. A multiple-input
converter (MIC) is a technique for integrating different DG sources [5]. The most
attractive benefit of MIC is that it is cost-efficiency. In general, MIC has fewer
components due to the common stage [6]. The multiple-input single ended primary
inductor converter (SEPIC) is a good current-feed converter and discussed thoroughly in
[7]. However, multiple outputs or higher output voltage may be required in some
applications. In these applications, the central inductor is replaced by a coupled-inductor
[8], which is the isolated multiple-input SEPIC (IMISEPIC), shown in Figure1. In
Chapter 2, the circuit operation of IMISEPIC is analyzed, a different driving strategy is
discussed, and a different form of IMISEPIC is presented. The applications, different
2
control methods, and zero-ripple technique of IMISEPIC are discussed in Chapter 3.
Chapter 4 contains descriptions of simulations conducted by Simplis/SiMetrix and
Matlab/Simulink to support the discussion in Chapters 2 and 3. In Chapter 5, different
control methods and the zero-ripple technique are applied to the IMISEPIC, and the
converter efficiency is tested. Finally, the study limitations are discussed in Chapter 6.
Figure 1: Isolated Multi-input SEPIC
3
Chapter 2: The Isolated Multiple-Input Single Ended Primary Inductor
Converter (IMISEPIC)
2.1 THE IMISEPIC CIRCUIT OPERATION ANALYSIS
To simplify the analysis, an isolated 2-input single ended primary inductor
converter (I2ISEPIC) is considered in Figure 2. As discussed in [6], the input-cell
switches of the multiple-input SEPIC have to be forward conducting and bidirectional
blocking (FCBB). Therefore, a FCBB component (such as a diode) has to be placed in
series with a bidirectional conducting switch (such as a metal-oxide semiconductor field-
effect transistor, or MOSFET), as shown in Figure 2. Figure 3 shows the I2ISEPIC with
the ideal transformer (or coupled inductor) model, where L
m
represents the magnetizing
inductance of the transformer. The turns ratio of the transformer is assumed to be N
p1
:N
s1
= n. Assuming the circuit is operating in a continuous conduction mode (CCM), V
in1
>
V
in2
, and the duty cycle of S
1
is smaller than that of S
2
, as shown in Figure 4. Under these
assumptions, there are three possible operation states as follows:
State 1: S
1
and S
2
are both turned on.
State 2: S
1
is turned off, and S
2
is turned on.
State 3: S
1
and S
2
are both turned off.
Figure 2: The I2ISEPIC
4
Figure 3: The Remodeled I2ISEPIC
Figure 4: Duty Cycles of S
1
and S
2
5
Since V
in1
> V
in2
, diode D
2
is reversed bias in state 1. Also, no energy transfers
from the input to the output, and diode D
out
is also reversed bias. The dynamic equations
in state 1 are shown in (1) with the assumption of ideal diode models.
=
=
=
=
+ =
=
R
v
dt
dv
C
i
dt
dv
C
i i
dt
dv
C
v
dt
di
L
v v V
dt
di
L
V
dt
di
L
out out
out
L
Cs
s
Lm L
Cs
s
Cs
Lm
m
Cs Cs in
L
in
L
2
2
2
2
1
1
1
1 2 2
2
2
1
1
1
(1)
In state 2, there is still no energy transfer from the input to the output and D
2
is
forward bias. The dynamic equations in state 2 are shown in (2).
=
=
=
=
=
+ =
R
v
dt
dv
C
i i
dt
dv
C
i
dt
dv
C
v
dt
di
L
V
dt
di
L
v v V
dt
di
L
out out
out
Lm L
Cs
s
L
Cs
s
Cs
Lm
m
in
L
Cs Cs in
L
1
2
2
1
1
1
2
2
2
2
2 1 1
1
1
(2)
In state 3, the energy is transferred to the output via the transformer. The primary
transformer current, i
p
, is equal to the sum of i
L1
, i
L2
, and i
Lm
. With transformer turns ratio,
n, the relationship between i
p
and i
s
is n(i
p
) = i
s
. Since diode D
out
is forward biased at this
6
moment, we have the voltage relationship of the transformer as v
NP1
= n(v
NS1
) = n(v
out
).
Having the voltage and current relationship connect the two sides of the transformer, the
dynamic equations in state 3 are shown in (3).
( )
+ + =
=
=
=
=
=
R
v
i i i n
dt
dv
C
i
dt
dv
C
i
dt
dv
C
nv
dt
di
L
nv v V
dt
di
L
nv v V
dt
di
L
out
Lm L L
out
out
L
Cs
s
L
Cs
s
out
Lm
m
out Cs in
L
out Cs in
L
2 1
2
2
2
1
1
1
2 2
2
2
1 1
1
1
(3)
7
Define ( )
=
off. is S when , 0
on. is S when , 1
1
1
1
t q , ( )
=
off. is S when , 0
on. is S when , 1
2
2
2
t q , and
1 2 2
q q q
eff
= ,
then the switching dynamic equations of I2ISEPIC can be written as (4).
The steady-state equilibrium point can be approached by assuming all the
variables in (4) to be constant and then applying the fast average model [9] to q
1
and q
2
.
Duty cycles D
1
, D
2
and D
2eff
are defined in (5), where T is the switching period. The
approached equilibrium is shown in (6), which is very similar to (8) in [7], the only
difference is the turns ratio factor, n.
( ) ( )( )
( ) ( )( )
( )
( ) ( )
( ) ( )
( ) ( ) | |
+ + =
+ =
+ + =
+ =
+ =
+ =
R
v
i i i n q
dt
dv
C
i i q i q
dt
dv
C
i q i i q
dt
dv
C
nv q v q v q
dt
di
L
nv v q v v q V
dt
di
L
nv v q v v q V
dt
di
L
out
Lm L L
out
out
Lm L eff L eff
Cs
s
L Lm L
Cs
s
out Cs eff Cs
Lm
m
out Cs Cs Cs in
L
out Cs Cs Cs eff in
L
2 1 2
1 2 2 2
2
2
1 1 2 1
1
1
2 2 2 1 1
2 2 1 2 1 2
2
2
1 2 2 1 2 1
1
1
1
1
1
1
1
1
(4)
( )
( )
=
=
=
}
}
1 2 2
0
2 2
0
1 1
1
1
D D D
dt t q
T
D
dt t q
T
D
eff
T
T
(5)
8
( )
( )
( )
(
(
(
(
(
(
(
(
(
(
(
(
=
(
(
(
(
(
(
(
(
2
2 2 1 1
2
1
2
2
2
1
, 2
, 1
,
,
,
1
1
1
2
1
D n
V D V D
V
V
nR
v
R D n
v D
R D n
v D
v
v
v
i
i
i
in eff in
in
in
out
out eff
out
out
eq Cs
eq Cs
eq L
eq L
eq L
m
(6)
However, the result in (6) is true when the ripple current and voltage are small
enoughthat is, when they have. high frequency or inductors and capacitors have large
inductance and capacitance. These requirements may not be achieved in the circuit
implementation, which results in a large error in the equilibrium point of i
L1
and i
L2
. A
better approach in finding the equilibrium point of i
L1
and i
L2
discussed in the appendix,
has the result in (7), which gives very helpful information in designing the I2ISEPIC.
( )
( )
( )
( )
( )
(
(
(
(
(
(
(
(
(
(
(
(
+
+ +
+
+ +
=
(
(
(
(
(
(
(
(
2
2 2 1 1
2
1
2 1
1 2 2 1 1 2 1
2
2
2 1
1 2 2 1 2 2 1
2
1
, 2
, 1
,
,
,
1
2 1
2 1
2
1
D n
V D V D
V
V
nR
v
L L L
L L L L L L T V D D
R D n
v D
L L L
L L L L L L T V D D
R D n
v D
v
v
v
i
i
i
in eff in
in
in
out
m
m m in eff out eff
m
m m in eff
out
out
eq Cs
eq Cs
eq L
eq L
eq L
m
(7)
9
2.2 DIFFERENT DRIVING STRATEGY FOR THE I2ISEPIC
If the control strategy is changed to D
1
and D
2,
which are not turned on at the
same time, as shown in Figure 5, then the conditions that V
in1
> V
in2
and that the duty
cycle of S
1
is smaller than that of S
2
are no longer required here, which gives more
freedom to the input sources. In other words, V
in1
= V
in2
and V
in1
< V
in2
are allowed here.
With this control strategy, we can ensure that both input sources are utilized. This control
strategy can also be applied in a multiple-input buck-boost converter, multiple-input
flyback converter, and multiple-input uk converter.
Figure 5: A Different Duty Cycles Driving Strategy
10
2.3 THE I2ISEPIC WITH COUPLED INPUT INDUCTORS
The idea behind using MIC is to reduce component counts as many as possible.
An IMISEPIC with coupled-input inductors is proposed here in Figure 6. Two input
inductors have been combined into one coupled-inductor, T
in
. With the coupled input
inductors, the converter size is also minimized. The dot position should be noticed to
prevent T
in
from acting like a transformerthat is, from transferring energy from V
in1
to
V
in2
or from V
in2
to V
in1
.
Analysis is conducted by using a real transformer model with leakage inductance
both on the primary and on the secondary sides (L
rp
and L
rs
) of T
in
, as shown in Figure 7,
where L
m2
is the magnetizing inductance of T
in
. To simplify the analysis, the turns ratio of
T
in
is assumed to be 1. The assumption that V
in1
> V
in2
and that the duty cycle of S
1
is
smaller than that of S
2
still hold. Overall dynamic equations are shown as (8). By
assuming all the variables in (8) are constants and then applying (5) to the model, the
voltage transfer ratio of I2ISEPIC with coupled-input inductors is the same as that of the
original I2ISEPIC converter.
Figure 6: The I2ISEPIC with Coupled Input Inductors
11
Figure 7: The I2ISEPIC with Remodeled Coupled Input Inductors
( ) ( )( )
( ) ( ) ( )( )
( )
( ) ( )
( ) ( )
( ) ( ) | |
+ + =
+ =
+ + =
+ =
+ + =
=
+ =
R
v
i i i n q
dt
dv
C
i i q i q
dt
dv
C
i q i i q
dt
dv
C
nv q v q v q
dt
di
L
nv v q v v q v v q
dt
di
L V V
dt
di
L
i i i
nv v q v v q
dt
di
L V
dt
di
L
out
Lm in in
out
out
Lm in eff in eff
Cs
s
in Lm in
Cs
s
out Cs eff Cs
Lm
m
out Cs Cs Cs eff Cs Cs
in
rp in in
in
rs
in in L
out Cs Cs Cs eff
in
rp in
L
m
m
m
2 1
1 2
1 2
1 2
2 1 2
1 2
2
2 2
2
2
1 1
1
1
2 2 2 1 1
1 2 2 1 2 1 2 1 2 1
1 2 2 1 2 1 2
1
1
1
1
1
1
(8)
12
Chapter 3: Control Methods and Zero-Ripple Current Technique of
IMISEPIC
When multiple sources are applied with a MIC, a consequent problem is to
control the energy flow [10]. In other words, some sources will be utilized as the first
sources, and some will be utilized as second sources. Figure 8 shows an example of a
multiple-input system. Usually, we will use PVs and wind turbines as primary sources
and fuel cells and power grid as second sources in such a system to get full use of the
clean and renewable energies. To meet the need of using renewable energies as the
primary source, some control strategies are needed for adjusting the energy flows from
each source. Maximum power point tracking (MPPT) techniques have been developed to
maximize the utility of using PVs. Current feed-forward control and voltage feedback
control [11] can be applied in this system to control the secondary source.
Figure 8: An Example of Multiple-input System
13
3.1 CURRENT FEED-FORWARD CONTROL
A block diagram including the I2ISEPIC with a current feed-forward control
system is shown in Figure 9. The output current of V
in1
has been sensed and compared
with a reference voltage (V
ref
). By comparing the compensated signal with a fixed
frequency sawtooth waveform, a duty cycle can be generated to reach the desired input
current. In other words, if the input current, which is transferred to a voltage signal, is
lower than the reference voltage, the signal to the non-inverting input of the comparator
will be increased. Therefore, a larger duty is generated. Base on the result in (7), a larger
duty results in a higher input current.
Figure 9: The I2ISEPIC with Current Feed-forward Control
14
3.2 VOLTAGE FEEDBACK CONTROL
Voltage feedback control operates with a similar concept as current feed-forward
control. However, a transformer is used to isolate the primary side and secondary side in
the IMISEPIC. Therefore, the compensation block output cannot directly connect to the
non-inverting input of the comparator. Thus, an isolated component is required for this
application. An optocoupler is applied as an isolated component here. Based on the input-
output relation in (7), a negative feedback control is applied to the I2ISEPIC, as shown in
Figure 10.
Figure 10: The I2ISEPIC with Voltage Feedback Control
15
3.3 RIPPLE CURRENT CORRECTION (RCC) CONTROL
PVs have I-V and P-V relationships shown in Figure 11 [12]. Based on the
characteristics, many MPPT techniques [13] have been investigated. Compared to other
MPPT techniques, RCC control is a low-cost, simple, and analog solution, and it fits
perfectly with DC-DC converter applications. Therefore, RCC control is chosen here.
Figure 11: An Example of PVs I-V and P-V Curve [12]
The PVs I-V relationship can be expressed as (9), where A, B, and I
sc
are positive
constants (where incident solar energy is fixed) [14]. The maximum power point occurs
at (P
pv
/V
pv
) = 0 when there are not multiple local maxima. By chain rule, (P
pv
/V
pv
) =
0 is equivalent to (P
pv
/t)(V
pv
/t) = 0 [15], and the sign of (P
pv
/V
pv
) determines the
16
sign of P
pv
V
pv
(10). If V
pv
is smaller than the voltage at the maximum power point,
V
pv,mpp
, (P
pv
/V
pv
) will be greater than zero. But if V
pv
is greater than V
pv,mpp
, (P
pv
/V
pv
)
will be negative. The isolated SEPIC converter has an equivalent load on the input side
(the output side of the PVs), shown in (11), which necessitates increasing the duty result
in the increasing of the load line slope (R
equiv
) in Figure 7that is, decreasing V
pv
.
Therefore, (12) is applied as the RCC control law.
( ) 1 I =
pv
BV
sc pv
e A I (9)
2
' '
|
|
.
|
\
|
c
c
|
|
.
|
\
|
c
c
=
c
c
c
c
|
|
.
|
\
|
c
c
=
c
c
c
c
=
t
V
V
P
t
V
t
V
V
P
t
V
t
P
V P
pv
pv
pv pv pv
pv
pv pv pv
pv pv
(10)
( )
( )
( )
load
out
out
in
in
equiv
R
D
D n
D n
D
I
D
D n
V
I
V
R
2
2 2
1
1
1
= = (11)
( )
}
c
c
c
c
= dt
t
V
t
P
k t d
pv pv
(12)
17
3.4 ZERO-RIPPLE TECHNIQUE
Many converters, such as buck, boost, buck-boost, SEPIC, forward and flyback
converters, and etc., are associated with high ripple current either at the input side or the
output side, meaning they have discontinuous current flow. Due to the switching
operation, Boost, buck-boost, flyback and SEPIC converters have high ripple current at
the output side, which may damage or reduce the life-time of the load. Therefore,
capacitors with large capacitance, such as electrolytic capacitors, are usually required to
be inserted at the output side. Table 2 in [16] shows that the electrolytic capacitor has a
relatively high failure rate compared with other converter components. To increase the
mean time between failures (MTBF), a better idea is to replace all the electrolytic
capacitors with film capacitors in a converter circuit. An active filter configuration is
discussed in [17]; the idea is to increase the voltage in the capacitor to reduce
capacitance. Therefore, capacitors with higher life-time and lower capacitance may be
eligible for the application, such as film capacitors. Based on such an idea, a buck-boost
type active filter for the I2ISEPIC is introduced in Figure 12.
Figure 12: An Active Filter for the I2ISEPIC
18
According to the analysis in Chapter 2, D
out
is off when S
2
is on. In Figure 3, i
S
is
zero during this period, and current is drawing from C
out
to supply the output, which is
the root cause of the output ripple current. The active filter switch, S
3
, is controlled by a
complementary signal to q
2
. In other words, when S
2
is on, S
3
is off. And S
4
turns on at
the same time as S
2
. Under this control, the ripple current in C
oL
has been reduced and the
capacitance of C
oH
can be decreased due to higher voltage. However, the active filter
requires an additional source at C
oH
to achieve a zero-ripple current. Therefore, a circuit
similar to Figure 5 in [17] is necessary. The disadvantages of the active filter technique
are as follows:
Component counts greatly increased
Difficult to control
Large size
Additional source required
To achieve the goals of less component counts and easy control, another zero-
ripple technique [18] has been taken into consideration, shown in Figure 13.
Figure 13: A Coupled Filter for the I2ISEPIC
19
The current flows through D
out
, i
s
, can be divided into a DC component and an
AC component (13). The turns ratio of the smoothing transformer is n
c
, where n
c
=
N
AC
: N
DC
. If the transformer is a perfect coupling, then the current flows through winding
N
DC
have an AC current component, n
c
(i
a
). Therefore, the AC current component
relationship can be shown as (14). If n
c
is small enough, i
ac
= i
a
and all the ripple currents
go to the AC port, then zero-ripple current on the output port is achieved.
ac dc s
i i i + = (13)
( )
a c ac
i n i 1 + = (14)
20
Chapter 4: Simulations
4.1 THE I2ISEPIC MODELING
The I2ISEPIC dynamic equations in (4) are applied to Simulink. The block
diagram is shown in Figure 14. The initial central capacitor voltages are set to the
equilibrium point; the initial inductor currents and output voltage are set to zero for the
following simulation. The integrator blocks are set to prevent the current of inductors and
the voltage or capacitors from being less than zero.
Figure 14: The I2ISEPIC Model
21
4.2 THE CURRENT FEED-FORWARD CONTROLLER
The current feed-forward controller block diagram is shown in Figure 15. The
saturation block limits the compensation block output to less than the peak value of the
sawtooth signal in order to avoid the duty cycle becoming equal to one. If I
L1
is less than
the reference voltage, V
ref
, the compensation block output will produce a higher level
signal than before, and a larger duty cycle is generated. Consequently, a higher inductor
current is achieved.
Figure 15: The Current Feed-forward Controller Block Diagram
22
4.3 THE I2ISEPIC WITH CURRENT FEED-FORWARD CONTROL
Overall simulation blocks are shown in Figure 16. The component values in the
experimental circuit are applied to the simulation, where L
m
is the magnetizing
inductance of transformer. The turns ratio of transformer, n1, is set to 0.47. The switching
frequency is set to 80 kHz, and D
2
, the pulse width of q
2
, is fixed at 59%.
Figure 16: Simulation Model of the I2ISEPIC with Current Feed-forward Control
23
Also, the small-signal open-loop gain curve (the compensation block is not
included) of i
L1
/FF is simulated by Simplis and is shown in Figure 17, where FF is the
output signal of the compensation block. The simulation circuit for frequency response is
shown in Figure 18. A 1V AC signal, V
1
, is injected at the output of the compensation. As
we can see, the low frequency gain is very low, which will result in lower regulation
accuracy. And the bandwidth is only around 400Hz, which will result in slow response
[19].
Figure 17: Small Signal Gain of i
L1
/FF
Figure 18: Simplis Simulation Circuit for Frequency Response
24
The small-signal close-loop gain can be derived by dividing the voltage on the
two sides of the AC signal. A simple compensation with a pole at 0 Hz and a zero at 568
Hz is chosen as Figure 15. The simulation result of the close-loop gain is shown in Figure
19. With the compensation, the low frequency gain has been increased above 30dB, and
the bandwidth is extended to 1.12 kHz.
Figure 19: Loop Gain of I2ISEPIC with Current Feed-forward Control
The simulation results of I2ISEPIC with current feed-forward control are shown
in Figures 20, 21, 22, and 23. The inductor current, i
L1
, is eventually regulated to
1.39A
rms
, which is the desired current. Load response and dynamic response also be
examined. In Figure 22, the resistive load is changed from 110 to 110//100at
100mS. As a matter of fact, the control response is very fast. In the load dynamic
situation, load is changed from 110 to 110//100 with a period of 350mS. There is
almost no overshoot during the load changing transient on the inductor current, i
L1
, either
in the load response or in the dynamic response.
25
Figure 20: Startup Transient of I2ISEPIC with Current Feed-forward Control
Figure 21: Steady State of I2ISEPIC with Current Feed-forward Control
Figure 22: Load Response of I2ISEPIC with Current Feed-forward Control
26
Figure 23: Dynamic Response of I2ISEPIC with Current Feed-forward Control
27
4.4 THE VOLTAGE FEEDBACK CONTROLLER
The voltage feedback controller block diagram is shown in Figure 24. Block
Gain2 represents the output voltage divider, which is used to downgrade the voltage
level and compare with 2.5V reference voltage. A different zero and gain is chosen in
compensation. Block Gain1 represents the optocoupler current transfer ratio (CTR) and
the gain caused by optocoupler voltage supply resistors, which will be discussed in
Chapter 5. Since the simulation is conducted with fixed D
2
, V
in1
is greater than V
in2
.
Therefore, the saturation block is set to prevent D
1
from becoming greater than D
2
, which
makes no use of V
in2
.
Figure 24: The Voltage Feedback Controller Block Diagram
28
4.5 THE I2ISEPIC WITH VOLTAGE FEEDBACK CONTROL
The simulation blocks are shown in Figure 25. The switching frequency is set to
80 kHz, and D
2
is fixed at 47%. The simulation results are shown in Figure 26, 27, and
28. The desired output voltage, 34.72V, is achieved after 0.05S. Unlike current feed-
forward control, the load and dynamic response are relatively slow.
Figure 25: Simulation Model of I2ISEPIC with Voltage Feedback Control
29
Figure 26: Startup transient of I2ISEPIC with Voltage Feedback Control
Figure 27: Load Response of I2ISEPIC with Voltage Feedback Control
Figure 28: Dynamic Response of I2ISEPIC with Voltage Feedback Control
30
4.6 THE I2ISEPIC WITH VOLTAGE FEEDBACK AND CURRENT FEED-FORWARD
CONTROL
The I2ISEPIC is joined with a current feed-forward controller and a voltage
feedback controller in Figure 29. The current feed-forward controller is the same as the
one applied in Figure 16, and the voltage feedback controller is the same as the one
applied in Figure 25. The inductor current, i
L1
, and the output voltage are both well
regulated. The simulation results are shown in Figure 30, 31, 32. Compared to the result
of the IMISEPIC with only current feed-forward control, the result in Figure 32 shows
that with both current feedforward control and voltage feedback control, the inductor
current has been injected with more noise.
Figure 29: Simulation Model of I2ISEPIC with Voltage Feedback Control and Current
Feed-forward Control
31
Figure 30: Startup Transient of I2ISEPIC with Voltage Feedback Control and Current
Feed-forward Control
Figure 31: Steady State of I2ISEPIC with Voltage Feedback Control and Current Feed-
forward Control
Figure 32: Load Response of I2ISEPIC with Voltage Feedback Control and Current
Feed-forward Control
32
4.7 RIPPLE CURRENT CORRELATION (RCC) CONTROLLER
The RCC controller simulation block diagram is shown in Figure 33, which is
based on real components in the circuit experiment. Multipliers are divided by 10 because
the real multiplier, AD633 [20], applied in the experiment divides the product of two
inputs by 10. Also, the choice of k
v
and k
i
is made in order to prevent components
saturation. The values of differentiator 1 and differentiator 2 are set to be the same to
avoid phase shift between P and V [13].
Figure 33: Simulation Block Diagram of Ripple Current Correlation Controller
33
4.8 THE I2ISEPIC WITH RIPPLE CURRENT CORRELATION AND VOLTAGE
FEEDBACK CONTROL
The PVs characteristic can be modeled based on (9). In the simulation, I
sc
equals
4.30524, A equals 0.00524 and B equals 0.1777. The I-V and P-V simulation curves are
shown in Figure 34. The maximum power point (MPP) is at 27.72V, and the MPP
current is 3.58A. The voltage feedback controller, which is used before, has been
slightly modified and is shown in Figure 35. Gain 2 is smaller than it is in Figure 24
because the output voltage here is higher than in the simulation of I2ISEPIC with
voltage feedback control. The compensation is also slightly adjusted.
Figure 34: I-V and P-V Curves of the Photovoltaic Simulation Model
34
Figure 35: Voltage Feedback Controller Block
35
The overall simulation block diagram is shown in Figure 36. An input capacitor,
C
in
, is placed at V
in2
, which is the output of the PV, in order to give the initial condition of
v
pv
. The voltage feedback controller is used to control q
1
, where the desired output
voltage is set to 100V. The simulation results are shown in Figures 37 and 38. After 0.2S,
the MPP is achieved and the output voltage is regulated to 100V.
Figure 36: Simulation Model of I2ISEPIC with Voltage Feedback Control and RCC
Control
36
Figure 37: Startup Transient of I2ISEPIC with Voltage Feedback Control and RCC
Control
Figure 38: Steady State of I2ISEPIC with Voltage Feedback Control and RCC Control
37
4.9 THE I2ISEPIC WITH ZERO-RIPPLE TECHNIQUE
The simulation is conducted both with and without a coupled filter in Simplis.
The circuit diagrams are shown in Figures 39 and 40. The inductor L
2
represents the
magnetizing inductance of the transformer, TX
1
. The turns ratio of TX
1
is N
P1
: N
S1
= 0.5,
and the turns ratio of the transformer TX
2
is N
P1
: N
S1
= 42. R
2
is inserted to accelerate the
simulation speed, and R
3
is used to simulate the DC resistance (DCR) of TX
2
. The
simulation results are shown in Figures 41 and 42. The output ripple voltage of the
original I2ISEPIC is about 0.1V
pp
, and the output ripple voltage of the I2ISEPIC with the
zero-ripple technique is about 0.01V
pp
, which means that most of the ripple current stays
in C
out1
. The results show that with the zero-ripple technique, smaller capacitors can be
applied to the I2ISEPIC and the output ripple can still be maintained within a reasonable
range.
Figure 39: The I2ISEPIC without Zero-Ripple Technique
38
Figure 40: The I2ISEPIC with Zero-Ripple Technique
Figure 41: Simulation Result of I2ISEPIC without Zero-Ripple Technique
Figure 42: Simulation Result of I2ISEPIC with Zero-Ripple Technique
39
Chapter 5: Circuit Design and Experiments
5.1 THE IMISEPIC CIRCUIT DESIGN
Good instruction for designing a SEPIC converter is given in [22]. However, the
leakage inductance of the transformer must be taken into consideration in the real
IMISEPIC circuit. Figure 43 is the simulation result of considering the transformer
leakage inductance; the simulation circuit is shown in Figure 44. L
4
represents the
leakage inductance of the transformer TX
1
, C
1
and C
2
are the drain-to-source
capacitances, C
ds
, of the MOSFETs, and the parallel resistor R
2
is used to increase the
simulation speed. If the capacitances of C
s
and C
s1
are very large, the theoretical drain-to-
source voltage of Q
2
during Q
2
is turned off should be ( )
out in
v n V +
2
. However, with the
transformer leakage inductance, the drain-to-source voltage of Q
2
is much higher than the
theoretical value, ( ) V v n V
out in
120
2
~ + , as shown in Figure 43. The energy stored in L
4
cant be transferred to the output because it will cause an inductance-capacitance (LC)
resonant with the MOSFET C
ds
, and the energy will dissipate on MOSFET while
MOSFET is turned on. This operation causes an additional power loss and decreases the
converters efficiency. Thus, the idea is to reduce the transformer leakage inductance
that is, to have better coupling. Therefore, the sandwiched or interleaved winding method
should be applied to the IMISEPIC transformer. The winding structure and flux intensity
relationship are shown in Figure 45 [21], which shows that a transformer with interleaved
winding has a smaller peak flux intensity than with stacked or sandwiched winding. With
interleaved winding, the transformer leakage inductance can be minimized.
40
Figure 43: Simulation Result of I2ISEPIC with Real Transformer Model
Figure 44: Simulation Circuit of I2ISEPIC with Real Transformer Model
Figure 45: Transformer Winding and Flux Intensity Relationship
41
5.2 THE EFFICIENCY OF IMISEPIC
Since the IMISEPIC has the leakage inductance problem as discussed above, the
efficiency of IMISEPIC is usually worse than that of non-isolated converters and some
resonant converters [23]-[24]. The efficiency of I2ISEPIC has been examined with the
circuit in Figure 46. The input inductors, L
1
and L
2
, are PFCV-HP7354 with
300H@100kHz which is made by Delta Electronics, Inc. Ferrite core PQ3220 [25] with
interleaved winding is applied to the transformer, T
1
. The transformer turns ratio is N
p
:N
s
= 6T
s
:12T
s
, the primary inductance is 11.8H, and the leakage inductance at the primary
side is 364nH. Fairchild hyperfast diode RHRP1560 [26] is applied as the output diode,
which has V
f
= 1.7V @ I
f
= 15A, and 600V
R
. Shindengen S60SC6MT [27] is applied as
the diodes in series with the MOSFETs to form the FCBB switches, which have typical
V
f
= 0.6V @ I
f
= 30A, and V
R
= 60V. C
s_1
through C
s_8
and C
s1_1
thru C
s1_8
are 2.2F
Rubycon MPB series film capacitors [28]. Q
1
and Q
2
are Infineon semiconductor
SPW47N60C3 [29], which has nominal R
ds(on)
= 0.06 and 650V voltage rating. A
pulse width modulation (PWM) IC MC34060 [30] manufactured by On semiconductor is
applied here for generating sawtooth waveform and PWM signal. A dual inverting
MOSFET driver IC, UCC27323 [31], is applied here to increase the driving capability.
The capacitors C
DS1
and C
DS2
are used to avoid the LC resonant voltage, caused by the
transformer leakage inductance, exceeding the MOSFET voltage rating. And the driving
signals are generated as shown in Figure 4; the driving signal waveform is shown in
Figure 47. The efficiency test is conducted with D
1
fixed at 37.5%, D
2
fixed at 56.5%,
and 70 kHz set as the switching frequency. The measurement results are shown in Table
1; the converter efficiency is about 86%. In an effort to reduce components, the FCBB
combinations have been replaced with an insulated-gate bipolar transistor (IGBT) [32],
and C
DS1
and C
DS2
are removed. The results are shown in Table 2. However, both results
42
show that the efficiencies are not good enough in comparison with other converters, for
example, converters in [23] and [24].
C
I N
2
1
0
u
F
5
0
V
RGS1
20k
Q
2
S
P
W
4
7
N
6
0
C
3
S60SC6M
D2
RG1
12.1
DG2
1N4148
0
. 0
1
u
/
1
k
V
C
D
S
2
L1
PFCV-HP7354
S60SC6M
D1
2
. 2
u
/
4
5
0
V
C
S
_
2
2
. 2
u
/
4
5
0
V
C
S
_
1
RGS
20k
Q
1
S
P
W
4
7
N
6
0
C
3
2
. 2
u
/
4
5
0
V
C
S
1
_
2
2
. 2
u
/
4
5
0
V
C
S
1
_
1
C
I N
1
_
2
4
7
0
u
F
1
6
0
V
C
I N
1
_
1
4
7
0
u
F
1
6
0
V
RG2
12.1
DG1
1N4148
L2
PFCV-HP7354
0
. 0
1
u
/
1
k
V
C
D
S
1
2
. 2
u
/
4
5
0
V
C
S
_
6
2
. 2
u
/
4
5
0
V
C
S
_
4
2
. 2
u
/
4
5
0
V
C
S
_
5
2
. 2
u
/
4
5
0
V
C
S
_
3
2
. 2
u
/
4
5
0
V
C
S
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
6
2
. 2
u
/
4
5
0
V
C
S
1
_
5
2
. 2
u
/
4
5
0
V
C
S
1
_
4
2
. 2
u
/
4
5
0
V
C
S
1
_
3
T1:2
DOUT
RHRP1560
2
. 2
u
/
4
5
0
V
C
S
1
_
8
2
. 2
u
/
4
5
0
V
C
S
_
8
C
O
U
T
5
6
0
u
F
2
5
0
V
RLOAD1
1
R
L
O
A
D
2
2
2
0
R
L
O
A
D
3
2
2
0
R
L
O
A
D
4
1
0
0
C12
1u
RDUTY_1
1.2k
IC2
MC34060A
RT1
1.2k
VR_FREQ
5k
VR_DUTY1
5k
6.8n
CT
CFB
0.01u
CFILTER
0.1u
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
5
OUT_B
7
OUT_A
IC1
UCC27323
R
E
M
I T
T
E
R
1
. 2
k
R1G
3.3k
IC5:1
LM293N
10k
R2
VR_DUTY2
5k
R2G
3.3k
1.2k
R1
R
D
U
T
Y
_
2
1
. 2
k
IC5:2
LM293N
Figure 46: The I2ISEPIC Efficiency Test Circuit
Figure 47: Driving Signal Waveform of I2ISEPIC
43
Table 1: The I2ISEPIC Efficiency Measurement
Table 2: The I2ISEPIC Efficiency Measurement with IGBTs
44
The FCBB combination (diode in series with MOSFET) has first been taken into
consideration for replacement in order to improve the I2ISEPIC efficiency, as shown in
Figure 48. D
1
and D
2
in Figure 46 have been replaced by MOSFETs Q
1_1
and Q
2_1
[33],
which have very low on-state resistance. Also, the source pins of MOSFETs on each leg
are connected for easier control setup. This placement is different from the FCBB
combination placement in Figure 46. However, the source pins of Q
1_1
and Q
2_1
still have
different groundings. Therefore, an isolated driving technique has to be applied here. The
driving transformer T
9
is applied here for isolation; the turns ratio is N
7-9
:N
1-2
= 15:40.
The inductance of L
1
, L
2
and T
1
determine the magnitude of the inductor current ripple,
and high ripple current results in high switching losses. For this reason, a larger core
(PQ3230) [25] is used for T
1
and the turns ratio is increased to N
p
:N
s
= 8T
s
: 17T
s
with
24.42H as primary inductance. The control strategy in Figure 5 is applied here; the
circuit waveforms are shown in Figure 49 and Figure 50. The test condition is V
in1
=
55.5V, V
in2
= 25V, D
1
= 31.1%, D
2
= 32.4%, and the switching frequency is 80 kHz.
With 216.87W output power, the efficiency is calculated as 92.5%. This circuit setting
makes significant improvements to the I2ISEPIC efficiency.
45
CFILTER1
1800u/25V
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
5
OUT_B
7
OUT_A
IC3
UCC27323
0
. 0
1
u
/
1
k
V
C
D
S
2
S
P
W
4
7
N
6
0
C
3
Q
2
_
3
L2
PFCV-HP7354
2
. 2
u
/
4
5
0
V
C
S
1
_
3
2
. 2
u
/
4
5
0
V
C
S
1
_
2
2
. 2
u
/
4
5
0
V
C
S
1
_
4
2
. 2
u
/
4
5
0
V
C
S
1
_
1
RG2
5.6
DG2
D1N4148
RGS3
20k
RGS1
34k
I P
P
0
7
5
N
1
5
N
3
Q
2
_
1
S
P
W
4
7
N
6
0
C
3
Q
2
_
2
2
. 2
u
/
4
5
0
V
C
S
1
_
6
2
. 2
u
/
4
5
0
V
C
S
1
_
5
5.36k
R7
5.36k
R6
357
R10
3.16k
R9
D1N4148
D1
8.66k
R8
IC6:2
LM293N
T9:1
S
P
W
4
7
N
6
0
C
3
Q
1
_
3
0
. 0
1
u
/
1
k
V
C
D
S
1
L1
PFCV-HP7354
I P
P
0
7
5
N
1
5
N
3
Q
1
_
1
RGS
34k
RGS2
20k
S
P
W
4
7
N
6
0
C
3
Q
1
_
2
RG1
5.6
2
. 2
u
/
4
5
0
V
C
S
_
1
2
. 2
u
/
4
5
0
V
C
S
_
5
2
. 2
u
/
4
5
0
V
C
S
_
6
2
. 2
u
/
4
5
0
V
C
S
_
3
2
. 2
u
/
4
5
0
V
C
S
_
4
2
. 2
u
/
4
5
0
V
C
S
_
2
DG1
D1N4148
R
L
O
A
D
_
1
1
o
h
m
/
4
0
W
2
. 2
u
/
4
5
0
V
C
S
_
8
DOUT
RHRP1560
T1:2
2
. 2
u
/
4
5
0
V
C
S
_
7
IC5:1
LM293N
IC5:2
LM293N
R
D
U
T
Y
_
2
1
. 2
k
R2G
3.3k
VR_DUTY2
5k
R1G
3.3k
10k
R2
R
E
M
I T
T
E
R
1
. 2
k
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
5
OUT_B
7
OUT_A
IC1
UCC27323
CFILTER
0.1u
R_DRV2
340
R_DRV1
340
R_DRV3
340
R
L
O
A
D
_
3
5
0
o
h
m
/
1
K
W 2
. 2
u
/
4
5
0
V
C
S
1
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
8 R
L
O
A
D
_
2
5
0
o
h
m
/
1
K
W
C
O
U
T
5
6
0
u
F
2
5
0
V
RT1
1.2k
C12
1u
RDUTY_1
1.2k
CFB
0.01u
6.8n
CT
IC2
MC34060A
VR_FREQ
5k
VR_DUTY1
5k
1.2k
R1
Figure 48: The I2ISEPIC Circuit with MOSFET in Series
Figure 49: Current and Driving Waveforms of Improved I2ISEPIC Circuit
Figure 50: Waveforms of Improved I2ISEPIC Circuit
46
5.3 THE I2ISEPIC WITH CURRENT FEED-FORWARD CONTROL
The I2ISEPIC circuit with current feed-forward control based on the simulation
conditions is built as shown in Figure 51. A sensing resistor is placed in series with L
1
.
With the differential amplifier setting of IC4:2, the voltage drop in R
sense
has been
transfer to the current gain of I
L1
, and compared with an adjustable voltage in pin3 of
IC4:1. The surrounding circuit with IC4:1 is equivalent to the compensation block in
Figure 15. A hysteresis comparator circuit is formed by R
16
, R
17
and IC7:1 to prevent
undesired switching. The test is conducted with V
in1
= 14.8V, V
in2
= 10.1V, D
2
fixed at
59%, and 80kHz switching frequency. In steady state, V
out
= 49.32V, I
in1
= 1.32A and I
in2
= 0.5A; the waveform is shown in Figure 52. The input current of V
in
has been regulated
to the desired current. The load and dynamic response have also been tested as shown in
Figures 53 and 54. The load resistance is changing from 110//100 to 110 for the
load response test. For the dynamic response test, the load resistance is changing from
110 to 110//100 periodically. The rms value of the inductor current, i
L1
, is well
regulated and responded very fast. There is almost no undershoot or overshoot during the
transient.
C
I N
2
1
0
u
F
5
0
V
Q
4
S
P
W
4
7
N
6
0
C
3
0
. 0
1
u
/
1
k
V
C
D
S
2
S60SC6M
D2
Q
2
S
P
W
4
7
N
6
0
C
3
RGS1
20k
RG1
11
C
I N
1
_
1
4
7
0
u
F
1
6
0
V
C
I N
1
_
2
4
7
0
u
F
1
6
0
V
L2
PFCV-HP7354
RSENSE
24m L1
PFCV-HP7354
S60SC6M
D1
2
. 2
u
/
4
5
0
V
C
S
_
2
2
. 2
u
/
4
5
0
V
C
S
_
1
RGS
20k
Q
1
S
P
W
4
7
N
6
0
C
3
2
. 2
u
/
4
5
0
V
C
S
1
_
2
2
. 2
u
/
4
5
0
V
C
S
1
_
1
RG2
11
0
. 0
1
u
/
1
k
V
C
D
S
1
Q
3
S
P
W
4
7
N
6
0
C
3
2
. 2
u
/
4
5
0
V
C
S
_
6
2
. 2
u
/
4
5
0
V
C
S
_
4
2
. 2
u
/
4
5
0
V
C
S
_
5
2
. 2
u
/
4
5
0
V
C
S
_
3
2
. 2
u
/
4
5
0
V
C
S
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
6
2
. 2
u
/
4
5
0
V
C
S
1
_
5
2
. 2
u
/
4
5
0
V
C
S
1
_
4
2
. 2
u
/
4
5
0
V
C
S
1
_
3
T1:2
DOUT
RHRP1560
2
. 2
u
/
4
5
0
V
C
S
1
_
8
2
. 2
u
/
4
5
0
V
C
S
_
8
C
O
U
T
5
6
0
u
F
2
5
0
V
R
L
O
A
D
1
1
0
R17
1.13M
C13
0.1u
R14
2.8k
R7
750k
R13
9.53k
R11
18k
R10
18k
R15
5.36k
R6
5.36k
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
7
OUT_A
5
OUT_B
IC6
UCC27424
0.22u
C14
C1
1000uF 35V
R9
2k
IC4:2
LM258N
R12
1.1k
R20
750k
R8
2k
VR_REF
10k
IC4:1
LM258N
IC7:2
LM293
IC7:1
LM293
ZD1
1N5221B
R16
1.1k
6.8kp
C15
Figure 51: Circuit Diagram of I2ISEPIC with Current Feed-forward Control
47
Figure 52: Steady State Waveform of I2ISEPIC with Current Feed-forward Control
Figure 53: Load Response Waveform of I2ISEPIC with Current Feed-forward Control
Figure 54: Dynamic Response Waveform of I2ISEPIC with Current Feed-forward
Control
48
5.4 THE I2ISEPIC WITH VOLTAGE FEEDBACK CONTROL
The circuit diagram of I2ISEPIC with voltage feedback control is shown in Figure
55. The voltage dividerR
1
, R
2
, R
21
, and VR
1
downgrades the sensed output voltage to
compare with the inner reference voltage of IC
2
[34]. The cathode pin of TL431 is
connected to the optocoupler, OPTO
1
[35], in order to control the optocoupler current
flow. Two IC supply voltages with different grounding, +12V and +12V_1, have to be
applied here for isolation. The use of a 2.4V
z
zener diode, ZD
2
[36], is to prevent the
feedback voltage from becoming higher than the maximum value of the sawtooth
waveform. The circuit is tested with V
in1
= 15V, V
in2
= 10V, and D
2
fixed at 47%. The
circuit waveforms are shown in Figures 56, 57, and 58. After an overshoot, the output
voltage is regulated to 35V in the startup transient. Both input currents are 0.5A in steady
state. The load and dynamic response conditions are the same as those in the test done in
the I2ISEPIC circuit with current feed-forward control. During the load and dynamic
transient, the overshoot/undershoot is within 3V and comes back to the desired voltage
very quickly.
Q
4
S
P
W
4
7
N
6
0
C
3
0
. 0
1
u
/
1
k
V
C
D
S
2
S60SC6M
D2
Q
2
S
P
W
4
7
N
6
0
C
3
RGS1
20k
RG1
11
C
I N
2
1
0
u
F
5
0
V
L2
PFCV-HP7354
C
I N
1
_
2
4
7
0
u
F
1
6
0
V
C
I N
1
_
1
4
7
0
u
F
1
6
0
V
L1
PFCV-HP7354
RSENSE
24m
S60SC6M
D1
2
. 2
u
/
4
5
0
V
C
S
_
2
2
. 2
u
/
4
5
0
V
C
S
_
1
RGS
20k
Q
1
S
P
W
4
7
N
6
0
C
3
2
. 2
u
/
4
5
0
V
C
S
1
_
2
2
. 2
u
/
4
5
0
V
C
S
1
_
1
RG2
11
0
. 0
1
u
/
1
k
V
C
D
S
1
Q
3
S
P
W
4
7
N
6
0
C
3
2
. 2
u
/
4
5
0
V
C
S
_
6
2
. 2
u
/
4
5
0
V
C
S
_
4
2
. 2
u
/
4
5
0
V
C
S
_
5
2
. 2
u
/
4
5
0
V
C
S
_
3
2
. 2
u
/
4
5
0
V
C
S
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
7
2
. 2
u
/
4
5
0
V
C
S
1
_
6
2
. 2
u
/
4
5
0
V
C
S
1
_
5
2
. 2
u
/
4
5
0
V
C
S
1
_
4
2
. 2
u
/
4
5
0
V
C
S
1
_
3
T1:2
DOUT
RHRP1560
2
. 2
u
/
4
5
0
V
C
S
1
_
8
2
. 2
u
/
4
5
0
V
C
S
_
8
C
O
U
T
5
6
0
u
F
2
5
0
V
R
L
O
A
D
1
1
0
R6
5.36k
R23
11k
R20
10.5k
R18
5.36k
R19
10.5k
1u
C14
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
7
OUT_A
5
OUT_B
IC6
UCC27424
R22
1.47k
R15
5.36k
IC7:2
LM293
IC7:1
LM293
R2
845
IC2
TL431
OPTO1
PC123
R1
51.1k
5k
VR1
C2
1u
R3
845
R4
6.49k
R21
5.36k
ZD2
1N5221B
Figure 55: Circuit Diagram of I2ISEPIC with Voltage Feedback Control
49
Figure 56: Startup Waveform of I2ISEPIC with Voltage Feedback Control
Figure 57: Load Response Waveform of I2ISEPIC with Voltage Feedback Control
Figure 58: Dynamic Response Waveform of I2ISEPIC with Voltage Feedback Control
50
5.5 THE I2ISEPIC WITH CURRENT FEED-FORWARD AND VOLTAGE FEEDBACK
CONTROL
With the same current feed-forward and voltage feedback control circuit, the
I2ISEPIC has also been tested. The steady state, load, and dynamic response waveforms
are shown in Figures 59, 60, and 61. The inductor current, i
L1
, is regulated to 0.52A and
V
out
is regulated to 33.82V in steady state. During load and dynamic transients, the
switching signals S
1
and S
2
are modulated together.
Figure 59: Steady State Waveform of I2ISEPIC with Current Feed-forward and Voltage
Feedback Control
Figure 60: Load Response Waveform of I2ISEPIC with Current Feed-forward and
Voltage Feedback Control
51
Figure 61: Dynamic Response Waveform of I2ISEPIC with Current Feed-forward and
Voltage Feedback Control
52
5.6 THE I2ISEPIC WITH RIPPLE CURRENT CORRELATION AND VOLTAGE
FEEDBACK CONTROL
The experiment was conducted at The University of Texas at Austin Lab ENS212
on January 12, 2010; the circuit diagram and the experimental result are shown in Figures
62 and 63. Input inductors L
1
and L
2
are 100H with Ferrite core PJ4026. The parameters
of the transformer, T
1
, are the same as those of the transformer in the I2ISEPIC efficiency
test circuit. The surrounding circuit of IC
4
gives the PVs voltage gain and current gain,
which are the same as K
i
and K
v
in Figure 35. An optocoupler is applied to the
experimental circuit as an isolated buffer to isolate the feedback signal and the control
signal. A 24m resistor is used for current sensing. Two 47pF capacitors, C
14
and C
15
,
are applied to the differential amplifiers to filter high-frequency noises due to the
differential operation. R
17
helps the RCC controller start with a smaller duty cycle. A
dual-inverting driving IC, MIC4426 [37], is used as the driver of the RCC controller. The
PV open circuit voltage is 40V, and the PV short circuit current is 4A. V
in1
is applied by
DC power supply with input voltage 36.7V. The total power generated from the PV is
27.3V x 3.79A = 103.47W. The output voltage is regulated to 103V, and I
in2
is 0.595A.
The efficiency can be calculated as 84.7%.
53
R20
750k
R9
2k
R8
2k
IC4:2
LM258N
R11
18.2k
R10
18.2k
8
+Vs
7
W
6
Z
5
-Vs
4
Y2
3
Y1
2
X2
1
X1
AD633
IC3
9.09k
R6
1.02k
R5
1.02k
R4
R3
1.02k
IC4:1
LM258N
R7
750k
C13
6.8n
IC7:2
LM258N
R13
7.5k
C14
47p
R12
100
C15
47p
R14
7.5k
8
+Vs
7
W
6
Z
5
-Vs
4
Y2
3
Y1
2
X2
1
X1
AD633
IC9
C16
6.8n
R15
100
IC7:1
LM258N
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
5
OUT_B
7
OUT_A
IC1
MIC4426
R22
5.36k
1/2
R21
5.36k
R23
10.2k
IC5
TL431
ZD1
HZ2V7
OPTO1
PC123
R1
51.1k
R24
21.5k
C1
1u
R25
845
R26
6.49k
IC301:1
LM293
1
NC
2
IN_A
3
GND
4
IN_B
6
VDD
8
NC
7
OUT_A
5
OUT_B
IC6
UCC27424
C2
0.1u
RSENSE
24m
L1
PJ4026
C
I
N
2
4
7
0
u
F
2
5
0
V
S60SC6M
D2
Q
2
S
P
W
4
7
N
6
0
C
3
RGS1
20k
0
.
0
1
u
/
1
k
V
C
D
S
2
0
.
0
1
u
/
1
k
V
C
D
S
1
Q
1
S
P
W
4
7
N
6
0
C
3
RGS
20k
S60SC6M
D1
L2
PJ4026
2
.
2
u
/
4
5
0
V
C
S
1
_
1
2
.
2
u
/
4
5
0
V
C
S
1
_
2
2
.
2
u
/
4
5
0
V
C
S
1
_
3
2
.
2
u
/
4
5
0
V
C
S
1
_
4
2
.
2
u
/
4
5
0
V
C
S
1
_
5
2
.
2
u
/
4
5
0
V
C
S
_
1
2
.
2
u
/
4
5
0
V
C
S
_
2
2
.
2
u
/
4
5
0
V
C
S
_
4
2
.
2
u
/
4
5
0
V
C
S
_
5
2
.
2
u
/
4
5
0
V
C
S
_
3
2
.
2
u
/
4
5
0
V
C
S
_
8
2
.
2
u
/
4
5
0
V
C
S
_
6
2
.
2
u
/
4
5
0
V
C
S
_
7
T1:2
2
.
2
u
/
4
5
0
V
C
S
1
_
7
2
.
2
u
/
4
5
0
V
C
S
1
_
6
2
.
2
u
/
4
5
0
V
C
S
1
_
8
DOUT
RHRP1560
C
O
U
T
5
6
0
u
F
2
5
0
V
R
L
O
A
D
1
0
0
R2
845
5k
VR1
IC2
MC34060A
5k
VR
RT1
1.18k
C12
1u
R
E
M
I
T
T
E
R 1
.
1
8
k
C17
1u
R17
1.08Meg
IC8:2
LM258N
R16
500
R19
200k
IC11:1
LM258N
R18
200k
6.8n
CT
Figure 62: Circuit Diagram of I2ISEPIC with RCC and Voltage Feedback Control
54
Figure 63: Steady State Waveform of I2ISEPIC with RCC and Voltage Feedback Control
55
Chapter 6: Conclusions
As a good current-fed converter, SEPIC has been extended to the IMISEPIC in
this thesis. Two different topologies, the IMISEPIC and the coupled-input inductors
IMISEPIC, are analyzed. The IMISEPIC with coupled-input inductors was shown to
reduce the component counts. Different control strategies were discussed. Clearly
separating the driving signals of S
1
and S
2
gives the input sources more freedom. Current
feed-forward, voltage feedback, and RCC controls were discussed, simulated, and
implemented into real circuits. Each input inductor current and output voltage was related
to all the driving signals, which means that even though the current feed-forward
controller is placed for controlling i
L1
, the variation of D
2
still affects i
L1
. This
phenomenon limits the control operation range. The equilibrium point of input inductors
shows that the inductor currents are related with switching frequency and inductances.
This characteristic sets up another limitation on the control operation range. This
limitation can be ignored if high switching frequency or high inductances are applied to
the circuit. However, the inductances are limited by the magnetizing inductance of the
transformer, L
m
. Since the magnetizing and leakage inductance are approximately
proportional to square turns,
2
p
N , with the same air gap on the core. If L
m
is increased to
widen the limitation, the leakage inductance will also be increased, which will result in
higher losses and higher voltage stresses. The transformer stores energy when the switch
is turned on. For this reason, an air gap is always required for a transformer in this
application with Ferrite core. Therefore, a smaller air gap may not be a good solution for
increasing L
m
to widen the limitation. In other words, the use of a transformer limits the
IMISEPIC applications. Because of the limited inductance and narrow controllable range,
it is very difficult to apply the IMISEPIC to multiple current feed-forward control or
56
multiple RCC control. A trade-off has to be made for circuit optimization. The efficiency
tables in Chapter 5 show that IGBT is not a good choice in the IMISEPIC. Also, the
IMISEPIC can only reach about 500W output power in the experiment. Thus, research on
the lossless snubbers role in increasing the power level of the IMISEPIC is necessary.
In conclusion, the IMISEPIC is best suited for low-power applications. Using
MOSFETs in series to form a FCBB switch is the better choice in efficiency
improvement. The IMISEPIC is also a good converter for applications that require a
small control range.
57
Appendix
A better approach to find the equilibrium point of i
L1
and i
L2
is to consider the
voltage-second balance of the inductor and the ampere-second balance of the capacitor.
Under the law of voltage-second balance, total variation of the inductor current, i
L
,
should be zero. Similarly, under the law of ampere-second balance, total variation of
capacitor voltage, v
C
, should be zero. Using such a concept, (4) can be written in an
integration form as in (a1).
( )
( )
( ) ( )( ) | |
( )
( )
( ) ( )( ) | |
( )
( )
( ) | |
( ) ( ) | |
( )
( )
( )
( )
( ) ( ) | |
( )
( )
( ) ( ) | |
=
(
+ + =
= + =
= + + =
= + =
= + =
= + =
} }
} }
} }
} }
} }
} }
0 1
1
0 1
1
0 1
1
0 1
1
0 1
1
0 1
1
2 1 2
0 0
1 2 2 2
0
2
0
2
0 0
1 1 2 1
1
1
0
2 2 2 1 1
0
0
2 2 1 2 1 2
2
0
0
1 2 2 1 2 1
1
0
2
2
1
1
2
2
2
1
1
1
dt
R
v
i i i n q
C
dv
dt i i q i q
C
dv
dt i q i i q
C
dv
dt nv q v q v q
L
di
dt nv v q v v q V
L
di
dt nv v q v v q V
L
di
out
Lm L L
T
out
T v
v
out
Lm L eff L eff
T
s
T v
v
Cs
T v
v
T
L Lm L
s
Cs
T
out Cs eff Cs
m
T i
i
L
T
out Cs Cs Cs in
T i
i
L
T
out Cs Cs Cs eff in
T i
i
L
out
out
Cs
Cs
Cs
Cs
m
L
m
L
m
L
L
L
L
(a1)
Assuming the voltage variation of capacitors in each sectionD
1
T, D
2eff
T, and (1-
D
2
)Thas a constant slope rate, then based on the waveform in Figure a1, the functions
of v
Cs1
, v
Cs2
, and v
out
can be defined as (a2) thru (a4). Moreover, (a1) can be written as
(a5) based on the definition of q
1
, q
2
, and q
eff
in Figure 3. By combining the first three
equations in (a5) with (a2) (a4), the average voltage of v
Cs1
, v
Cs2
, and v
out
can be derived
as shown in (a6). The result gives the same conclusion as (6).
58
Figure a1: State Variable Waveforms
59
( )
( )
( )
T t T D
T D t
T D t V
t V
t v
s
L
s
s
m
L L
s
C
i
C
C
i i
C
Cs
< <
< <
+
+
=
1
1
1
0
,
1
1
min , 1
1
2
min , 1
1
(a2)
( )
( ) ( )
( ) ( )
( )
T t T D
T D t T D
T D t
T D t V
V
T D t V
t v
s
L
s
s
m
L L
s
s
L
s
C
i
C
C
i i T D t
C
C
i
C
Cs
< <
< <
< <
+
+
+ +
=
2
2 1
1
2
2 0
,
1
2
2
min , 2
2
1
2
min , 2
2
2
min , 2
2
(a3)
( )
( ) | |
( ) | |
( )
T t T D
T D t
T D t V
V
t v
out
R
out
v
m
L L L
out
R
out
v
C
i i i n
out
C
T D t
out
out
< <
< <
+
+
=
+ +
2
2
2 min ,
min ,
0
,
2 1
2
(a4)
( ) | |
( ) ( ) | |
| |
( ) | |
| |
| | ( ) | |
+ +
}
+
}
=
}
+
}
}
=
}
+
}
+
}
=
}
}
+
}
=
+
}
+
}
=
}
+
}
+
}
=
dt i i i dt
dt i dt i dt i dt i
dt i dt i dt i
dt nv dt v dt v
dt nv v dt v v V
dt nv dt v dt v V
m
out
m
m
L L L
T
T D nR
v T
T
L
T
T D L
T D
T D L
T D
T D L
T D
T
L
T
T D L
T D
L
T D
T
out
T
T D Cs
T D
T D Cs
T D
T
out Cs
T
T D Cs Cs
T D
T in
out
T
T D Cs
T D
T D Cs
T
T D T in
2 1 2
2 2
2
1 1
2
1 2
1
1 1
1
2
1
2
2
1
1
2
1
2
2
2
1 1
0
1
0
1
0 0
1
2 1 0
1
2 1 2 0
1
2 1
1
1
0
0
0
0
(a5)
( )
( )
(
(
(
=
(
(
(
+
2
2 1 2 1 1
1
2
1
,
, 2
, 1
D n
V D D V D
in
in
avg out
avg Cs
avg Cs
in in
V
V
v
v
v
(a6)
Again, the functions of i
L1
, i
L2
, and i
Lm
can be defined as (a7) thru (a9) based on
the waveforms in Figure a1. To simplify the calculation, the function v
Cs1
is assumed to
be V
in1
, v
Cs2
to be V
in2
, and v
out
to be
( )
( )
2
2 1 2 1 1
1 D n
V D D V D
in in
+
. Then the system equations,
including the last three equations in (a5) and (a7) (a9), are solved by MathCAD
software as shown in Figure a2.
60
( ) ( )
| |
T t T D
T D t T D
T D t
I
T D t I
t I
t i
L
T t nv v V
L
L
V V V
L
V T D
L
L
V
L
L
out Cs in
s
C
s
C in
in
in
< <
< <
< <
+
+ +
+
=
+
2
2 1
1
) (
1
) (
0
,
1
1
1
min , 1
1
2 1
1
1
1 1
min , 1
1
1
min , 1
1
(a7)
( ) ( )
( )| |
T t T D
T D t T D
T D t
I
T D t I
t I
t i
L
T t nv v V
L
L
V
L
v v V T D
L
L
v v V
L
L
out Cs in
in s
C
s
C in
s
C
s
C in
< <
< <
< <
+
+ +
+
=
+
+
2
2 1
1
1
) (
) (
0
,
2
2
2
min , 2
2
2
2
1 2
2 1
min , 2
2
1 2
2
min , 2
2
(a8)
( ) ( )
( )| |
T t T D
T D t T D
T D t
I
T D t I
t I
t i
m
out Cs in
m
m
in
m
Cs
m
m
Cs
m
m
L
T t nv v V
L
L
V
L
v T D
L
L
v
L
L
< <
< <
< <
+
+ +
+
=
2
2 1
1
1
0
,
2
2
min ,
2 1 1
min ,
1
min ,
(a9)
Figure a2: Mathcad Symbolic Solving Function for Solving I
L1,min
, I
L2,min
and I
Lm,min
However, the result in Figure a2 is very long and complex. The result can be
simplified with both a software simplify function and by hand. With (a7) (a9), the
average value is calculated as (a10).
( )
( )
( )
( )
(
(
(
(
(
(
(
(
+ +
+
+ +
=
(
(
(
nR
v
L L L
L L L L L L T V D D
R D n
v D
L L L
L L L L L L T V D D
R D n
v D
i
i
i
out
m
m m in eff out eff
m
m m in eff
out
avg L
avg L
avg L
m
2 1
1 2 2 1 1 2 1
2
2
2 1
1 2 2 1 2 2 1
2
1
,
,
,
2 1
2 1
2
1
(a10)
61
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65
Vita
Sheng-Yang Yu was born in Taipei, Taiwan. In June 2003, he received a Bachelor
of Science in Industrial Engineering and a Bachelor of Science in Electrical Engineering
(double major) from National Tsing Hua University in Hsinchu, Taiwan. After two years
of military service, he joined the Display Power Business Unit of Delta Electronics as an
electronics engineer in March 2005. He received a Design Award from Delta Electronics
in both 2006 and 2007. In August 2008, he entered the Cockrell school of engineering at
the University of Texas at Austin. He is with the Power Electronic Research Group in the
Electrical and Computer Engineering department.
Permanent address: 1317 Colby Dr, Lewisville, TX, 75067
Email: seanyu0518@gmail.com
This thesis was typed by Sheng-Yang Yu.