Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011

www.iiste.org

Optimized SVPWM for Multilevel Inverter

Bandaru Urmila G.. Pulla Reddy Engineering College, Kurnool A.P., India E-mail: urmila913@gmail.com D. Subbarayudu Brindavan Institute of Technology, Kurnool A.P., India E-mail: dsr@gmail.com The research is financed by Asian Development Bank. No. 2006-A171(Sponsoring information) Abstract Multilevel inverters have gained interest in recent years in high-power medium-voltage industry. This paper considered the most popular structure among the transformer-less voltage source multilevel inverters, the diode-clamped converter based on the neutral point converter. This paper proposes a single carrier multi-modulation SVPWM technique with an optimized space vector switching sequence. Simulation results presents comparison of single and multicarrier optimized space vector switching sequence with general switching sequence of nine-level diode-clamped inverter for the parameter total harmonic distortion and fundamental component of voltage. Keywords- Multilevel inverter, SVPWM, total harmonic distortion, Diode-clamped inverter, SCMMGS, MCMMGS, SCMMOS, MCMMOS 1. Introduction Multilevel inverters have drawn tremendous interest in high-power medium-voltage industry. In literature, inverters with voltage levels three or more referred as multilevel inverters. The inherent multilevel structure increase the power rating in which device voltage stresses are controlled without requiring higher ratings on individual devices. They present a new set of features that suits well for use in static reactive power compensation, drives and active power filters. Multilevel voltage source inverter allows reaching high voltages with low harmonics without use of series connected synchronized switching devices or transformers. As the number of voltage levels increases, the harmonic content of output voltage waveform decreases significantly. The advantages of multilevel inverter are good power quality, low switching losses, reduced output dv/dt and high voltage capability. Increasing the number of voltage levels in the inverter increases the power rating. The three main topologies of multilevel inverters are the Diode clamped inverter, Flying capacitor inverter, and the Cascaded H-bridge inverter by Nabae et al. (1981). The PWM schemes of multilevel inverters are Multilevel Sin-Triangle Pulse Width Modulation-SPWM and Space Vector Pulse Width Modulation-SVPWM. Multilevel Sin-Triangle PWM involves comparison of reference signal with a number of level shifted carriers to generate the PWM signal. SVPWM involves synthesizing the reference voltage space vector by switching among the nearest voltage space vectors. SVPWM is considered a better technique of PWM owing to its advantages (i) improved fundamental output voltage (ii) reduced harmonic distortion (iii) easier implementation in microcontrollers and Digital Signal Processor. This paper considered the most popular structure among the transformer-less voltage source multilevel inverters, the diode-clamped converter based on the neutral point converter proposed by Carrara et al.(1992) with SVPWM technique. This paper proposes a single carrier modulation technique with an optimized space vector switching sequence for multilevel inverter. Simulation results presents comparison of single and multicarrier optimized space vector switching sequence with general switching sequence of nine-level diode-clamped inverter for the parameter total harmonic distortion and fundamental component of voltage.

91

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011
2. Diode-Clamped Multilevel Inverter

www.iiste.org

A three-phase nine-level diode-clamped inverter is shown in Fig.1. Each phase is constituted by 16 switches (eight switches for upper leg and eight switches for lower leg). Switches S a1 through Sa8 of upper leg form complementary pair with the switches Sa1 to Sa8 lower leg of the same phase. The complementary switch pairs for phase A are (Sa1, Sa1), (Sa2, Sa2), (Sa3, Sa3), (Sa4, Sa4), (Sa5, Sa5), (Sa6, Sa6), (Sa7, Sa7), (Sa8, Sa8) and similarly for B and C phases. Clamping diodes carry the full load current by Jose Rodriguez et al.(2002) Table1 shows phase to fictitious midpoint o of capacitor string voltage (V AO) for various switchings.
Table 1 Nine-Level Inverter Voltage States Sa1 Sa2 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 Sa3 1 1 1 0 0 0 0 0 0 Sa4 1 1 1 1 0 0 0 0 0 Sa5 1 1 1 1 1 0 0 0 0 Sa6 1 1 1 1 1 1 0 0 0 Sa7 1 1 1 1 1 1 1 0 0 Sa8 1 1 1 1 1 1 1 1 0 VAO +Vdc/2 +3Vdc/8 +Vdc/4 +Vdc/8 0 -Vdc/8
-Vdc/4 -3Vdc/8

-Vdc/2

Figure 1 Circuit Diagram of 3 Phase Nine Level Diode Clamped Inverter

92

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011
818 718 618 518 018 418 318 218 118

www.iiste.org

817

828 717 827 716 838 727 616 837 726 615 836 725 610 847 736 625 510

728 617 738 627 516 848 737 626 515

628 517 638 527 016 748 637 526 015

528 017 538 027 416 648 537 026 415

028 417 038 427 316 548 037 426 315

428 317 438 327 216 048 437 326 215

328 217 338 227 116 448 337 226 115

288 117 238 127 348 237 126 408 347 236 125 308 247 136 458 307 246 135 358 207 146 468 357 206 145 248 137

128

816

138

815 825 710 820 714 824 713 823 712 822 711 832 721 842 731 802 741 852 701 862 751 833 722 611 843 732 621 803 742 631 834 723 612 830 724 613

826 715

148

810

814

835 720 614 845 730 624 513

846 735 620 514

813

812

811

844 733 622 511

840 734 623 512

821

804 743 632 521

800 744 633 522 011

805 740 634 523 012

806 745 630 524 013

807 746 635 205 014

808 747 636 525 010

831

854 703 642 531

850 704 643 532 021

855 700 644 533 022 411

658 507 046 435 320 214 865 750 604 543 032 421

758 607 546 035 420 314 866 755 600 544 033 422 311 875 760 654 503 042 431

858 707 646 535 020 414 867 756 605 540 034 423 312 876 765 650 504 043 432 321 885 770 664 553 002 441

708 647 536 025 410

868 757 606 545 030 424 313 877 766 655 500 044 433 322 211 886 775 660 554 003 442 331

758 607 546 435 420 314 878 767 656 505 040 434 323 212 887 776 665 550 004 443 332 221 785 670 564 053 402 341

608 547 036 425 310

768 657 506 045 430 324 213 888 777 666 555 000 444 333 222 111 786 675 560 054 403 342 231

658 507 046 435 320 214 778 667 556 005 440 334 223 112 787 676 565 050 404 343 232 121 685 570 064 453 302 241

508 047 436 325 210

668 557 006 445 330 224 113 788 677 566 055 400 344 233 122 686 575 060 454 303 242 131

558 007 446 335 220 114 678 567 056 405 340 234 123 687 576 065 450 304 243 132 585 070 464 353 202 141

008 447 336 225 110

208 157 258 107 368 257 106 478 367 256 105 378 267 156 388 277 166 387 276 165 386 275 160 385 270 164 285 170 280 174 286 175 268 157

108

568 057 406 345 230 124 688 577 066 455 300 244 133 586 075 460 354 203 142

058 407 346 235 120

158

578 067 456 305 240 134

068 457 306 245 130

168

841

853 702 641 863 752 601

864 753 602 541

860 754 603 542 031

587 076 465 350 204 143

588 077 466 355 200 144

078 467 356 205 140

278 167 288 177 287 176

178

087 476 365 250 104 485 370 264 153

088 477 366 255 100

801

851 861

873 762 651 872 761

874 763 652 501

870 764 653 502 041

884 773 662 551

880 774 663 552 001

784 673 562 051

780 674 563 052 401

684 573 062 451

680 574 063 452 301

584 073 462 351

580 074 463 352 201

084 473 362 251

080 474 363 252 101

085 470 364 253 102

086 475 360 254 103

486 375 260 154

487 376 265 150

488 377 266 155

188

187

186

185

484 373 262 151

480 374 263 152

380 274 163 384 273 162 284 173 283 172

180

184

883 772 661 882 771 782 671

783 672 561 682 571

683 572 061 582 071

583 072 461 082 471

083 472 361 482 371

483 372 261 382 271

383 272 161 282 171

183

871

182

881

781

681

581

081

481

381

281

181

Figure 2 Nine-Level Inverter State Space Vector Diagram

3. SVPWM Implementation Implementation of SVPWM involves (i) Identification of the sector in which the tip of the reference vector lays (ii) Determination of the nearest three voltage space vectors (ii) Determination of the duration of each of these switching voltage space vectors (iv) Choosing an optimized switching sequence. Space vector diagram of nine-level inverter with its 729 (=39) vectors are shown in Fig 2. Every 60 degrees constitute a sector. Sector1 diagram is shown in Fig 3. Each sector consists of 64 regions 177 vectors. 3.1 Sector and region identification Three phase instantaneous reference voltages (1) are transformed to two phase (2). Every 60 degrees, from zero to 360 degrees constitute a sector [4][5]. Identification of the sector in which the tip of the reference vector lies is obtained by (3).

(1)

93

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011

www.iiste.org

(2) ( ) ; (3)

Where is the angle varies from 0 to 2. Amplitude and angle of the reference vector are obtained from (3). From Parks transformation the di-phase, - components are: (

(4) (5)

Region is obtained by normalizing the di-phase components of the space vector (4)-(5) of an n-level inverter through division by V dc/n-1, where Vdc is the dc link voltage. 3.2 Determination of the duration of nearest three voltage space vectors Switch dwelling duration is obtained from (6)-(7). (6) (7) 3.3 Determination of optimized switching sequence Consider reference vector lying in sector1 region 21. The nearest three space vectors for switching sequence are , , .

64 63

49 48 0

62 61

36 35

47

60 59

46 34 45

25

58 57

24 16 15 9 14 23

33 32

44 0

43

56 55

22

31

42 30 41

21

54 53

8 4 7

13 12

20 0

29 19 28

40 39

52 51

3 1 2

6 5

11 10

18 17

27 26

38 37

50

Figure 3 Sector1 Regions Space Vector Representation

94

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011

www.iiste.org

The space redundant vectors for sector1 region 21, are, for 0 6 8, 4 5 7, 3 0 6, 2 4 5, 1 3 0 (5 redundant vectors), for 4 6 8, 3 5 7, 2 0 6, 1 4 5 (4 redundant vectors), and for 4 5 8, 3 0 7, 2 4 6, 1 3 5 (4 redundant vectors). An optimized switching sequence starts with virtual zero vectors state. A virtual zero vectors are with minimum offset from zero vector of two-level inverter. Based on the principles derived in literature for two-level inverter, for Region 21, switching sequence is 0 6 84 6 8 4 5 8 4 5 7 3 5 7 3 0 7 3 0 6 2 0 6 2 4 6 2 4 5 1 4 5 1 3 5 1 3 0 during a sampling interval and 1 3 0 1 3 5 1 4 5 2 4 5 2 4 6 2 0 6 3 0 6 3 0 7 3 5 7 4 5 7 4 5 8 4 6 8 0 6 8 during the subsequent sampling interval. This sequence uses all the space redundant vectors of each state by Anish Gopinath et al.(2007), (2009). Consider two different outer regions 59 and 60 of Figure3 for switching sequence. Three vertices of region 59 are (2 0 8, 1 4 7), (2 4 8, 1 3 7) and (1 4 8). Virtual zero vector is . The optimized switching sequence is 2 0 8 2 4 8 1 4 8 1 4 7 1 3 7 during a sampling interval and 1 3 7 1 4 7 1 4 8 2 4 8 2 0 8 during the subsequent sampling interval. Considering the region 60, Virtual zero vector is (2 4 8, 1 3 7) and (1 4 8), (1 3 8) are the two other vertices. The optimized switching sequence is 2 4 8 1 4 8 1 3 8 1 3 7 during a sampling interval and 1 3 7 1 3 8 1 4 8 2 4 8 during the subsequent sampling interval [23]. This sequence utilizes vectors. Application of usage of same number of states also for inner regions reduced the total harmonic distortion with increased fundamental component of voltage with single carrier modulation. Extending this for region 21, the sequence is 0 6 84 6 8 4 5 8 4 5 7 during a sampling interval and 4 5 7 4 5 8 4 6 8 0 6 8 during the subsequent sampling interval discarding three redundant states from each vertex. 4. Simulation Results Simulation is carried out on nine-level diode-clamped inverter for four methods of Space Vector PWM technique at switching frequency 1.5 KHz for different modulation indices. (i) SCMMGS-Single Carrier Multi-Modulation for General Switching Sequence (ii) MCMMGS-Multi-Carrier Multi-Modulation for General Switching Sequence (iii) SCMMOS-Single Carrier Multi-Modulation for Optimized Switching Sequence (iv) MCMMOS-Multi-Carrier Multi-Modulation for Optimized Switching Sequence. Multi-Carrier Multi-Modulation results reduced harmonic distortion with reduced fundamental component; however Single Carrier Multi-Modulation results reduced harmonic distortion with highly improved fundamental component of voltage. Optimized switching sequence reduces harmonic distortion compared to General switching sequence. SVPWM-SCMMGS simulation results are shown from Figure4 through Figure7 for modulation index of 0.85. Figure4 comprises pole, phase and line voltage for SCMMGS method. Pole, phase and line voltage for MCMMGS method is Figure6. Line voltage THD for SCMMGS and MCMMGS are shown in Figure5 and Figure7 respectively. SVPWM-SCMMOS results at modulation index of 0.85 are shown from Figure8 through Figure11. Figure8 comprises pole, phase and line voltage for SCMMOS method. Pole, phase and line voltage for MCMMOS method is Figure10. THD of line voltage is shown in Figure9 and Figure11 respectively for SCMMOS and MCMMOS.

95

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011
50 0 -50 50 0 -50

www.iiste.org

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

Selected signal: 1 cycles. FFT window (in red): 1 cycles

0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

50 100
0 -100

-50 0 0 0.002 0.002 0.004 0.004 0.006 0.006 0.008 0.008 0.01 0.01 0.012 0.012 0.014 0.014 0.016 0.016 0.018 0.018 0.02 0.02

Time (s) Figure 4 MCMMGS 0.85 MI Pole, Phase and Line Voltage

1 0.8 0.6 0.4 0.2 0 0 20 40 60 80 100 120 140 160 180 200 Fundamental (50Hz) = 80.82 , THD= 9.57%

Figure 5 MCMMGS 0.85 MI Line Voltage THD

50 0 -50 100 0 -100

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

Selected signal: 1 cycles. FFT window (in red): 1 cycles

0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

1000
100

VabS (V)

0 0
-100 -1000 0 0.002 0.002 0.004 0.004 0.006 0.006 0.008 0.008 0.01 0.012 0.01 0.012 Time (s) Time (s) Phase MI Pole, 0.014 0.014 0.016 0.016 0.018 0.018 0.02 0.02

Figure 6 SCMMGS 0.85

1 0.8 0.6 0.4 0.2 0 0 20 40 60

and Line Voltage

Fundamental (50Hz) = 97.01 , THD= 10.20%

80

100

120

140

160

180

200

Figure 7 SCMMGS 0.85 MI Line Voltage THD

96

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011
50 0 -50 100 0 -100 100

www.iiste.org

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

0.002

Selected signal: 1 0.008 cycles. FFT window (in 0.014 1 cycles red): 0.016 0.004 0.006 0.01 0.012

0.018

0.02

50 0 0 -50 -100

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

0.002 0.004 0.006

0.01 0.012 0.014 0.016 0.018 Figure 8 MCMMOS 0.85 MI(s) Time Pole, Phase and Line Voltage

0.008

0.02

1 Fundamental (50Hz) = 82.03 , THD= 10.87% 0.5

20

40

60

80

100

120

140

160

180

200

Figure 9 MCMMOS 0.85 MI Line Voltage THD

50 0 -50 100 0 -100

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

100 100
0 0

0.002

Selected signal: 1 cycles. FFT window (in red): 1 cycles

0.004 0.006 0.008 0.01 0.012 0.014 0.016

0.018

0.02

-100 -100 0 0

0.002 0.004 0.006

0.002

0.01 0.012 0.014 0.016 0.018 Figure 10 SCMMOS 0.85 MI Pole, Phase and Line Voltage Time (s)

0.004

0.006

0.008

0.008

0.01

0.012

0.014

0.016

0.018

0.02

0.02

1 Fundamental (50Hz) = 97.13 , THD= 9.54% 0.5

20

40

60

80

100

120

140

160

180

200

Figure 11 SCMMOS 0.85 MI Line Voltage THD Table2 gives the Total harmonic Distortion and fundamental component of line voltage for normal modulation range. Figure12 shows chart of Modulation Index Vs THD of line voltage.

97

Innovative Systems Design and Engineering ISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol 2, No 4, 2011
Table 2 Modulation Index Vs THD and Fundamental Component of Voltage MI 0.866 0.85 0.8 0.75 0.7 0.6 SCMMGS THD V1 9.42 98.96 10.20 97.01 12.65 90.91 15.65 84.79 19.35 78.69 26.89 66.32
30 SCMMGS 25 MCMMGS SCMMOS MCMMOS

www.iiste.org

MCMMGS THD V1 11.79 87.03 9.57 80.82 9.45 76.73 15.22 70.38 18.37 56.52 25.67 49.29

SCMMOS THD V1 9.17 98.98 9.54 97.13 10.54 91.5 10.97 85.64 12.75 80.01 12.96 68.39

MCMMOS THD V1 11.89 87.52 10.87 82.03 9.99 78.05 13.26 75.1 11.47 65.67 15.02 60.27

20

15

10

0.6

0.65

0.7

0.75

0.8

0.85

0.9

Figure 12 Mi Vs THD of Nine-Level Inverter 4. References Nabae, Takahashi, Akagi.(1981) A neutral-point clamped PWM inverter, IEEE Transactions on I.A., Vol. IA-17, No. 5, pp. 518-523. Carrara, Gardella, Marchesoni, Salutari, and Sciutto, (1992) A New Multilevel PWM Method: A theoretical Analysis, IEEE Transactions on Power Electronics, Vol. 7, No. 3, July, pp.497-505. Jos Rodrguez, Jih-Sheng Lai, Fang Zheng Peng (2002) Multilevel Inverters: A Survey of Topologies, Controls, and Applications, IEEE Trans., VOL. 49, NO. 4, AUGUST Anish Gopinath, Baiju, (2007) Space Vector PWM for Multilevel Inverters- A Fractal Approach PEDS, Vol.56, No. 4, April, pp 1230-1237 Anish Gopinath, Aneesh Mohammed, and Baiju, (2009) Fractal Based Space Vector PWM for Multilevel Inverters-A Novel Approach IEEE Transactions on Industrial Electronics, Vol.56, No. 4, April, pp 1230-1237

98