GETTING STARTED

Spartan-3 DSP Protoboard is provided with all necessary accessories required by you to use
the Protoboard efficiently.

Accessories.
1. JTAG Communication Cable
2. Operational Manual
3. CD. - Contents of CD
• Data Sheets – Data sheets of the components used on the card are provided for your
reference.
• FT245BM_DRIVER:-USB device driver.
• Hardware:- It contains one folder having UCF, BIT file, Sample VHDL code for
downloading purpose in folder VHDL_xc3s400_PQ208
• Software - there are Three folders, they contain software files required for the three
USB examples provided.
counter_read_write:-It contains two folders
1.D2XX_lib (Library File)
2.Read_Write_VC (Software File )
file-loopback:- It contains two folders
1.D2XX_lib (Library File)

Read_Write_Vc (Software File)

keyboard_ASCII:- It contains two folders
1.D2XX_lib (Library File)
2.Read_Write_VC (Software File)
It is recommended that Visual Studio be installed on your PC

How to Install a USB Driver

• Plug USB cable to USB connector. Windows should first detect the new hardware device with
a “New Hardware Found” message box. Acknowledge this message box.
• Windows then displays the “Found New Hardware” Wizard, which will search for new drivers.
For Driver Installation refer Chapter10
• Your USB device is ready to Work.

PRECAUTIONS - to be followed, while using Protoboard.

• Verify the POWER ON LED status after applying power to the Protoboard.
• Connect the 9 pin D connector of the cable to the Protoboard only after confirming the
above.
• During downloading make sure that the jumper selections are proper. [Refer Chapter 8].
• Before implementation, it is necessary to lock the pins in User Constraint File (UCF) as per
the Protoboard hardware.
• For downloading the bit stream, the downloading circuit requires a stable supply.

1
 CHAPTER 1
INTRODUCTION

ABOUT SPARTAN-3 based DSP ProtoBoard

Universal DSP Protoboard MXS3FK-004-DSP is useful to physically verify DSP algorithms or
simple digital designs. It also has LCD, Stepper Motor, Relay, Thermister and USB interfaces.
This Multipurpose board incorporates all required power supplies, configuration interfaces …etc.
User can design DSP systems using MATLAB -Simulink Environment.
Further these designs can be converted to VHDL codes using System Generator for DSP from
Xilinx, (it has a large set of optimised and parameterizable DSP building blocks).
The DSP system code thus generated can be synthesized and implemented using ISE tool.
The DSP system thus implemented can be downloaded and physically verified using the
universal DSP Protoboard

Advantages of using FPGA

Using FPGAs for implementing DSP functions is one of the preferred ways of implementing
DSP functions and algorithms and has many advantages over - using DSP Processor and
ASICs
• High Performance - upto 100X or more acceleration of DSP algorithms over
implementations in ASIC / DSP Processors.
This is due to the fact that large parallel architectures can be implemented in FPGAs
• Quick turnaround
• Reconfigurable
• One-chip Solution.

SYSTEM GENERATOR for DSP

• System Generator for DSP from Xilinx is a bridge between the Matlab (Simulink) and Xilinx
FPGA design tool. It adds a Xilinx Blockset in the Simulink Library Browser. This blockset
consists of synthesizable blocks for various applications in Communication and DSP. The
“System Generator” block allows automatic generation of VHDL code. This code can be
synthesized and implemented in the target device using Xilinx ISE tool.

SPARTAN-3 [FPGA]
• Spartan-3 family is building on the successor Spartan-IIE family by increasing the amount of
logic resources, the capacity of internal RAM, the total no of I/O’s and overall level of
performance as well as by improving clock management functions.
Features of the Spartan-3 FPGA are:
• Revolutionary 90 nm process technology
• Very low cost, high performance logic solutions for high volume consumer–oriented
application
• Densities as high as 74,880 logic cells’
• 326 MHz system clock rate
• Three separate power supplies for the core (1.2), I/Os(1.2 to 3.3), and special function(2.5V)
• Select I/O signalling
• Abundant, flexible logic cells with registers, wide multiplexer, dedicated 18x18 multiplier,
• Up to 1872 Kbits of total block RAM
• Up to 520 Kbits of total distributed RAM
• Digital clock manager (up to four DCM)
• Eight global clock lines and abundant routing.
• Fully supported by Xilinx ISE development system
• Unlimited reprogram ability.
• Very low cost.

2
 CHAPTER 2
HARDWARE DESCRIPTION

2.1. Features:
• It supports a FPGA - XC3S400-4PQ208 – 400Kgates FPGA in PQ208 pin package.
• Analog Interface: -
Ð Analog Input – Four channels using ADC using AD7891, (500Ksps, 12 bit).
Additional Stereo Jacks are provided for Audio Input.
Ð Thermister interface is given to ADC channel 5.
Ð Analog Output- Four channels using four DAC’s-AD7541. (12 bit, 100 ns conversion
time)
Stereo Jacks are provided for Audio Output.
• Function Generator (using IC 8038)
Ð Provides Sine, Square and Triangular waveforms outputs.
Ð Frequency variable from 60-200 KHz.
• One Anti-aliasing filter at the input of Analog to Digital converter.
• One Reconstruction filter at the output of Digital to Analog converter.
• User interface
Ð Interface for 16 * 2 LCD. (LCD optional)
Ð 16 output LEDs.
Ð Stepper motor interface
Ð Relay interface
Ð 16 DIP switches.
Ð 4 Key Switches.
Ð Four 7-Segment displays.
• PS/2 Keyboard & Mouse Interface –
Ð It handles Data signal that carries a serial stream of bits from the keyboard as each key
is pressed and released.
Ð It configures and initializes the mouse, gets the information sent by the mouse
• VGA Interface
Ð Adjustable width for the red, green and blue output signals.
Ð Flexible timing for the horizontal and vertical sync signals.
• Serial Interface – One RS-232 channel using MAX3223
• USB Interface –USB interface using FTDI (FT245BM)
Ð Single Chip USB interface with no external components, on chip firmware ( with facility
for external EEprom)
Ð Entire USB protocol handled on chip, no USB-specific firmware programming required.
Ð Support data transfer rates upto 1MB/sec. Supports USB Bulk or Isochronous data
transfer modes.
Ð Required device drivers provided free by FTDI. ( D2xx Driver).
Ð Parallel FIFO on peripheral (local) side for transferring data to/from a peripheral and a
host PC makes it easy to interface to any microcontroller, microprocessor, FPGA via IO
ports.
Ð Eight bit data bus with 4 wire handshake interface is provided.
• Stepper Motor Interface
Ð Stepper Motor interface using 12VDC, Steps/Rev-200 motor with step angle of 1.80
• Relay Interface
Ð NO & NC contacts are provided using Relay-12VDC
• User selectable configuration modes.
• User IO’s – Maximum 100 user IOs. (Refer details of Digital IOs).
• On Board regulated Power supply generation that is compatible with device, user only has
to connect external power supply that is provided with this board.

3
2.2 BLOCK DIAGRAM

Block diagram

4
2.3 POWER SUPPLY
• External Power supply is provided as a standard accessory to power the board. Which
powers the digital and analog circuitry on board
• FPGA supplies viz. Vccint & Vcco are generated on board.

2.4 HARDWARE DESCRIPTION

2.4.1 VCCINT & VCCIO

The board power supply section generates all the voltages that are required to FPGA that it can
support.
The voltages required by the FPGA are
• VccINT - 1.2V
• VccAUX -2.5
• VccIO - 3.3 V

2.4.2 FPGA CONFIGURATION

• For downloading the design from PC, a 10 way connector is provided on board.

2.4.3 ANALOG INPUT

Five analog input channels ( In-Channel1 to In-Channel4 and Channel 5 for Thermister ) are
provided using ADC - AD7891, with following specifications
• Input range - +10V to -10 Volts.
Note - AD7891 ADC has eight single ended channels out of which only five channels are used
as analog inputs.

• In-Channel1 and In-Channel2 can take external analog inputs either from the PUT terminal
or audio inputs from the stereo jacks provided.
• In-Channel3 takes an external analog input from the PUT terminal.
• In-Channel4 takes an external analog input from the PUT terminal; user has the option of
cascading the onboard Anti-Aliasing Filter – (a low pass Analog filter) to his input.
Antialiasing filter

5
• Channel5 takes input from Thermister.

2.4.4 ANALOG INPUT CONNECTOR:

• CH1 to CH4 – Four Terminal blocks are provided to connect single ended ANALOG
INPUTS
Ch1 Ch2 Ch3 Ch4
Ch1 In GND Ch2 In GND Ch3 In GND Ch4 In GND
1 2 1 2 1 2 1 2
2.4.4.1 Analog Output
Four analog output channels are provided on-board DAC – AD7541
• Output Range +10 V to -10 Volts, single ended
• Analog output on Out-Channel1 and Out-Channel2 can be routed either to Stereo jacks or
PUT terminals.
• Out-Channel3 is directly connected to PUT terminals.
• Out-Channel4 – user has the option of either connecting its output directly to PUT terminal
or through a “Reconstruction filter” (Low pass analog filter). as-

2.4.4.2-ANALOG OUTNPUT CONNECTOR:

• Vout1 to Vout4 – Four Terminal blocks are provided to provide ANALOG OUTPUTS
Vout1 Vout2 Vout3 Vout4
Vout1 GND Vout2 GND Vout3 GND Vout4 GND
1 2 1 2 1 2 1 2

2.4.5 STEREO JACK CONNECTOR –

Stereo jack connectors are provided taking in / giving out signals to/from for audio systems.

2.4.6 FUNCTION GENERATOR

Function Generator - IC8038 is used on board to generate sine, square, triangular waves in the
frequency range of 60 Hz to 200 KHz.
Output of function generator can be used as analog input to ADC for performing different DSP
applications

6
• Function Generator outputs are available as Sine, Square and Triangular wave at three test
points – SINE, SQUARE and TRIANGULAR respectively.
• Frequency Setting - function generator frequency can be varied in 2-steps
Ð Coarse Frequency - using switch SW8.
Ð Fine Frequency - using potentiometer PR1. for frequency range selection Refer 3.12
• Amplitude Setting - Amplitude of the generated waveform(s) can be adjusted using
potentiometers as follows
Ð PR2 for Sine wave,
Ð PR3 for Square Wave
Ð PR4 for Triangular wave.

2.4.7 STEPPER MOTOR INTERFACE

One stepper motor is provided with onboard interface with the following specification-
• Stepper Motor-SMO-02
Ð Input Voltage – 12 VDC
Ð Step Angle – 1.80
Ð Steps/Revolution – 200

Stepper Motor Connector Details

A1_Coil A2_Coil +12 V B1_coil B2_coil
1 2 3 4 5

2.4.8 RELAY
12V DC, Single contact relay is provided on board, NO & NC contacts are provided on PUT.
Do not connect any external power supply at the PUT.
Connect load of 12V only.

2.4.9 USB
USB interface devices are devices which provide interface between a USB bus and a host
controller (microprocessor, microcontroller, FPGA …etc). They ease the designer’s job of
interfacing their systems to a USB port by taking care of the USB interface and USB protocol.
FTDI USB Interface device has (128 Byte) FIFO receive buffer & (384 Byte) FIFO Transmit
Buffer for high data throughput.

FIFO Receive Buffer (128 Byte): -Data sent from the USB Host to the FIFO via the USB data
out endpoint is stored in the FIFO receive buffer and is removed from the buffer by reading the
FIFO contents using RD#.
FIFO Transmit Buffer (384 Byte): -Data written into the FIFO using WR# is stored in the FIFO
Transmit Buffer the Host removes Data from the FIFO Transmit Data by sending a USB request
for Data from the device data in endpoint.

7
USB Drivers
Required Drivers + DLL S/W Interface are provided on CD supplied with this proto-board and
are also freely downloadable from the FTDI Website.

2.4.10 VGA INTERFACE

The FPGA can generate a video signal for display on a VGA monitor. The FPGA outputs three
bits each of red, green and blue colour information to a simple resistor ladder DAC. This
3 3 3
provides 2 X 2 X 2 = 512 colours. The output of the DAC (Resister network) is sent to the
RGB inputs of a VGA monitor. The FPGA also generates the horizontal and vertical sync pulses
(HSYNC#, VSYNC#).
• Signal levels between 0 (completely dark) and 0.7 V (maximum brightness) control the
intensity of each colour component.

2.4.11 PS/2 INTERFACE –

Ð Keyboard - It handles Data signal that carries a serial stream of bits from the keyboard
as each key is pressed and released.
Ð Mouse - It configures and initializes the mouse, gets the information sent by the mouse

2.4.12 LEDS
There are total 36 LEDs on the Protoboard, which are grouped as follows.
• 3 POWER-ON LED - used for power supply indication.
• DONE LED - indicates successful configuration of FPGA.
• IL0 to IL15 - LEDs indicate the logic level inputs applied by user.
• OL0 to OL15 - LEDs used to monitor outputs.

2.4.13 TEST POINTS [TPS]

Test points are provided on the following signals,
• Supplies - Vcc (5V, 3.3V, 2.5V, 1.2V), GND
• Clocks - Osc1 and Osc2

8
• ADC control Signals – CONVST (start of conversion), EOC ( end of conversion), CS/, WR/,
RD/, Mode.

2.4.14 DIP SWITCH: -

8-way DIP switches [SW1 &SW2]
SW1 & SW2 can be used to apply logic inputs to the FPGA.
Logic Level applied to FPGA through SW1 & SW2 is seen on LEDs IL0 to IL15.
• SW7 is 4- way DIPswitch to select different time constants for Anti-Aliasing Filter.
• SW9 is 4 way DIP switch and is used to select different time constants for Reconstruction
Filter
• SW8 is 4-way DIP Switch and is used to select the frequency range of the Function
generator.

• Note: Only one switch must be on at a time for correct operation of the function generator.

2.4.15 JTAG INTERFACE CONNECTOR

10 Pin FRC male connector is provided for the Download cable
interface. FPGAs and Configuration PROMs can be configured
through this interface.

Configuration Mode selection for FPGAs.

In case of FPGAs, different configuration modes can be selected by
changing the jumper selections. (JP16, JP15, JP14) Refer chapter4

2.4.16 JUMPERS
are provided for:
• Selection of power ON reset circuit.
• Selection of configuration mode.
• Selection of Reference voltages for ADC and DAC
• For details Refer Chapter 8

2.4.17 DIGITAL INPUT OUTPUT CONNECTOR.

• I/O’s from FPGA are provided on four connectors. Each connector is having 3.3V, Ground
and Pure IOs. Details of the IOs are given individually for each adapter in an annexure
supplied with the adaptor.
For XC3S400 (PQ208) IOs are provided on three connectors as follows,
• I/O Connector1 - A 40 pin box type connector – provides 34 user IOs
• I/O Connector2 - A 40 pin box type connector – provides 32 programmable user IOs.
• I/O Connector3 - A 40 pin box type connector – provides 34 programmable user IOs.
Note –

9
Maximum 100 IOs are available out of which 24-IOs are freely available, the remaining 76 IOs
are available to the user when not using onboard features like - Key switches, DIP switches, 7
segment Displays, LEDs, LCD’s, USB, Relay, Stepper motor …etc

2.4.18 CLOCK AND RESET FUNCTIONS

• Footprints available for two Clock Oscillators OSC-1 and OSC-2.
Ð OSC1Æ P76 -------- frequency – 4MHz
Ð OSC2Æ P77 -------- Not present on board (Connected with FPGA )
• Reset Switch - Can be used by user as a manual Reset input.

10
 CHAPTER 3
PRECAUTIONS
Precautions to be followed, while using Protoboard

• Verify the POWER ON LED status after applying power to the Protoboard.
• Connect the 9 pin D connector of the cable to the Protoboard only after confirming the above.
• During downloading make sure that the jumper selections are PROPER
[Refer Chapter 4].
• Check the mode pins (M0 M1 M2 = 1 1 1) while configuring through downloading cable.
• Before implementation, it is necessary to lock the pins in User Constraint File (UCF) as per
the Protoboard hardware.

• For downloading the bit stream, the downloading circuit requires a stable supply;
hence it is recommended to use the power supply provided along with the Protoboard
only

11
 CHAPTER 4
JUMPER SETTINGS AND CONFIGURATION

4.1 JUMPER SETTING FOR USER INTERFACE SELECTION:

DETAILS OF J7
Connecting 1-2 - Disconnects User Interface
Connecting 2-3 - Connects User Interface

4.2Configuration through PROM – JP17

JUMPER SETTING JP1
1-2 Configuration of PROM + FPGA
2-3 Configuration of FPGA

4.3 Analog Input to ADC

Note:- Jumper JP3 is for IN-Channel1 and JP2 for IN-Channel2
JUMPER SETTING JP3 / JP2
1-2 Audio I/P from Stereo Jack
2-3 Analog I/P from PUT

4.4 Anti aliasing filter selection – JP4

Anti-aliasing filter is provided with channel4
JUMPER SETTING JP4
1-2 ADC IN with Anti-Aliasing Filter
2-3 ADC IN without Anti-Aliasing Filter

4.5 Analog Output

Note: - Jumper JP9 is for Out-Channel1 and JP8 for Out-Channel2

JUMPER SETTING JP9/JP8

1-2 Audio O/P to Stereo Jack
2-3 Analog O/P to PUT

4.6 Reconstruction Filter selection JP7

Reconstruction Filter is provided with channel4
JUMPER SETTING JP7
1-2 DAC OUT with Reconstruction Filter
DAC OUT without Reconstruction
2-3
Filter

12
4.7 Potentiometer Details
Note:-
• PR9, PR10, PR11, PR12 and PR13 Potentiometers, are factory configured, do not change
settings.
• If the settings are changed, the Analog output range will change.
• You will have to return the card to the factory for recalibration.

Adjustments Potentiometer
Frequency Adjustment PR1
Square Wave Amplitude Adjustment PR2
Triangular Wave Amplitude Adjustment PR3
Sine Wave Amplitude Adjustment PR4
Offset adjustment of Sine wave PR5
Offset adjustment of Triangular wave PR6
Time constant(R) adjustment of anti-Aliasing Filter PR7
Time constant(R) adjustment of Reconstruction Filter PR8
DAC-1 range adjustment PR9
DAC-2 range adjustment PR10
DAC-3 range adjustment PR11
DAC-4 range adjustment PR12
DAC Reference Voltage Adjustment PR13
LCD Contrast adjustment PR14
Configuration is the process by which the bit-stream of a design, as generated by the Xilinx
development software, is loaded into the internal configuration memory of the FPGA.
SPARTAN-3 device supports both serial configuration, using the master serial and JTAG
modes, we are using JTAG mode for configuration.

4.8 SPECIAL PURPOSE PINS

• Three configuration mode pins (M2, M1, M0) are sampled prior to configuration to determine
the configuration mode. After configuration, these pins can be used as auxiliary I/O
connections.

4.9 CONFIGURATION MODES

Two configuration modes are provided with Spartan 3 device.
• Master Serial Mode (Through PROM)
• Boundary scan mode
Combinations of M0, M1 and M2 inputs select these modes.
Following modes are provided on the protoboard.
• Master Serial Mode while downloading through PROM
• Boundary Scan Mode (pins are brought on connector for details) Refer Chapter 7
MODE SELECTION JUMPER SETTING:
1 2 3
JP16 (M0)
JP14 (M1)
JP15 (M2)
• Connecting 1-2 selects Logic –1, Connecting 2-3 selects Logic- 0
MODE SELECTION TABLE:
Configuration Mode JP16 (M0) JP14 (M1) JP15 (M2)
Master Serial Mode 0 0 0
Boundary Scan Mode 1 0 1

13
• DONE LED is provided on the Protoboard to indicate successful configuration of the device.

4.9.1 MASTER SERIAL MODE

• PROM Through Configuration -
PROM adapter can be connected here
depending on the FPGA adapter used.
• JTAG Chain Selection
While configuring FPGA or PROM; chain
may be formed in one of the two ways as
shown in figure. Jumper JP17 is used for
JTAG Chain Selection. (for details refer
Chapter8)
• When jumper is connected between 1-
2, then PROM and FPGA both gets
added in the JTAG Chain
• When jumper is connected to 2-3, then
only FPGA is available in JTAG
Connection.

14
 CHAPTER 5
OPERATING INSTRUCTIONS TO START NEW DESIGN

5.1 STARTING THE ISE SOFTWARE:

• Start ISE from the Start menu by selecting Start -> Programs -> Xilinx ISE Project
Navigator.

5.2 DESIGN FLOW

• DESIGN ENTRY
• SIMULATION
• SYNTHESIS
• IMPLEMENTATION
• DEVICE PROGRAMMING

15
Sample Design of Half Adder is used to explain the Design Flow.

5.3 DESIGN DESCRIPTION

A Sum

B Carry
Half Adder

5.4 TRUTH TABLE OF HALF ADDER: -

Inputs Output
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

5.5 VHDL CODE FOR HALF ADDER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity half_adder is
Port ( a : in std_logic;
b : in std_logic;
c : in std_logic;
sum : out std_logic;
carry : out std_logic);
end half_adder;

architecture Behavioral of half_adder is

begin
sum <= a xor b ;
carry <= a and b;

end Behavioral;

16
5.6 STEPS TO IMPLEMENT THE HALF ADDER IN THE FPGA USING XILINX
ISE(8.1I)

Step 1 : Start the Xilinx Project Navigator by using the desktop shortcut or by using the Start
Æ Programs Æ Xilinx ISE (8.1i)

Source
Window Workspace

Process
Window
Transcript

Step 2 Create a new project

In the window go to FILE ÆNew project.
Specify the project name and location and say NEXT

Select Device. Use the pull-down arrow to select the Value for each Property Name.
Click in the field to access the pull-down list.

17
Say FINISH. Project summary is seen.

18
Step 3: Creating a new VHD file
Click on the symbol of FPGA device and then right clickÆ Click on new source
ÆVHDL module and give the File name

VHDL
Module

Then say NextÆDefine ports.In this case

• a and b are the input ports defined as in
• sum and carry are output ports defined as out
after this say Next twice and then Finish
Skeleton of the design is shown in the VHDL editor.

19
Step 4: Writing the Behavioral VHDL Code in VHDL Editor
Sample code is given below for this experiment.

Design
Entry

Step 5 Check Syntax

Run the Check syntax Æ Process windowÆ synthesizeÆcheck syntax >, and remove
errors if present.
Step 6 Creating a test bench file
Verify the operation of your design before you implement it as hardware. Simulation
can be done using ISE simulator. For this click on the symbol of FPGA device and
then right clickÆ Click on new source ÆTest Bench Waveform and give the name Æ
Select entityÆFinish.

Select the desired parameters for simulating your design. In this case combinational
circuit and Simulation time.

20
Step 7: Simulate the code
Simulation Tools
ISE tool supports the following simulation tools:
• HDL Bencher is an automated test bench creation tool. It is fully integrated with
Project Navigator.
• ModelSim from Model Technology, Inc., is integrated in Project Navigator to
simulate the design at all steps (Functional and Timing). ModelSim XE, the Xilinx
Edition of Model Technology, Inc.’s ModelSim application, can be installed from
the MTI CD included in your ISE Tool

In source Window from the Drop-down menu select Behavioral Simulation to view the
created test Bench file.

21
 For
simulation

Click on test bench file. Test bench file will open in main window. Assign all the
signals and save File. From the source of process window. Click on Simulate
Behavioral Model in Process window.

Verify your design in wave window by seeing behaviour of output signal with respect
to input signal. Close the ISE simulator window

22
 Simulated
Output

Step 8: Synthesize the design using XST.

Translate your design into gates and optimize it for the target architecture. This is the
synthesis phase.
Again for synthesizing your design, from the source window select,
synthesis/Implementation from the drop-down menu.

Synthesis

Highlight file in the Sources in Project window. To run synthesis, right-click on

Synthesize, and the Run option, or double-click on Synthesize in the Processes for

23
 Current Source window. Synthesis will run, and
• a green check 9will appear next to Synthesize when it is successfully
completed.
• a red cross 8indicates an error was generated and
• a yellow exclamation! mark indicates that a warning was generated, (warnings
are OK).
Check the synthesis report.
If there are any errors correct it and rerun synthesis..

Synthesis
completed
successfully

Step 9: Create Constraints File(UCF)

Click on the symbol of FPGA device and then right clickÆ Click on new source
ÆImplementation Constraints File and give the name Æ Select entityÆFinish.
Click on User Constraint and in that Double Click on Assign Package Pins option in
Process window. Xilinx PACE window opens. Enter all the pin assignments in PACE.,
depending upon target device and number of input and outputs used in your design.
(sample code is given below for given design.)

24
 Pin
assignments

Step 10: Implementing a Design

Once synthesis is complete, you can place and route your design to fit into a Xilinx
device (Spartan-II 200k), and you can also get some post place-and-route timing
information about the design. The implementation stage consists of taking the
synthesized netlist through translation, mapping, and place and route. To check your
design as it is implemented, reports are available for each stage in the implementation
process. Use the Xilinx Constraints Editor to add timing and location constraints for
the implementation of your design. This procedure runs you through the basic flow for
implementation.
Right-click on Implement Design, and choose the Run option, or double left-click on
Implement Design.

Implementation
done

25
Step 11: Generating Programming File
Right-click on Generate Programming File choose the Run option, or double left-click
on Generate Programming File. This will generate the Bit stream
Step 12 Downloading in Boundary Scan Mode.
Note : Xilinx provides 2-tools for downloading purpose, viz.
• iMPACT - is a command line and GUI based tool
• PROM File Formatter

Boundary
Scan Mode

Procedure for downloading using iMPACT

• Boundary Scan Mode
1. Right click on “Configure Device (iMPACT)” -> and Say RUN or Double click
on “Configure Device (iMPACT)”.
2. Right click in workspace and say Initialize chain .The device is seen.
3. Right click on the device and say Program.

If the device is programmed properly, it says Programming Succeeded or else.

Programming Failed. The DONE Led glows green if programming succeeds.
Note:
Before downloading make sure that Protoboard is connected to PC's parallel port with

26
 the cable provided and power to the Protoboard is ON.
Step 13: Apply input through DIP Switches, output is displayed on LEDs
Step 14: Configuration through PROM: Generating PROM file:
FPGA can also be configured in Master Serial Mode through PROM. For this you
need to program the PROM through a .mcs file.
Right click on “Generate PROM,ACE or JTAG file” -> and Say RUN or Double click on
“Generate PROM,ACE or JTAG file”

Specify the PROM file name and location where it is to be generated.

27
Specify the desired parameters of the PROM on board and say ADD then FINISH

Say Generate File from the Process Window.

28
Generate
File

29
PROGRAMMING THE PROM
Note: Check the Jumper setting on the board. Refer the Chapter jumper Setting
Similar to Step 12.Initialize chain through iMPACT. PROM and FPGA devices on
board are seen .Assign the generated mcs file and bit file as desired.
Right click the PROM symbol and say PROGRAM.

Now, whenever the board is powered on in master serial mode, FPGA is configured
through PROM automatically.

30
 CHAPTER 6
PIN ASSIGNMENTS

6.1SPARTAN 3 PQ208 Daughter board Configuration Details

VCCIO 3.3V
VCCINT 1.2, 2.5V
VCC Cable 3.3V

Configuration JTAG Cable Spartan 3 Pin

Connector
Signal Connector Number

TDI J31-9 208 ---

TDO J31-3 158 ---
TMS J31-5 150 ---
TCK J31-1 159 ---
DONE --- 210 ---
MODE0 --- 54 JP1-16
MODE1 --- 55 JP3-14
MODE2 --- 56 JP4-15

CONFIGURATION MODES
Configuration Modes MODE0 MODE1 MODE2
Master Serial /Flash PROM 0 0 0
Boundary Scan Mode 1 0 1

CLOCK & RESET

Signal Spartan 3 Pin Number
GCLK1 76
GCLK2 77
RESET 78

RS232 SERIAL PORT

RXD1 205
TXD1 204

SPARTAN 3 PQ208 – connections details of on board peripherals

• ADC
Function FPGA Pin Number Function FPGA Pin Number
"DB0" 45 "MODE" 72
"DB1" 46 "EOC" 44
"DB2" 57 "\CONVST\" 48
"DB3" 58 "\CS\" 50
"DB4" 61 "\RD\" 51
"DB5" 62 "\WR\" 52
"DB6" 63
"DB7" 64
"DB8" 65
"DB9" 67
"DB10" 68
"DB11" 71

31
• STEPPER MOTOR INTERFACE
Function FPGA Pin Number
A1_COIL 43
A2_COIL 42
B1_COIL 37
B2_COIL 39
RELAY0 40

• DAC
Function FPGA Pin Number Function FPGA Pin Number
"DAC0" 81 "EN1" 87
"DAC1" 79 "EN2" 85
"DAC2" 100 "EN3" 86
"DAC3" 97 "EN4" 74
"DAC4" 93
"DAC5" 90
"DAC6" 94
"DAC7" 95
"DAC8" 96
"DAC9" 102
"DAC10" 101
"DAC11" 80

• VGA INTERFACE
Function FPGA Pin Number Function FPGA Pin Number
"RED0" 7 "BLUE0" 200
"RED1" 5 "BLUE1" 199
"RED2" 4 "BLUE2" 198
"GREEN0" 3 HOR_SYNC 196
"GREEN1" 2 VER_SYNC 197
"GREEN2" 203

• USB INTERFACE
Function FPGA Pin Number Function FPGA Pin Number
USB_D0 106 RD# 116
USB_D1 107 WR# 117
USB_D2 108 TXE# 119
USB_D3 109 "RXF# 120
USB_D4 111
USB_D5 113
USB_D6 114
USB_D7 115

• INPUT SWITCHES
FPGA Connector FPGA
Connector Pin
Function Pin Pin Function Pin
Number
Number Number Number
"IL0" 141 J1-7 "IL8" 131 J1-17
"IL1" 140 J1-8 "IL9" 130 J1-18
"IL2" 139 J1-11 "IL10" 128 J1-21
"IL3" 138 J1-12 "IL11" 126 J1-22
"IL4" 137 J1-13 "IL12" 125 J1-23
"IL5" 135 J1-14 "IL13" 124 J1-24
"IL6" 133 J1-15 "IL14" 123 J1-25
"IL7" 132 J1-16 "IL15" 122 J1-26

32
• OUTPUT LEDs
FPGA Connector FPGA
Connector Pin
Function Pin Pin Function Pin
Number
Number Number Number
“OL0” 161 J2-34 “OL8” 152 J2-38
“OL1” 172 J2-24 “OL9” 167 J2-28
“OL2” 156 J2-43 “OL10” 150 J2-37
“OL3” 171 J2-33 “OL11” 166 J2-27
“OL4” 155 J2-36 “OL12” 149 J1-1
“OL5” 169 J2-26 “OL13” 165 J2-32
“OL6” 154 J2-35 “OL14” 148 J1-2
“OL7” 168 J2-25 “OL15” 162 J2-31

• SEVEN SEGMENT DISPLAY

FPGA Connector FPGA
Connector Pin
Function Pin Pin Function Pin
Number
Number Number Number
“SEGA” 189 J2-8 “SEGE” 184 J2-14
“SEGB” 190 J2-7 “SEGF” 183 J2-13
“SEGC” 187 J2-12 “SEGG” 182 J2-16
“SEGD” 185 J2-11 “SEGDP” 181 J2-15
"CSDIS0" 175 J2-18 "CSDIS2" 178 J2-22
"CSDIS1" 176 J2-17 "CSDIS3" 180 J2-21

• LCD DISPLAY
FPGA Connector FPGA
Connector Pin
Function Pin Pin Function Pin
Number
Number Number Number
"DL0" 33 J3-32 "E" 36 J3-33
"DL1" 31 J3-31 "R/W" 35 J3-34
"DL2" 29 J3-28 "RS" 34 J3-35
"DL3" 28 J3-27
"DL4" 27 J3-26
"DL5" 26 J3-25
"DL6" 24 J3-24
"DL7" 22 J3-23

• USER I/O’S

FPGA Connector FPGA

Connector Pin
Function Pin Pin Function Pin
Number
Number Number Number
IO1 21 J3-22 IO6 15 J3-15
IO2 20 J3-21 IO7 13 J3-14
IO3 19 J3-18 IO8 12 J3-13
IO4 18 J3-17 IO9 11 J3-12
IO5 16 J3-16 IO10 10 J3-11
IO6 15 J3-15 IO11 9 J3-8

PS/2 INTERFACE
Function FPGA pin Number
Mouse Data 191
Mouse Clock 194

33
 CHAPTER 7
DESIGN EXAMPLES
Some experiments which can be implemented and verified using DSP PROTOBOARD.
• Digital Low-Pass Filter.
• Digital High-Pass Filter.
• Digital Band-Pass Filter
• Digital Band-Stop Filter
• Digital Multirate Filters
• Image filtering
• FFT Processor
• Direct Digital Synthesis

9.1 ADC-DAC Controller in Verilog

• Description : Combines the ADC-DAC Controller module and User Generated module.

//Verilog code for ADC (AD7891) and DAC (AD 7541) interfacing

module lowpassvlog (smpclk,dac_out,en,cs_ad7891,convst_ad7891,

wr_ad7891,rd_ad7891,mode_ad7891,reset,clk,
dac_sel, bit_trunc,ch_adc,db_7891);

output smpclk,cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891;
output [11:0] dac_out;
output [3:0] en;

input clk, reset;

input [7:0] bit_trunc;
input [1:0] dac_sel;
input [1:0] ch_adc;
inout [11:0] db_7891;

reg [3:0] en;

reg cs_ad7891,convst_ad7891,wr_ad7891,rd_ad7891,mode_ad7891,convst_ad7891_s;

wire sampling_clk,wr_s,rd_s;
wire [11:0] dac_out_s;
wire [21:0] dacout;

`define reset_1 2'd0

`define write_cwr 2'd1
`define start_conv 2'd2
`define read_data 2'd3

reg [1:0] ps_1;

reg [1:0] ns_1;
reg [3:0] div;
wire [5:0] conc;
wire [11:0] conc1;
reg [15:0] div_adc;
reg [11:0] adcin,db_7891_s;
wire clk_s;

always @ (posedge reset or posedge clk)

begin
if (reset)
div = 4'b0000;
else
if (div == 4'b1001)
div = 4'b0000;

34
 else
div = div + 4'b0001;
end

assign clk_s = (div == 4'b1001) ? 1'b1:1'b0;

always @ (posedge reset or posedge clk_s)

begin
if (reset)
div_adc = 16'd0;
else
div_adc = div_adc + 1;
end

assign sampling_clk = div_adc[2];

assign smpclk = sampling_clk;

always @ (posedge reset or posedge sampling_clk)

begin
if (reset)
ps_1 = `reset_1;
else
ps_1 = ns_1;
end

always @ (ps_1)
begin
case (ps_1)
`reset_1 : ns_1 = `write_cwr;
`write_cwr : begin
cs_ad7891 = 1'b0;
ns_1 = `start_conv;
end
`start_conv : ns_1 = `read_data;
`read_data : begin
cs_ad7891 = 1'b0;
ns_1 = `reset_1;
end
endcase
end

assign conc = {1'b0,ch_adc,3'b0};

assign db_7891[5:0] = (wr_s == 1'b0) ? conc : 6'bZZZZZZ;

always @ (posedge reset or posedge sampling_clk)

begin
if (reset)
convst_ad7891_s = 1'b0;
else
convst_ad7891_s = wr_s;
end

always @ (convst_ad7891_s)
convst_ad7891 = convst_ad7891_s;

always @ (posedge reset or negedge sampling_clk)

begin
if (reset)
db_7891_s = 12'b0;
else if (!rd_s)
db_7891_s = db_7891;
end

always @ (db_7891_s)

35
adcin = db_7891_s;

always
mode_ad7891 = 1'b1;

assign wr_s = (ps_1 == `write_cwr) ? 1'b0 :1'b1;

assign rd_s = (ps_1 == `read_data) ? 1'b0 : 1'b1;

always @ (rd_s or wr_s)

begin
wr_ad7891 = wr_s;
rd_ad7891 = rd_s;
end

always @ (dac_sel)
begin
case (dac_sel)
2'b00 : en = 4'b1000;
2'b01 : en = 4'b0100;
2'b10 : en = 4'b0010;
2'b11 : en = 4'b0001;
default : en = 4'b0000;
endcase
end

lowpass u1(.clk(div_adc[4]),.gateway_in(adcin),.gateway_out(dacout));

assign dac_out_s = bit_trunc[0] ? dacout[21:10] :

bit_trunc[1] ? dacout[20:9] :
(bit_trunc[2] ? dacout[19:8] :
(bit_trunc[3] ? dacout[18:7] :
(bit_trunc[4] ? dacout[17:6] :
(bit_trunc[5] ? dacout[16:5] :
(bit_trunc[6] ? dacout[15:4] :
(bit_trunc[7] ? dacout[14:3]:
dacout[13:2])))))));

assign conc1 = {dac_out_s[11],~dac_out_s[10:0]};

assign dac_out = (dac_out_s[11] == 0) ? (conc1 + 1) : conc1;
endmodule

36
9.2 ADC-DAC Controller in VHDL
• --Description : Combines the ADC-DAC Controller module and User Generated module.
------VHDL code for ADC (AD7891) and DAC (AD 7541) interfacing----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity adc_dac_test is
generic (n : natural := 21);
Port (
clk : in std_logic; -- Local clock
reset : in std_logic; -- Local reset signal
----------------------------- For ADC1(7891)---------------------
adc_clk : out std_logic; --sampling frequency to ADC
cs_ad7891 : out std_logic; --chip select
convst_ad7891 : out std_logic; --conversion start
wr_ad7891 : out std_logic; --write
rd_ad7891 : out std_logic; --read
eoc_ad7891 : in std_logic; --end of conversion
mode_ad7891 : out std_logic; --mode=1 for parallel
db_7891 : inout std_logic_vector(11 downto 0); --bidirectional
----------------------------------For DAC-----------------
bit_trun : in std_logic_vector( 7 downto 0);
----------------------------------------------------------
--DAC selection. IL0 and IL1 are used
----------------------------------------------------------
dac_sel : in std_logic_vector(1 downto 0);

----------------------------------------------------------
--- Input channel selection for ADC IL6 and IL7 are used for Ch_adc
---00 for ch1, 01 for ch2, 10 for ch3,11 for ch4
-------------------------------------------------------------
ch_adc : in std_logic_vector( 1 downto 0);
dac_out : out std_logic_vector(11 downto 0); ---Output to DAC
en : out std_logic_vector( 3 downto 0) ---DAC latch en
);

end adc_dac_test;

architecture Behavioral of adc_dac_test is

type state_1 is (reset_1, write_cwr, start_conv, read_data);

signal ps_1, ns_1 : state_1;
signal dac_out_s : std_logic_vector(11 downto 0);
signal dacout : std_logic_vector(n downto 0);
----------------------- -------------------------------
---This should be changed as per input on board clock
----------------------------------------------------------
signal div_adc : std_logic_vector(15 downto 0
signal decade : std_logic_vector( 3 downto 0 );
signal sampling_clk : std_logic;
signal wr_s : std_logic;
signal clk_s : std_logic;
signal rd_s : std_logic;
signal convst_ad7891_s : std_logic;
signal db_7891_s : std_logic_vector( 11 downto 0 );

37
component lowpass
port (
clk :in std_logic;
gateway_in : in std_logic_vector(11 downto 0);
gateway_out : out std_logic_vector(21 downto 0)
);
end component;
begin
-----------------------------Clk Divider------------------------
--- Decade counter is used because on board clock is 4 MHz.
-- In case of 20/40 MHz we have to use decade counter to get 2/4 MHz.
-- In case of 4 MHz bypass decade counter.
---This arrangement is made so as to design filter or any other application -
--irrespective of input
-- clk at particular clock frequency.
---Otherwise every time we will have to change frequency of our design
--- We cannot have similar frequency by direct division of input clock
----20/40/4 MHz.
--- For example 4 divided by 5 FF to have 62.5KHz.if we want this
--- Frequency from 20/40 MHz clock we will get 78.125.

process(clk, reset)
begin
if(reset = '1') then
decade <= (others => '0');
elsif(clk'event and clk = '1') then
if decade="1001" then
decade<=(others=>'0');
else
decade <= decade + 1;
end if;
end if;
end process;
------------------------------------------------------------------------
clk_s<='1' when decade="1001" else
'0';
------------------------------------------------------------------------
process(clk_s, reset)
begin
if(reset = '1') then
div_adc <= (others => '0');
elsif(clk_s'event and clk_s = '1') then
div_adc <= div_adc + 1;
end if;
end process;

sampling_clk <=div_adc(2) ;
------------------------------------------------------------------------
--- Input clock is very fast so divided clock is used as sampling clock to
--- FSM. FSM will divide sampling clock by four so sampling clock
--- for ADC is 62.5KHz.
------------------------------------------------------------------------

adc_clk <= sampling_clk;

------------------------------------------------------------------------
--- Used just for checking, mapped to output LED OL0.
-------------------------------------------------------------------------
process(reset, sampling_clk)
begin
if(reset = '1' ) then
ps_1 <= reset_1;
elsif(sampling_clk'event and sampling_clk = '1') then
ps_1 <= ns_1;

38
 end if;
end process;
-------------------------------------------------------------------------
process(ps_1)
begin
case ps_1 is
when reset_1 =>
ns_1 <= write_cwr;
when write_cwr =>
ns_1 <= start_conv;
when start_conv =>
ns_1 <= read_data;
when read_data =>
ns_1 <= reset_1;
end case;
end process;

cs_ad7891 <= '0' when (ps_1 = read_data or ps_1 = write_cwr) else

'1';
wr_s <= '0' when (ps_1 = write_cwr) else
'1';
wr_ad7891 <= wr_s;

rd_s <= '0’ 'when (ps_1 = read_data) else

'1';
rd_ad7891 <= rd_s;
mode_ad7891 <= '1'; -- set parallel mode of ADC
------------------------------------------------------------------------
--- Write channel number
------------------------------------------------------------------------

db_7891(5 downto 0) <= '0' & ch_adc & "000" when wr_s = '0' else
(others => 'Z');

-----------------------------convst------------------------
process(reset, sampling_clk)
begin
if(reset = '1') then
convst_ad7891_s <= '0';
elsif(sampling_clk'event and sampling_clk = '1') then
convst_ad7891_s <= wr_s;
end if;
end process;

convst_ad7891 <= convst_ad7891_s;

--------------------------read adc--------------------------
process(reset,clk,rd_s)
begin
if(reset = '1') then
db_7891_s <= (others => '0');
elsif(sampling_clk'event and sampling_clk = '0') then
if(rd_s = '0') then
db_7891_s <= db_7891;
end if;
end if;
end process;
------------------ write ADC Data to DAC -------------------------
dac_out_s <= dacout(n downto n-11) when bit_trun(0)='1' else
dacout(n-1 downto n-12) when bit_trun(1)='1' else
dacout(n-2 downto n-13) when bit_trun(2)='1' else
dacout(n-3 downto n-14) when bit_trun(3)='1' else
dacout(n-4 downto n-15) when bit_trun(4)='1' else

39
 dacout(n-5 downto n-16) when bit_trun(5)='1' else
dacout(n-6 downto n-17) when bit_trun(6)='1' else
dacout(n-7 downto n-12) when bit_trun(7)='1' else
dacout(n-8 downto n-12) ;
dac_out<=(dac_out_s(11)&( not dac_out_s( 10 downto 0))) +'1' when
dac_out_s(11)='0' else
dac_out_s(11)&( not dac_out_s( 10 downto 0));
----------------------DAC selection logic--------------------------
process(dac_sel)
begin
case dac_sel is
when "00" => en<="1000" ;
when "01" => en<="0100";
when "10"=> en<="0010";
when "11"=> en<="0001";
when others=> null;
end case;
end process;
Inst_untitled: lowpass port map
(
------------------------------------------------------------------------
---Filter is operating at 62.5KHz so we have divided the clock
------------------------------------------------------------------------
clk =>div_adc(4) ,
gate way_in =>db_7891_s ,
gateway_out =>dacout
);

end Behavioral;

Note :
The component name represented in BOLD (e.g. lowpass) letters is required to be changed
according to the entity name in the module generated by user.
The value of n must be equal to the bus-width of the Gateway_out signal in the module
generated by user.

9.3 Steps to design FIR filter in Simulink:

Blocks required :
FIR
Gateway-In, Gateway-out
Signal Generator
Scope
System Generator
Where to find
Xilinx - DSP Blockset
Xilinx – Matlab i/o
Simulink – Sources
Simulink – Sinks
Xilinx – Basic Elements

Inputs to FIR Block :

Coeff. = Computed according to the “window function”
No. of Bits per coeff = 12
Binary Point Position = 8
Latency = 14

Inputs to Gateway-In Block:

No. of Bits per coeff = 12
Binary Point Position = 8

Inputs to System Generator Block:

Device Family = Spartan-III
Target Directory = User defined
Check in “Create Testbench” option
Click on “Generate”

40
Steps to implement the Filter in DSP-Protoboard:
• Change the device type to XC3S400-4PQ208
• Add source files : lowpass.vhd, adc_7891.vhd
• Change the name of the component in “lowpass.vhd” according to the entity name in the
VHDL file generated by system generator (project name).
• Assign the generic number n in “lowpass.vhd” the value equal to the Gateway_out
signal’s bus-width.
• Add “UCF” file at the “implement design” step.

41
 CHAPTER 8
USB DRIVER INSTALLATION
The following sections describe WDM driver installation.
The Windows PnP Manager is responsible for detecting devices and prompting the user for the
correct driver.
To assign a driver to a device, Windows refers to an INF file. The INF file provides instructions
for Windows as to which driver files to install and which registry entries to insert.

10.1 STEPS TO INSTALL USB DRIVER

Check system properties> Device manager > Universal Serial Bus, there is no FTDI FT8U2XX
device driver exist.

42
• After plugging USB Cable Windows Driver Model detects new hardware
• Click “Next” button

• Select “Search for a suitable driver for my device (recommended)” option. Click “Next”
Button.

• Select “Specify a location” & “Microsoft Windows Update” options. Click “Next” Button.

43
 • Click “Browse” & Specify location of ” FTD2XX.INF” file which is available in Deliverable
(CD).
[Note:-Deliverable CD contains “FT245BM_DRIVER” folder, Copy
” FTD2XX.INF” file from this folder into local Drive (D, E, F). Specify the path of ” FTD2XX.INF” ]

• Click “Next” Button, it will copy required files from FT245BM_DRIVER” folder from
Deliverable.

44
 • Click “Finish” Button. Check System properties> Device manager>Universal Serial Bus
for “FTDI FT8U2XX Device” driver.

[Note- When the P.C detects that a device has been plugged in, it automatically interrogates
the device to learn its capabilities and requirement. From this information, the P.C automatically
loads the device’s driver into the operating systems. When the device is unplugged, the
operating system automatically logs it off and unloads its driver.]

Your system is ready to communicate through USB port.

45
 CHAPTER 9
GLOSSARY
Aliasing
The process where a sinusoid changes from one frequency to another as a result of sampling or
other nonlinear action. Usually results in a loss of the signal's information.
Antialias Filter
Low- pass analog filter placed before an analog- to- digital converter. Removes frequencies
above one- half the sampling rate that would alias during conversion.
Autocorrelation
A signal correlated with itself. Useful because the Fourier transform of the autocorrelation is the
power spectrum of the original signal.
Bit Reversal Sorting
Algorithm used in the FFT to achieve an interlaced decomposition of the signal. Carried out by
counting in binary with the bits flipped left- for- right.
Blackman Window
A smooth curve used in the design of filters and spectral analysis, calculated f r o m

Where n runs from 0 to M.

Butterfly
The basic computation used in the FFT. Changes two complex numbers into two other complex
numbers.
Butterworth Filter
Separates one band of frequencies from another; fastest roll- off while keeping the passband
flat; can be analog or digital. Also called a maximally flat filter.
Carrier Wave
Term used in amplitude modulation of radio signals. Refers to the high frequency sine wave that
is combined with a lower frequency information-carrying signal.
Causal Signal
Any signal that has a value of zero for all negative numbered samples.
Causal System
A system that has a zero output until a nonzero value has appeared on its input (i. e., the input
causes the output). The impulse response of a causal system is a causal signal.
Chebyshev Filter
Used for separating one band of frequencies from another. Achieves a faster roll- off than the
Butterworth by allowing ripple in the passband. Can be analog or digital.
Chirp System
Used in radar and sonar. An impulse is converted into a longer duration signal before
transmission, and compressed back into an impulse after reception.
Circularity
The appearance that the end of a signal is connected to its beginning. This arises when
considering only a single period of a periodic signal.
Companding
An "s" shaped nonlinearity allows voice signals to be digitized using only 8 bits instead of 12
bits. Europe uses "A" law, while the United States uses the mu law version.
Complex DFT
The discrete Fourier transforms using complex numbers. A more complicated and powerful
technique than the real DFT.
Continuous Signal
A signal formed from continuous (as opposed to discrete) variables.
Example: a voltage that varies with time. Often used interchangeably with analog signal.
Correlation
Mathematical operation carried out the same as convolution, except a left- for- right flip of one
signal. This is an optimal way to detect a known waveform in a signal

46
Cutoff Frequency
In analog and digital filters, the frequency separating the passband from the transition band.
Often measured where the amplitude is reduced to 0.707 (- 3dB).
Decimation
Reducing the sampling rate of a digitized signal. Generally involves low- pass filtering followed
by discarding samples.
Delta- Sigma
Analog to- digital conversion method popular in voice and music processing. Uses a very high
sampling rate with only a single bit per sample, followed by decimation.
Discrete Signal
A signal that uses quantized variables, such as a digitized signal residing in a computer
DSP Microprocessor
A type of microprocessor designed for rapid math calculations. Often has a pipeline and/ or
Harvard architecture. Also called a RISC
Elliptic Filter
Used to separate one band of frequencies from another. Achieves a fast roll- off by allowing
ripple in the passband and the stopband. Can be used in both analog and digital designs.
Fast Fourier Transform (FFT)
An efficient algorithm for calculating the discrete Fourier transform (DFT). Reduces the
execution time by hundreds in some cases.
Filter Kernel
The impulse response of a filter implemented by convolution. Also known as the convolution
kernel and the kernel.
Finite Impulse Response (FIR)
An impulse response that has a finite number of nonzero values. Often used to indicate that a
filter is carried out by using convolution, rather than recursion.
Fixed Point
One of two common ways that computers store numbers; usually used to store integers.
Floating Point
One of the two common ways that computers store numbers. Floating point uses a form of
scientific notation, where a mantissa is raised to an exponent.
Fourier Transform
A family of mathematical techniques based on decomposing signals into sinusoids. In the
complex version, signals are decomposed into complex exponentials.
Frequency Domain
A signal having frequency as the independent variable. The output of the Fourier transform.
Frequency Response
The magnitude and phase changes that sinusoids experience when passing through a linear
system. Usually expressed as a function of frequency. Often found by taking the Fourier
transform of the impulse response.
Fundamental Frequency
The frequency that a periodic waveform repeats itself.
Hamming Window
A smooth curve used in the design of filters and spectral analysis, calculated from
Where n runs from 0 to M.
Harmonics
The frequency components of a periodic signal, always consisting of integer multiples of the
fundamental frequency. The fundamental is the first harmonic; twice this frequency is the
second harmonic, etc.
Impulse
A signal composed of all zeros except for a very brief pulse. For discrete signals, the pulse
consists of a single nonzero sample. For continuous signals, the width of the pulse must be
much shorter than the inherent response of any system the signal is used
Impulse Response
The output of a system when the input is a normalized impulse (a delta function).
Impulse Train
A signal consisting of a series of equally spaced impulses.

47
Infinite Impulse Response (IIR)
An impulse response that has an infinite number of nonzero values, such as a decaying
exponential. Often used to indicate that a filter is carried out by using recursion, rather than
convolution.
Interpolation
Increasing the sampling rate of a digitized signal. Generally done by placing zeros between the
original samples and using a low- pass filter.
Inverse Transform
The synthesis equation of the Fourier transform, calculating the time domain from the frequency
domain.
Linear Phase
A system with a phase that is a straight line. Usually important because it means the impulse
response has left- to- right symmetry, making rising edges in the output signal look the same as
falling edges.
Matched Filtering
Method used to determine where, or if, a know pattern occurs in a signal. Matched filtering is
based on correlation, but implemented by convolution.
Moving Average Filter
Each sample in the output signal is the average of many adjacent samples in the input signal.
Can be carried out by convolution or recursion.
Multirate
Systems that use more than one sampling rate. Often used in ADC and DAC to obtain better
performance, while using less electronics.
Nyquist Frequency Nyquist Rate
These terms refer to the sampling theorem, but are used in different ways by different authors.
They can be used to mean four different things the highest frequency contained in a signal,
twice this frequency, the sampling rate, or one- half the sampling rate.
Passband
The band of frequencies a filter is designed to pass unaltered.
Pole
Term used in the Laplace transform and z-transform. When the s- domain or z- domain transfer
function is written as one polynomial divided by another polynomial, the roots of the
denominator are the poles of the system, while the roots of the numerator are the zeros.
Quantization Error
The error introduced when a signal is quantized.
Real DFT
The discrete Fourier transform using only real (ordinary) numbers. A less powerful technique
than the complex DFT, but simpler.
Real FFT
A modified version of the FFT. About 30% faster than the standard FFT when the time domain
is completely real (i. e., the imaginary part of the time domain is zero).
Roll- off
Jargon used to describe the sharpness of the transition between a filter's passband and
stopband. A fast roll- off means the transition is sharp; a slow roll- off means it is gradual.
Sampling Theorem
If a continuous signal composed of frequencies less than f is sampled at 2f, all of the information
contained in the continuous signal will be present in the sampled signal. Frequently called the
Shannon sampling theorem or the Nyquist sampling theorem.
Signal
A description of how one parameter varies with another parameter.
Example: a voltage that varies with time.
Stopband
The band of frequencies that a filter is designed to block.
Stopband Attenuation
The amount by which frequencies in the stop band are reduced in amplitude, usually expressed
in decibels. Used to describe a filter's performance.

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Time Domain
A signal having time as the independent variable. Also used as a general reference to any
domain the data is acquired in.
Time Domain Aliasing
Aliasing occurring in the time domain when an action is taken in the frequency domain. Circular
convolution is an example.
Transition Band
Filter jargon; the band of frequencies between the passband and stopband where the roll-off
occurs.
Zero
A term used in the Laplace & z- transforms. When the s- domain or z- domain transfer function
is written as one polynomial divided by another polynomial, the roots of the numerator are the
zeros of the system.

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 TABLE OF CONTENTS

GETTING STARTED ................................................................................................................... 1

ACCESSORIES. ................................................................................................................... 1
READ_WRITE_VC (SOFTWARE FILE) ............................................................................... 1
HOW TO INSTALL A USB DRIVER ..................................................................................... 1
PRECAUTIONS - TO BE FOLLOWED, WHILE USING PROTOBOARD............................. 1

CHAPTER 1 ................................................................................................................................. 2
INTRODUCTION ...................................................................................................................... 2
ABOUT SPARTAN-3 BASED DSP PROTOBOARD ............................................................ 2
ADVANTAGES OF USING FPGA ........................................................................................ 2
SYSTEM GENERATOR FOR DSP....................................................................................... 2
SPARTAN-3 [FPGA] ............................................................................................................. 2

CHAPTER 2 ................................................................................................................................. 3
HARDWARE DESCRIPTION ................................................................................................... 3
2.1. FEATURES: ................................................................................................................... 3
2.2 BLOCK DIAGRAM ......................................................................................................... 4
2.3 POWER SUPPLY ........................................................................................................... 5
2.4 HARDWARE DESCRIPTION.......................................................................................... 5
2.4.4 ANALOG INPUT CONNECTOR: ................................................................................. 6
2.4.5 STEREO JACK CONNECTOR – ................................................................................. 6
2.4.11 PS/2 INTERFACE – .................................................................................................. 8
2.4.13 TEST POINTS [TPS]................................................................................................. 8
2.4.14 DIP SWITCH: -........................................................................................................... 9
2.4.17 DIGITAL INPUT OUTPUT CONNECTOR. ................................................................ 9

CHAPTER 3 ............................................................................................................................... 11
PRECAUTIONS...................................................................................................................... 11

CHAPTER 4 ............................................................................................................................... 12
JUMPER SETTINGS AND CONFIGURATION....................................................................... 12
4.1 JUMPER SETTING FOR USER INTERFACE SELECTION: ....................................... 12
4.2CONFIGURATION THROUGH PROM – JP17.............................................................. 12
4.3 ANALOG INPUT TO ADC............................................................................................. 12
4.4 ANTI ALIASING FILTER SELECTION – JP4 ............................................................... 12
4.5 ANALOG OUTPUT ....................................................................................................... 12
4.6 RECONSTRUCTION FILTER SELECTION JP7 .......................................................... 12
4.7 POTENTIOMETER DETAILS ....................................................................................... 13
4.8 SPECIAL PURPOSE PINS ........................................................................................... 13
4.9 CONFIGURATION MODES.......................................................................................... 13

CHAPTER 5 ............................................................................................................................... 15
OPERATING INSTRUCTIONS TO START NEW DESIGN..................................................... 15
5.1 STARTING THE ISE SOFTWARE:............................................................................... 15
5.2 DESIGN FLOW ............................................................................................................. 15
5.3 DESIGN DESCRIPTION............................................................................................... 16
5.4 TRUTH TABLE OF HALF ADDER: -............................................................................. 16
5.5 VHDL CODE FOR HALF ADDER................................................................................. 16
5.6 STEPS TO IMPLEMENT THE HALF ADDER IN THE FPGA USING XILINX ISE(8.1I)17

CHAPTER 6 ............................................................................................................................... 31
PIN ASSIGNMENTS............................................................................................................... 31

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 6.1SPARTAN 3 PQ208 DAUGHTER BOARD CONFIGURATION DETAILS..................... 31

CHAPTER 7 ............................................................................................................................... 34
DESIGN EXAMPLES.............................................................................................................. 34
9.1 ADC-DAC CONTROLLER IN VERILOG....................................................................... 34
9.2 ADC-DAC CONTROLLER IN VHDL ............................................................................. 37
9.3 STEPS TO DESIGN FIR FILTER IN SIMULINK:.......................................................... 40

CHAPTER 8 ............................................................................................................................... 42
USB DRIVER INSTALLATION................................................................................................ 42
10.1 STEPS TO INSTALL USB DRIVER............................................................................ 42

CHAPTER 9 ............................................................................................................................... 46
GLOSSARY ............................................................................................................................ 46

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