Code: R7411001

1
(Common to Electronics & Instrumentation Engg, Electronics Computer Engg)

IV B.Tech I Semester (R07) Regular & Supplementary Examinations, Nov/Dec 2011 VLSI DESIGN Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 2 (a) (b) Explain with neat sketches CMOS fabrication using twin tub process. Define the terms SSI, MSI, LSI and VLSI. Define the terms fan out, fan in, propagation delay and noise margin of a logic family. Design a stick diagram for two input N Mos NAND and NOR gates. Implements the following gates with p Mos transistors only and explain its working 2 input AND gate. 4 input NOR gate. Explain about the following Multipliers. Parity generators. Explain about the programmable logic arrays (PLAs) in detail. Design a circuit using PAL to implement the following Max Marks: 80

3 4 (a) (b) 5 (a) (b) 6 (a) (b)

7 (a) (b) 8 (a) (b)

Explain the circuit design flow in VHDL synthesis. Explain about the design verification tools. Explain about the following Chip level test techniques. System level test techniques. *****

Code: R7411001

2
(Common to Electronics & Instrumentation Engg, Electronics Computer Engg)

IV B.Tech I Semester (R07) Regular & Supplementary Examinations, Nov/Dec 2011 VLSI DESIGN Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 List out different lithography techniques in VLSI and explain clearly about photolithography. Explain various pull ups in the CMos design. Derive the relationship between Ids and Vds when the transistor is operated in Non saturated region. Explain about the CMos design rules for wires in circuit design process/ Explain the scaling of Mos circuits and also give the list of limitations of scaling. Explain about the following Sheet Resistance. Area capacitance. Fan in and Fan out. Design the logic for an ALU that can perform addition, subtraction, AND, OR, NOT. Give the major differences between CPLDs and FPGAs. Explain about standard cells in the semi conductor integrated circuit design. Explain the design verification tools in VHDL synthesis. Explain about circuit synthesis. What is the need testing and explain design strategies for test. Explain the layout design for improved testability. ***** Max Marks: 80

2 (a) (b)

3 (a) (b) 4 (a) (b) (c) 5 6 (a) (b) 7 (a) (b) 8 (a) (b)

Code: R7411001

3
(Common to Electronics & Instrumentation Engg, Electronics Computer Engg)

IV B.Tech I Semester (R07) Regular & Supplementary Examinations, Nov/Dec 2011 VLSI DESIGN Time: 3 hours Answer any FIVE questions All questions carry equal marks ***** 1 (a) (b) Explain clearly about NMOS fabrication process with neat sketches. Explain about oxidation and metallization process involved in the fabrication of integrated circuits. Derive the relationship between Ids and Vds when the transistor is operated in saturated region. Bring out the comparisons of CMOS & Bipolar transistors. Define stick diagram. What is stick diagram in VLSI Design? Give stick representations of different layers in Mos technology. Explain clearly about Cmos design rules. Explain about the following Sheet resistance. Wire capacitances. Fan in & Fan out. Give the different high density memory elements in subsystem design and also explain about SRAM cell in detail. Explain the programmable logic array with examples. Explain about design capture tolls in VHDL synthesis. Explain about design verification tools. What is the need of testing of an IC? What are the different testing techniques involved in CMOS testing? Explain about system level test techniques. ***** Max Marks: 80

2 (a) (b) 3 (a) (b) 4 (a) (b) (c) 5

6 7 (a) (b) 8 (a) (b)

Code: R7411001 IV B.Tech I Semester (R07) Regular & Supplementary Examinations, Nov/Dec 2011 VLSI DESIGN
(Common to Electronics & Instrumentation Engg, Electronics Computer Engg)

4
Max Marks: 80 Answer any FIVE questions All questions carry equal marks *****

Time: 3 hours

1 (a) (b) 2 (a) (b) 3 (a) (b) 4 (a) (b) 5 (a) (b) 6 (a) (b) 7 (a) (b) 8 (a) (b) (c)

What is the need of Encapsulation? Explain clearly different types of encapsulation in VLSI design. Explain about integrated resistors and capacitors. Explain the aspects of Mos transistor threshold voltage. Determine pull up to pull down ratio for an n Mos inverter by another n Mos inverter. Draw the VLSI design flow and explain each block in detail. Draw and explain the layout of NMos and CMos inverters. Explain about switch logic and alternate gate circuits. Explain about choice of layers. Explain clearly about subsystem principles. Explain about counters in subsystem design. Give the major differences between CPLDs and FPGAs. Explain about the programmable arrays logic(PALs) in detail. Explain the circuit design flow in VHDL synthesis. Explain about the design verification tools. Explain any two of the following Test principles. Chip level test techniques. System level test techniques. *****