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Behaviour and model of MOS transistors in weak inversion [1,2,3]. Examples of analog circuits. Exploratory analysis of weak inversion logic [4,5].
Weak inversion
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VG G ID VS S n+ n+ p local substrate
W,L Cox
gate capacitance per unit area VS B UT = kT/q ( = 26 mV at 300K) V = local non-equilibrium voltage in channel : channel voltage (quasi-Fermi potential of electrons) at source end of channel: V = VS at drain end of channel: V = VD local mobile inversion charge in channel (electrons) Qi VT0 gate threshold voltage for V=0.
CSEM, E. Vittoz, 2003
Weak inversion
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Given by:
ID 0 VS
VD
Weak inversion
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DRAIN CURRENT IN WEAK INVERSION (vertical axis magnified) -Qi /Cox VG-VT0>0 -Qi /Cox
0 VS VP>0 VD
-n slope
-n slope
ID/ V
ID/ 0 VS VD V
VP<0 VG-VT0<0
Weak inversion
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FORWARD AND REVERSE CURRENTS -Qi/Cox Drain current ID -Qi/Cox forward current IF -Qi/Cox reverse current IR
=
ID VS VD V
IF VS V
IR VD
Weak inversion
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thus:
VG-VT0 V V - S - D ID = IS e nUT (e UT - e UT ) IF IR
for IF and IR IS
Weak inversion
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ID = ID0
output
VG,VS = const. ID /IF
1
5% saturation VD-VS UT
0 1 2 3 4 5 6
1/n V G pe lo s U
T
VS UT
Weak inversion
page 8
IF,R 1+4 I S
-1
Only 3 parameters: VT0, n (inside VP) and IS (or ) to model the current
from weak to strong inversion.
CSEM, E. Vittoz, 2003
Weak inversion
page 9
strong
with: VP =(VG-VT0)/n ID = IF - IR
10-2
10-4 -20
20
40
Weak inversion
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gm/ID decreases with increasing inversion coefficient IC. gm/ID is maximum in weak inversion.
CSEM, E. Vittoz, 2003
Weak inversion
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Large-signal DC model:
VG-VT0 ID = IS e nUT
VD VS ( e - UT - e - UT
+ translinear circuits and log domain filters + max. Ion/Ioff for given voltage swing intermodulation in RF front ends + max. intrinsic voltage gain + min. input noise density for given ID + max. bandwidth for given kT/C and ID + min. input offset voltage max. output noise current for given ID max. current mismatch : ID VT0 dominated by VT -mismatch: = ID nUT
+ min. gate voltage + min. gate capacitance + max. gm/ID : + gm(ID) linear
Weak inversion
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Scaling-down of process:
dimension scaling by factor k all voltages decreased by k, except U T: - analog circuits: VDSsat must be decreased by k, thus VDSsat 2 IC = 2U
T
decreased by k2
Weak inversion
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LOW-VOLTAGE CASCODE IN WEAK INVERSION VDSsat = 4 to 6UT per transistor I VDS2 T2 VD2 T3 I T4
[2]
T5 T1 V DS1 VR substrate
Weak inversion
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EXTRACTION OF UT AND CURRENT REFERENCE [1] V+ T6 source sink T5 VT1 T3 I1 R T4T3 I2 T2KT1 VR I2
slope K
mirror T1-T2
P(stable)
or T
3 -T 4
irr
Q (unstable)
I1
Weak inversion
page 15
T6
T3
V+ T4 I T2 I T7
T5
T1 V R V-
T9 T8
Reference current I proportional to specific current IS8 Useful to bias transistors at inversion coef.IC independently of process. 2 If mobility ~ T -2, then compensation by UT : I ~ IS independent of T
CSEM, E. Vittoz, 2003
Weak inversion
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In weak inversion:
linearity of currents even for different gate voltages with VGi Gi = 1/Ri ~ ISi exp nUT
Weak inversion
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simple example of pseudo-R network in weak inversion: CALCULATION OF HARMONIC MEAN ground 0 GN IN GN Gk Ik I1 G1 Gk G1 GN* I G Gk* IN 0* Ik 0* G1* I1 0* 0* I GN* Gk*
[14,13]
G1* VVresistive prototype pseudo-resistive version (0*=pseudo-ground) 1 Series combination of Gi : G = harmonic mean 1/Gi 1 = Ihm Same voltage across G and Gi, thus I = 1/Ii N Can be used as a fuzzy AND gate.
CSEM, E. Vittoz, 2003
Weak inversion
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TRANSLINEAR CIRCUITS With bipolar transistors: With MOS transistors in weak inversion:
Ii
[16,17]
[15]
+ +
VGi Ii -1 Ii VSi
VBEi
+ +
common substrate
+ Ii with: VBEi= UT ln I
VBEi
VBEi
si
Ii Ii
+ =
Isi Isi
+
Weak inversion
page 19
[5]
exponential in VGS, with maximum gm/ID, thus: - minimum swing V for given Ion/off, hence - minimum Pdyn for given Ioff V +(n-1)VS - T0 - with: I0 = IS e nU
T
adjustable by VS.
Assumptions on process:
1. Threshold VT0 close to 0 (VS cannot be too negative). 2. Triple well (true twin well): separate local p and n substrates - adjustment of I0 by VS for n- and p-channel.
CSEM, E. Vittoz, 2003
Weak inversion
page 20
V+ inverter Ip Vi In C Vo VVB
st
n=1.6
swing
vB
e abl t tas me
ab le
vH (high)
bistable for VB > 1.91UT stable vL (low) 95% swing for VB = 4UT
6 8
Weak inversion
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Since VL=VB-VH >0, static current Istat at each state is larger than I0
1.2 Istat
I0
n = 1.6
Weak inversion
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STANDARD TRANSITIONS IN HOMOGENEOUS SYSTEM 2Td Chain of inverters Vo2 VH Vo8 Vo6 Vo4
VL
4 von=vin+1 2 1 0 0 3 vo1 vo3 vo5 vo4 vo6 vo7 2Td/T0 vo2 vo8
vH
n = 1.6 vB = 4
Characteristic time : T0=CUT/I0 Transitions become standard after a few stages Normalized delay time Td/T0 only depends on VB and n.
CSEM, E. Vittoz, 2003
vL
Weak inversion
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Approximation:
CVB CVB Td Ion I0eVB/nUT or 5 6 8 4 7 9 10 normalized supply voltage vB 11 CVB -V /nU e B T Td (for calcul. of Pstat) I0
0.01 3
Weak inversion
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10-2 Qsc QC 0 3
n = 1.6
10
Weak inversion
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POWER-DELAY PRODUCT
PTd 2 CUT
10 8 6 4 2 0 2
=1
0.5
0.2
n =1.6
Pdyn dominates for large min. VB for min. PTd Pstat dominates for small increase VB to increase Ion/Ioff
CSEM, E. Vittoz, 2003
Weak inversion
page 26
POWER/FREQUENCY RATIO
By re-using =2f Td :
P/f 1000 C(nUT)2
normalized total power
-v /n e B ) 2
Pdyn for VB=25nUT 1V 10-2 10-3 10-4 parameter Pstat Pdyn e-3 10-2 10-4 10-3
100 e-3 10 1 1 1 2
6 8 4 14 10 12 normalized supply/slope factor vB/n VBopt and Pmin increase for decreasing At Pmin : PdynPstat Increasing I0 does not allow to reduce VB significantly for Td const. For > 5%, power reduction by >20 compared to Pdyn at 1V.
CSEM, E. Vittoz, 2003
Weak inversion
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MAXIMUM SPEED
Since Td
CVB Ion
and Ionmax ICon IS (inv. coeff* spec. current), thus: Tdmin VB C ICon IS process
Tdmin(weak) VB C IS
Weak inversion
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EFFECT OF ENTERING MODERATE AND STRONG INVERSION (using continuous model of ID) VGS nUT
60
105
40
VGS swing
103
20
param. Ion/Ioff
10
4 3 2 1 0 0 1
vH logic swing vL 2 3
vB=4 n=1.6
Istat IS ICon 4
Weak inversion
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NUMERICAL RESULTS
C VB
process A process B unit 500 200 20 28 228 1.46 20 50 0.22 32.5 180 400 4 4.2 44 0.22 4 500 2.56 56.3 nm nA fF aJ aJ fJ fJ MHz MHz nW
Weak inversion
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Short channel effects: should not drastically degrade the results. Gate leakage current : should be alleviated by very low VB. Adjustment of I0 orTd to required value
control by VS with charge pump in loop [18]; n>1 needed (no SOI!) corresponds to threshold adjustment unavoidable at very low VB.
Weak inversion
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Weak inversion
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CONCLUSION
Low speed, but keeps increasing with 1/L2 in scaled down processes.
CSEM, E. Vittoz, 2003
Weak inversion
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REFERENCES
[1] [2] E.Vittoz and J.Fellrath, "CMOS analog integrated circuits based on weak inversion operation", IEEE J.Solid-State Circuits, vol.SC-12, pp.224-231, June 1977. E.Vittoz, "Micropower techniques", in Design of VLSI Circuits for Telecommunications and Signal Processing, J.E.Franca and Y.P.Tsividis Editors, Prentice Hall, 1991
[3]. C.Enz, F.Krummenacher and E.Vittoz, "An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications", Analog Integrated Circuits and Signal Processing, Vol.8, pp.83-114, 1995. [4] [5] [6] [7] [8] [9] R.M Swanson and J.D.Meindl,"Ion-implanted complementary MOS transistors in low-voltage circuits", IEEE J.Solid-State Circuits, vol.SC-7, pp.146-153, April 1972. E. Vittoz, "Weak inversion for ultimate low-power logic", to be published in Low-Power Electronic Design, ed. C. Piguet, CRC Press LLC (2003?), Chapter 16. E. Vittoz, C. Enz and F. Krummenacher, "A basic property pf MOS transistors and its circuit implications", Workshop on Compact Modeling, WCM MSM.2003, Febr. 23-27, San F.rancisco, pp. 246-249. Slide of presentation can be downloaded at www.nanotech2003.com/WCM2003.html#Slides. M.A. Maher and C. Mead, "A physical charge-controlled model for the MOS transistors", Advanced research in VLSI, Proc. of the 1987 Stanford Conference, MIT Press, Cambridge MA, 1987. A. Cunha et al., "An MOS transistor model for analog circuit design", IEEE J.Solid-State Circuits, vol.33, pp.1510-1519, Oct. 1998. H. Oguey and S. Cserveny, "MOS modelling at low current density", Summer Course on "Process and Device Modelling", ESAT Leuven-Heverlee, Belgium, June 1983.
[10] H.J.Oguey and D.Aebischer. "CMOS current without resistance."IEEE Journal of Solid-State Circuits, vol 32, pp.1132-1135 July 1997. [11] K.Bult and G.Geelen, "A inherently linear and compact MOST-only current division technique", Dig. ISSCC Tech. Papers, February 1992, pp.198-199. [12] E.Vittoz and X.Arreguit,"Linear networks based on transistors", Electronics Letters, vol.29, pp.297-299, 4th Febr. 1993. [13] E.Vittoz, Pseudo-resistive networks and their applications to analog collective computation, Proc. MicroNeuro97, Dresden , pp.163-173. [14] T. Delbrck, "Bump circuit for computing similarity and dissimilarity of analog voltages", Proc. of International Joint Co on Neural Networks, vol.1, pp. I nf. 475-479. 1991. [15] B. Gilbert, "Translinear circuits: a proposed classification", Electron. Letters, vol.11, p.14, 1975. [16] A. Andreou and K. Boahen, "Neural information processing II" in Analog VLSI Signal and Information Processing, M. Ismail and T. Fiez, editors, pp.358-409, McGraw-Hill, 1994. [17] E.Vittoz, "Analog VLSI implementation of neural networks", published in the Handbook of Neural Computation, Institute of Physics Publishing and Oxford University Press, USA, 1996. [18] V. von Kaenel et al. "Automatic adjustment of threshold and supply voltage for minimum power consumption in CMOS digital circuits'', Proc. IEEE Symposium on Low Power Electronics, San Diego, 1994, pp.78-79. CSEM, E. Vittoz, 2003