 Adder 8 bit test bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

ENTITY adder8bit_adder_test_vhd_tb IS
END adder8bit_adder_test_vhd_tb;

ARCHITECTURE behavior OF adder8bit_adder_test_vhd_tb IS

COMPONENT adder8bit
PORT(
a : IN std_logic_vector(7 downto 0);
b : IN std_logic_vector(7 downto 0);
cin : IN std_logic;
sum : OUT std_logic_vector(7 downto 0);
cout : OUT std_logic
);
END COMPONENT;

SIGNAL a : std_logic_vector(7 downto 0):="00000000";

SIGNAL b : std_logic_vector(7 downto 0):="00000000";
SIGNAL cin : std_logic:='0';
SIGNAL sum : std_logic_vector(7 downto 0);
SIGNAL cout : std_logic;
signal my_out: std_logic_vector(8 downto 0):="000000000";
BEGIN

uut: adder8bit PORT MAP(

a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);

-- *** Test Bench - User Defined Section ***

tb : PROCESS
BEGIN
for k in 1 to 2 loop
 for i in 1 to 10 loop
for j in 1 to 10 loop

my_out<= '0'& a+b+cin;

wait for 1 ps;

assert my_out = not (cout&sum)
severity NOTE;
report"Adder working properly";

a<=a+1;
end loop;
b<=b+1;
end loop;

cin<='1';
end loop;

assert now <= 150 ps

severity FAILURE;

END PROCESS;
END;

Simulation result:-

# ** Note: Assertion violation.

# Time: 1 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 1 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 2 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 2 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 3 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 3 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 4 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 4 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 5 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 5 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 6 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 6 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 7 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 7 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 8 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 8 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 9 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 9 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.
# Time: 10 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Adder working properly
# Time: 10 ps Iteration: 0 Instance: /adder8bit_adder_test_vhd_tb
# ** Note: Assertion violation.

Continue for the other combination.