Scaling of MOS circuits

Scaling of MOS circuits

by SURESHA V
Professor,Dept. of E&C Visvesvaraya Technological University(VTU) BelgaumBelgaum-590 014.karnataka State. INDIA e-mail: suresha.vee@gmail.com

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Objectives:
To know what is Scaling To know why scaling is required Figure(s) of Merit (FoM) for scaling Scaling models Scaling factors for device parameters Implications of scaling on design Limitations of scaling

Learning outcomes:
At the end of this module the students will be able understand what is scaling. Understand how to improve the performance of simple MOS circuits by scaling. Writing scaling Model for simple MOS device Understand the effect and limitation of scaling.
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Introduction:
What is Scaling?
Proportional adjustment of the dimensions of an electronic device while maintaining the electrical properties of the device, results in a device either larger or smaller than the un-scaled device. Then Which way do we scale the devices for VLSI? BIG and SLOW or SMALL and FAST? What do we gain?

Why Scaling?...
Scale the devices and wires down, Make the chips fatter functionality, intelligence, memory and faster, Make more chips per wafer increased yield, Make the end user Happy by giving more for less and therefore, make MORE MONEY!!
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd FoM for Scaling

Impact of scaling is characterized in terms of several indicators: o Minimum feature size o Number of gates on one chip o Power dissipation o Maximum operational frequency o Die size o Production cost Many of the FoMs can be improved by shrinking the dimensions of and interconnections. Shrinking the separation between features transistors and wires Adjusting doping levels and supply voltages.
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transistors

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd Technology Scaling

Goals of scaling the dimensions by 30%: Reduce gate delay by 30% (increase operating frequency by 43%) Double transistor density Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency) Die size used to increase by 14% per generation Technology generation spans 2-3 years

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure1: Illustrates the technology scaling in terms of minimum feature size.

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure2 : illustrates the technology scaling in terms of transistor count.

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure3: illustrates the technology scaling in terms of propagation delay

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure4: illustrates the technology scaling in terms of power dissipation and density

Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Scaling Models
Most commonly used Models are:
Full Scaling (Constant Electrical Field): Ideal model dimensions and voltage scale together by the same scale factor Fixed Voltage Scaling: Most common model until recently only the dimensions scale, voltages remain constant General Scaling: Most realistic for todays situation voltages and dimensions scale with different factors

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Scaling Factors for Device Parameters

In our discussions we will consider two scaling factors, and 1/ is the scaling factor for VDD and oxide thickness D 1/ is scaling factor for all other linear dimensions We will assume electric field is kept constant

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
It is important that you understand how the following parameters are effected by scaling
Gate Area Gate Capacitance per unit area Gate Capacitance Charge in Channel Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipation Per Unit Area Power - Speed Product
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Example: Sacling of MOS tansistor

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Scaling Factors for Device Parameters 1. Gate area A g :

Where L: Channel length and W: Channel width and both are scaled by 1/ Thus Ag is scaled up by 1/2

2. Gate capacitance per unit area Co or Cox

Where ox is permittivity of gate oxide(thin-ox)= ins o and D is the gate oxide thickness scaled by 1/ Thus Cox is scaled up by
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd 3. Gate capacitance Cg :

Thus Cg is scaled up by * 1/2 = /2

4. Parasitic capacitance Cx
Cx is proportional to Ax / d where d is the depletion width around source or drain and scaled by 1/ Ax is the area of the depletion region around source or drain, scaled by (1/2 ). Thus Cx is scaled up by

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd 5.Carrier density in channel Qon

where Qon is the average charge per unit area in the on state. Co is scaled by and Vgs is scaled by 1/ Thus Qon is scaled by 1

6.Channel Resistance Ron

Where = channel carrier mobility and assumed constant Thus Ron is scaled by (1/ * * 1) = 1
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd 7. Gate delay Td Td is proportional to Ron* Cg Thus Td is scaled by 8. Maximum operating frequency fo

fo is inversely proportional to delay Td and is scaled by

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd 9.Saturation current Idss

Both Vgs and Vt are scaled by (1/). Therefore, Idss is scaled by

10. Current density J: J= Idss/A

where A is cross sectional area of the Channel in the on state which is scaled by (1/ 2) So, J is scaled by
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd 11.Switching energy per gate Eg

So Eg is scaled by

12. Power dissipation per gate Pg

Pg comprises of two components: static component Pgs and dynamic component Pgd: Where, the static power component Pgs is given by: Dynamic component Pgd is given by: Since VDD scales by (1/ ) and Ron scales by 1, Pgs scales by (1/ 2). Since Eg scales by (1/ 2 ) and fo by (2 / ), Pgd also scales by (1/ 2). Therefore, Pg scales by (1/ 2).
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
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Scaling of MOS circuits

Contd
13. Power dissipation per unit area Pa

14. Power speed product PT

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Summary of scaling effects

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Physical Limits
Will Moores Law run out of steam? Cant build transistors smaller than an atom Many reasons have been predicted for end of scaling Dynamic power Sub-threshold leakage, tunneling Short channel effects Fabrication costs Electro-migration Interconnect delay
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
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Scaling of MOS circuits

Limitations of Scaling
Effects, as a result of scaling down- which eventually become severe enough to prevent further miniaturization.
o

Substrate doping

o Depletion width o Limits of miniaturization o Limits of interconnect and contact resistance o Limits due to sub threshold currents o Limits on logic levels and supply voltage due to noise o Limits due to current density
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
1. Substrate doping
Built-in(junction) potential VB depends on substrate doping level can be neglected as long as VB is small compared to VDD. As length of a MOS transistor is reduced, the depletion region width scaled down to prevent source and drain depletion region from meeting. The depletion region width d for the junctions is given by

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Vb built in potential and it given by

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
2. Depletion width NB is increased to reduce d, but this increases threshold voltage Vt - against trends for scaling down. Maximum value of NB(1.3*1019 cm-3) , at higher values, maximum electric field applied to gate is insufficient and no channel is formed. NB maintained at satisfactory level in the channel region to reduce the above problem. Emax maximum electric field induced in the junction and it is given by

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
If NB is increased by and if Va = 0 then Vb increased by ln and d is decreased by Therefore Electric field across the depletion region is increased by Reach a critical level Ecrit with increasing NB Fig:5.2a shows the depletion width d as a function of NB and Vdd .The dashed line indicates the maximum depletion width for Emax= Ecrit ,then d we have

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure 5.1a: shows the relation between substrate concentration Vs depletion width ,

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure 5.1b: shows the relation between depletion width d and Electric field Vs, substrate doping NB

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure 5.1c: Demonstrates the interconnect length Vs. propagation delay

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure 5.1d : Demonstrates the oxide thickness Vs. thermal noise.

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
3. Limits of miniaturization Minimum size of transistor; process tech and physics of the device Reduction of geometry; alignment accuracy and resolution Size of transistor measured in terms of channel length L L = 2d (to prevent push through) L determined by NB and Vdd Minimum transit time for an electron to travel from source to drain is

then the transit time t is given by

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Maximum carrier drift velocity is approx. equals to Vsat ,regardless of supply voltage. Therefore minimum transit time maybe assumed to occur for a minimum size transistor when Va is approx. 0 V

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Fig 5.3 b : Relation for channel length L vs transit time t

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
4 . Limits of interconnect and contact resistance Short distance interconnect- conductor length is scaled by 1/ and resistance is increased by For constant field scaling, I is scaled by 1/ so that IR drop remains constant as a result of scaling.- driving capability/noise margin. Following graphs 5.6a and 5.6b shows the effect of interconnect and resistance

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure5.6a : Demonstrates the length of interconnect L (mm) Vs propagation delay(sec).

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure5.6 b : Demonstrates the length of interconnect L (mm) Vs propagation delay(sec).

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
5. Limits due to subthreshold currents
Major concern in scaling devices. I sub is directly proportional exp (Vgs Vt ) q / KT As voltages are scaled down, ratio of Vgs Vt to KT will reduce-so that threshold current increases. Therefore scaling Vgs and Vt together with Vdd . Maximum electric field across a depletion region is

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
6. Limits on supply voltage due to noise Decreased inter-feature spacing and greater switching speed result in noise problems Fig5.7a : Relation for Thermal noise v/s oxide thickness

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Fig5.7b : Relation for Thermal noise v/s substrate concentration

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
Figure 5.8 : relation for probability of total error v/s supply voltage Vdd

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Contd
7. Limits due to current density:
Aluminum most commonly used material for forming interconnection in VLSI chips. However scalingdown dimension increase the current density in interconnections by the same factor. When the current density in Aluminum approaches 106 Amps/cm2 , the interconnect are likely to be burned off owing to metal migration. The allowable current density in Aluminum are set below the limit of J= 1 to 2 mA /m2

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

CONCLUSION
Observation - Device scaling
Gate capacitance per micron is nearly independent of process But ON resistance * micron improves with process Gates get faster with scaling (good) Dynamic power goes down with scaling (good) Current density goes up with scaling (bad) Velocity saturation makes lateral scaling unsustainable

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

CONCLUSION
Observations Interconnect scaling Capacitance per micron is remaining constant
About 0.2 fF/mm Roughly 1/10 of gate capacitance

Local wires are getting faster

Not quite tracking transistor improvement But not a major problem

Global wires are getting slower

No longer possible to cross chip in one cycle
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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

SUMMARY Scaling allows people to build more complex machines

That run faster too

It does not to first order change the difficulty of module design

Module wires will get worse, but only slowly You dont think to rethink your wires in your adder, memory Or even your super-scalar processor core

It does let you design more modules Continued scaling of uniprocessor performance is getting hard
Machines using global resources run into wire limitations Machines will have to become more explicitly parallel
Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327
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Scaling of MOS circuits

Reference
Basic VLSI design by Douglas A. Pucknel and Kamran Eshraghian, 3rd edition PHI publication, India, year 2001(Page 123-144)

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

THE END

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Any Question ?

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327

Scaling of MOS circuits

Any correction or suggestion please feedback to: e-mail : suresha.vee@gmail.com Mobile : +91 - 94485 24399

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Suresha V. Professor, Dept. of E&C, KVG College Of Engineering. Sullia, D.K - 574 327