EEE469B ASSIGNMENT # 1 14 Jan 09 Due in class 28 Jan 09 Answer the following questions: 1) Review Question 2.

5
Similar or identical instruction set: In many cases, the same set of machine instructions is supported on all members of the family. Thus, a program that executes on one machine will also execute on any other. Similar or identical operating system: The same basic operating system is available for all family members. Increasing speed: The rate of instruction execution increases in going from lower to higher family members. Increasing Number of I/O ports: In going from lower to higher family members. Increasing memory size: In going from lower to higher family members. Increasing cost: In going from lower to higher family members.

2)

The ENIAC was a decimal machine, where a register was represented by a ring of 10 vacuum tubes. At any time, only one vacuum tube was in the ON state, representing one of ten digits. Assuming that the ENIAC had the capability to have multiple vacuum tubes ON and OFF simultaneously, why is this representation wasteful and what range of integer values could we represent using the 10 vacuum tubes?
This representation was wasteful because if multiple tubes could be on or off simultaneously within each group of 10 vacuum tubes, then there are two ways to make better use of this fact. First, and probably most obvious to us these days, would be to use the 10 tubes as a binary value, giving a range of 1024 numbers, either signed or unsigned. Second, and less obvious, would be to use four tubes instead of 10 to represent the digits from 0-9 in binary format, like packed decimal. Keep in mind that back in the old days, computers were a novelty and humans think in decimal. This possibility is also less wasteful.

3)

Different machine instructions may require a different number of clock cycles to execute. An important parameter is therefore the average cycles per instruction (CPI) for a program. A common measure of performance for a processor is the rate at which instructions are executed, expressed as millions of instructions per second (MIPS). Express MIPS in terms of the clock rate and CPI.
MIPS = Clock Rate / (CPI * 106)

4)

A benchmark program is run on a processor running at 2 GHz. The program contains 100,000 instructions, with the following instruction mix and clock cycle count: Instruction Count 45000 32000 15000 8000 Clock Cycle Count 1 2 2 2

Instruction Type Integer arithmetic Data transfer Floating Point Control transfer

Determine the effective CPI, MIPS rate, and execution time for this program.
Effective CPI = (45000 + 64000 + 30000 + 16000) / 100000 Effective CPI = 155000 / 100000 = 1.55 Effective MIPS = 2 * 109/ (1.55 * 106) Effective MIPS = 1290.3 Execution Time = (1.55 * 100000) /(2 * 109) Execution Time = 77.5 us

5)
a. b.

Problem 3.3
224 = 16 MBytes (1) If the local address bus is 32 bits, the whole address can be transferred at once and decoded in memory. However, since the data bus is only 16 bits, it will require 2 cycles to fetch a 32-bit instruction or operand. (2) The 16 bits of the address placed on the address bus can't access the whole memory. Thus a more complex memory interface control is needed to latch the first part of the address and then the second part (since the microprocessor will end in two steps). For a 32-bit address, one may assume the first half will decode to access a "row" in memory, while the second half is sent later to access a "column" in memory. In addition to the two-step address operation, the microprocessor will need 2 cycles to fetch the 32 bit instruction/operand. The program counter must be at least 24 bits. Typically, a 32-bit microprocessor will have a 32-bit external address bus and a 32-bit program counter, unless on-chip segment registers are used that may work with a smaller program counter. If the instruction register is to contain the whole instruction, it will have to be 32-bits long; if it will contain only the op code (called the op code register) then it will have to be 8 bits long.

c.

6)

Problem 3.12
a. The clock period is 125 ns. Therefore, two clock cycles need to be inserted. b. From Figure 3.19, the Read signal begins to rise early in T2. To insert two clock cycles, the Ready line can be put in low at the beginning of T2 and kept low for 250 ns.

7)

Produce a table comparing USB 2.0 and PCI Express in terms of data transfer rate, communication type

(serial/parallel; synchronous/asynchronous), power available to devices, and whether or not it is hot pluggable. Refs: http://www.usb.org/developers/docs/; http://www.pcisig.com/specifications/. Devices Data Transfer Rate Communication Power (for devices) Hot Pluggable Data Flow 8) Problem 9.5
The twos complement of the original number.

USB 2.0 External 480 Mbps = 60 MBps Serial Asynchronous / Isochronous Max 2.5 W per device Yes Bi-Directional

PCI-Express Internal 250 MBps Serial Synchronous 75 W per slot Yes Bi-Directional

9) Problem 9.14
A 0000 0000 1011 1101 0010 0001 1100 1110 Q 1010 0101 0101 1010 1010 0101 0101 0010 Q1 0 0 0 1 1 0 0 1 M 0101 0101 0101 0101 0101 0101 0101 0101 Initial Shift A A M Shift A A + M Shift A A M Shift

10)
a.

Problem 9.38
The exponents are equal. Therefore the significands are added, keeping the common exponent, and the sum is renormalized if necessary. 3 3 3 4 0.5566 10 + 0.7777 10 = 1.3343 10 0.1344 10 The exponents must be equalized first. 0.3344 102 + 0.8877 10-1 = 0.3344 102 + 0.0008877 102 = 0.3352877 102 0.3352 102

b.

11)

What (in your opinion) will be the next major architectural change to the computer? Will this change be driven by an organizational change? Why or why not?

(Note: This question is designed to make you think. I expect 3 completely different answers for this one, and no one can use the photonic quantum computer either that one is mine!)