82527

ARCHITECTURAL
OVERVIEW
Januaiy 1996
82527
Serial Communications
Controller
Architectural Overview
Automotive
COPYRIGHT INTEL CORPORATION 1995
Order Number 272410-003
1
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoev-
er including infringement of any patent or copyright for sale and use of Intel products except as provided in
Intels Terms and Conditions of Sale for such products
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Products may have minor variations to this specification known as errata
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Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your
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literature may be obtained from
Intel Corporation
PO Box 7641
Mt Prospect IL 60056-7641
or call 1-800-879-4683
COPYRIGHT INTEL CORPORATION 1995
2
82527 Serial Communications Controller
CONTENTS PAGE
10 GENERAL FEATURES 1
11 Functional Overview 2
12 CAN Controller 3
13 RAM 3
14 CPU Interface Logic 3
15 Clockout 3
16 Two 8-Bit Ports 3
20 PACKAGE DIAGRAMPIN OUT 4
30 PIN DESCRIPTION 5
31 Hardware Reset 8
32 Software Initialization 8
40 FUNCTIONAL DESCRIPTION 8
41 82527 Address Map 9
42 Control Register (00H) 9
43 Status Register (01H) 10
44 CPU Interface Register (02H) 12
45 Clocking Description 13
46 High Speed Read Register
(0405H) 13
47 Global Mask - Standard Register
(0607H) 14
48 Global Mask - Extended Register
(080BH) 14
49 Acceptance Filtering
Implications 15
410 Message 15 Mask Register
(0C0FH) 15
411 CLKOUT Register (1FH) 15
412 Bus Configuration Register
(2FH) 16
413 Bit Timing Overview 16
414 Bit Timing Registers
(3FH 4FH) 18
415 Comparison of 82526 and 82527
Bit Timing Calculations 19
416 Interrupt Register (5FH) 19
417 Serial Reset Address (FFH) 20
418 82527 Message Objects 20
419 Control 0 and Control 1
Registers 21
420 Arbitration 0 1 2 3 Registers 23
CONTENTS PAGE
421 Message Configuration
Register 24
422 Data Bytes 24
423 Special Treatment of Message
Object 15 24
50 PORT REGISTERS 25
60 SERIAL RESET ADDRESS (FFH) 26
70 FLOW DIAGRAMS 26
71 82527 Handling of Message
Objects 1-14 (Direction
e
Transmit) 27
72 82527 Handling of Message
Objects 1-14 (Direction
e
Receive) 28
73 CPU Handling of Message Object
15 (Direction
e
Receive) 29
74 CPU Handling of Message Objects
114 (Direction
e
Transmit) 30
75 CPU Handling of Message Objects
114 (Direction
e
Receive) 31
80 CPU Interface Logic 32
81 Serial Control Byte 34
90 82527 FRAME TYPES 35
91 Data Frame 35
92 Remote Frame 36
93 Error Frame 36
94 Overload Frame 37
95 CodingDecoding 38
96 Arbitration 38
100 ERROR DETECTION AND
CONFINEMENT 39
101 Bit Error 39
102 Bit Stuffing Error 39
103 CRC Error 39
104 Form Error 39
105 Error Detection Capabilities 40
106 Error Confinement 40
107 82527 States With Respect to the
Serial Bus 40
110 SAMPLE PROGRAM 41
3
4
82527
10 GENERAL FEATURES
Suppoits CAN Specification 2.0
- Standaid Data and Remote Fiames
- Fxtended Data and Remote Fiames
PiogiammabIe OIobaI Mask
- Standaid Message Identifiei
- Fxtended Message Identifiei
15 Message Objects of 8-byte Data Length
- 14 TX/RX Buffeis
- 1 RX Buffei with PiogiammabIe Mask
FIexibIe CPU Inteiface
- 8-bit MuItipIexed
- 16-bit MuItipIexed
- 8-bit Synchionous Non-MuItipIexed
- 8-bit Asynchionous Non-MuItipIexed
- SeiiaI Inteiface
PiogiammabIe Bit Rate
PiogiammabIe CIock Output
FIexibIe Inteiiupt Stiuctuie
FIexibIe Status Inteiface
ConfiguiabIe Input Compaiatoi
Two 8-bit BidiiectionaI I/O Poits
44-Iead PLCC Package/44-Lead QFP Package
Pinout CompatibiIity with the 82526
The 82527 seiiaI communications contioIIei is a highIy
integiated device that peifoims seiiaI communication
accoiding to the CAN piotocoI. The CAN piotocoI
uses a muIti-mastei (contention based) bus configuia-
tion foi the tiansfei of communication objects be-
tween nodes of the netwoik. This muIti-mastei bus is
aIso iefeiied to as CSMA/CR oi Caiiiei Sense, MuIti-
pIe Access, with CoIIision ResoIution. The 82527 pei-
foims aII seiiaI communication functions such as tians-
mission and ieception of messages, message fiIteiing,
tiansmit seaich, and inteiiupt seaich with minimaI in-
teiaction fiom the host miciocontioIIei, oi CPU.
The 82527 is InteIs fiist device to suppoit the standaid
and extended message fiames in CAN Specification 2.0
pait B. It has the capabiIity to tiansmit, ieceive, and
peifoim message fiIteiing on extended message fiames
with a 29-bit message identifiei. Due to the backwaidIy
compatibIe natuie of CAN Specification 2.0, the 82527
aIso fuIIy suppoits the standaid message fiames in
CAN Specification 2.0 pait A.
A communication object consists of an identifiei aIong
with contioI data segments. The contioI segment con-
tains aII the infoimation needed to tiansfei the message.
The data segment contains fiom 0 to 8 bytes in a singIe
message. AII communication objects aie stoied in the
RAM of the coiiesponding CAN chip foi each node. A
tiansmitting node bioadcasts its message to aII othei
nodes on the netwoik. An acceptance fiItei at each
node decides whethei to ieceive that message. A mes-
sage is accepted onIy if a communication object with
the same message identifiei has been set up in the CAN
RAM foi that node.
CAN not onIy manages the tiansmission and ieception
of messages but aIso the eiioi handIing, without any
buiden on the CPU.
CAN featuies seveiaI eiioi detection mechanisms.
These incIude CycIicaI Redundancy Check (CRC) and
bit coding iuIes (bit stuffing/destuffing). The poIyno-
miaI of the CRC has been optimized foi contioI appIi-
cations with shoit messages. If a message was coiiupt-
ed by noise duiing tiansmission, it is not accepted at
the ieceiving nodes. Cuiient tiansmission status is
monitoied in the contioI segment of the appiopiiate
communication object within the tiansmitting node,
automaticaIIy initiating a iepeated tiansmission in the
case of eiiois. CAN aIso has buiIt-in mechanisms to
Iocate eiioi souices and to distinguish peimanent haid-
waie faiIuies fiom occasionaI soft eiiois. Defective
nodes aie switched off the bus, impIementing a faiI-safe
behavioi (thus, haidwaie eiiois wiII not Iet defective
nodes contioI the bus indefiniteIy).
The message stoiage is impIemented in an inteIIigent
memoiy, oi RAM, which can be addiessed by the
CAN contioIIei and the CPU. The CPU contioIs the
CAN contioIIei by seIectiveIy modifying the vaiious
iegisteis and bit fieIds in the RAM. The content of the
vaiious bit fieIds aie used to peifoim the functions of
acceptance fiIteiing, tiansmit seaich, inteiiupt seaich
and tiansfei compIetion.
In oidei to initiate a tiansfei, the tiansmission iequest
bit has to be wiitten to the message object. The entiie
tiansmission pioceduie and eventuaI eiioi handIing is
then done without any CPU invoIvement. If a commu-
nication object has been configuied to ieceive messages,
the CPU easiIy ieads its data iegisteis using CPU iead
instiuctions. The message object may be configuied to
inteiiupt the CPU aftei eveiy successfuI message tians-
mission oi ieception.
The 82527 featuies a poweifuI CPU inteiface that of-
feis fIexibiIity to diiectIy inteiface to many diffeient
CPUs. It can be configuied to inteiface with CPUs us-
ing an 8-bit muItipIexed, 16-bit muItipIexed, oi 8-bit
non-muItipIexed addiess/data bus foi InteI and non-
InteI aichitectuies. A fIexibIe seiiaI inteiface is aIso
avaiIabIe when a paiaIIeI CPU inteiface is not iequiied.
The 82527 piovides stoiage foi 15 message objects of
8-byte data Iength. Fach message object can be config-
uied as eithei tiansmit oi ieceive except foi the Iast
1
5
82527
message object. The Iast message object is a ieceive onIy
buffei with a speciaI acceptance mask designed to aIIow
seIect gioups of diffeient message identifieis to be ie-
ceived.
The 82527 aIso impIements a gIobaI acceptance mask-
ing featuie foi message fiIteiing. This featuie aIIows the
usei to gIobaIIy mask any identifiei bits of the incoming
message. The piogiammabIe gIobaI mask can be used
foi both standaid and extended messages.
The 82527 piovides an impioved set of netwoik man-
agement and diagnostic functions incIuding fauIt con-
finement and a buiIt-in deveIopment tooI. The buiIt-in
deveIopment tooI aIeits the CPU when a gIobaI status
change occuis. OIobaI status changes incIude message
tiansmission and ieception, eiioi fiames, oi sIeep mode
wake-up. In addition, each message object offeis fuII
fIexibiIity in detecting when a data oi iemote fiame has
been sent oi ieceived.
The 82527 offeis haidwaie, oi pinout, compatibiIity
with the 82526. It is pin-to-pin compatibIe with the
82526 except foi pins 9, 30, and 44. These pins aie used
as chip seIects on the 82526 and aie used as CPU intei-
face mode seIection pins on the 82527.
The 82527 is fabiicated in InteIs ieIiabIe CHMOS III
5-V technoIogy and is avaiIabIe in a 44-Iead PLCC and
44-Iead QFP foi the automotive tempeiatuie iange
(
b
40C to
a
125C ambient).
11 Functional Overview
The 82527 CAN contioIIei consists of six functionaI
bIocks. The CPU Inteiface Iogic manages the inteiface
between the CPU (host miciocontioIIei) and the 82527
using an addiess/data bus. The CAN contioIIei intei-
faces to the CAN bus and impIements the piotocoI
iuIes of the CAN piotocoI foi the tiansmission and
ieception of messages. The RAM is the inteiface Iayei
between the CPU and the CAN bus. The two poit
bIocks piovide 8-bit Iow speed I/O capabiIity. The
cIockout bIock aIIows the 82527 to diive othei chips,
such as the host-CPU.
The 82527 RAM piovides stoiage foi 15 message ob-
jects of 8-byte data Iength. Fach message object has a
unique identifiei and can be configuied to eithei tians-
mit oi ieceive except foi the Iast message object. The
Iast message object is a ieceive onIy buffei with a spe-
ciaI mask design to aIIow seIect gioups of diffeient mes-
sage identifieis to be ieceived.
Fach message object contains contioI and status bits. A
message object with the diiection set as ieceive wiII
send a iemote fiame by iequesting a message tiansmis-
sion. A message object with the diiection set as tians-
mit wiII be configuied to automaticaIIy send a data
fiame whenevei a iemote fiame with a matching identi-
fiei is ieceived ovei the CAN bus. AII message objects
have sepaiate tiansmit and ieceive inteiiupts and status
bits, aIIowing the CPU fuII fIexibiIity in detecting when
a iemote oi data fiame has been sent oi ieceived.
The 82527 aIso impIements a gIobaI masking featuie foi
acceptance fiIteiing. This featuie aIIows the usei to
gIobaIIy mask, oi dont caie, any identifiei bits of the
incoming message. This mask is piogiammabIe to aIIow
the usei to design an appIication-specific message iden-
tification stiategy. Theie aie sepaiate gIobaI masks foi
standaid and extended fiames.
The incoming message fiist passes thiough the gIobaI
mask and is matched to the identifieis in message ob-
jects 114. If theie is no identifiei match then the mes-
sage passes thiough the IocaI mask in message object
15. The IocaI mask aIIows a Iaige numbei of infiequent
messages to be ieceived by the 82527. Message object
15 is aIso buffeied to aIIow the CPU time to seivice a
message ieceived.
2
6
82527
A bIock diagiam of the 82527 is shown beIow.
2724101
12 CAN Controller
The CAN contioIIei contioIs the data stieam between
the RAM (paiaIIeI data) and the CAN busIine (seiiaI
data). The CAN contioIIei aIso manages the tiansceiv-
ei Iogic (RX0, RX1, TX0, TX1), the eiioi management
Iogic and the message objects.
13 RAM
The RAM is an inteiIeaved access memoiy. This means
the access to the RAM is timeshaied between the CPU
Inteiface Logic and the CAN bus (thiough the CAN
contioIIei). The RAM is addiessed fiom 00H to FFH.
14 CPU Interface Logic
The 82527 piovides a fIexibIe CPU inteiface capabIe of
inteifacing to many commonIy used miciocontioIIeis.
Five modes aie seIected using two CPU inteiface mode
pins. Mode 0 (Mode1 pin
e
0, Mode0 pin
e
0) seIects
an 8-bit InteI muItipIexed addiess data bus. If the RD
and WR pins aie tied Iow at ieset in Mode 0, the
seiiaI inteiface (SPI) mode is enteied. Mode 1 (Mode1
pin
e
0, Mode0 pin
e
1) seIects 16-bit InteI muIti-
pIexed addiess data bus. Mode 2 (Mode1 pin
e
1,
Mode0 pin
e
0) seIects an 8-bit non-InteI muItipIexed
addiess data bus. LastIy, Mode 3 (Mode1 pin
e
1,
Mode0 pin
e
1) seIects an 8-bit non-muItipIexed ad-
diess data bus foi eithei synchionous oi asynchionous
communication.
15 Clockout
The on-chip cIock geneiatoi consists of an osciIIatoi,
cIock dividei iegistei and a diivei ciicuit. The CIockout
output iange is XTAL (exteinaI ciystaI fiequency) to
XTAL/15. The CIockout output sIew iate is piogiam-
mabIe.
16 Two 8-Bit Ports
Two 8-bit Iow speed input/output (I/O) poits aie avaiI-
abIe on-chip. Depending on the CPU inteiface seIected,
at Ieast 7 and up to 16 of these I/O pins aie avaiIabIe
foi system use.
3
7
82527
20 PACKAGE DIAGRAMPIN OUT
44-Pin PLCC Package
2724102
44-Pin QFP Package
27241033
4
8
82527
30 PIN DESCRIPTION
Pin Description
V
SSI
Ground (0V) connection must be shorted externally to a V
SS
board plane to provide digital
ground
V
SS2
Ground (0V) connection must be shorted externally to a V
SS
board plane to provide ground
for analog comparator
V
CC
Power connection must be shorted externally to
a
5V DC to provide power to the entire chip
XTAL1 Input for an external clock XTAL1 (along with XTAL2) are the crystal connection to an internal
oscillator
XTAL2 Push-pull output from the internal oscillator XTAL2 and XTAL1 are the crystal connections to
an internal oscillator If an external oscillator is used XTAL2 must be floated or not be
connected XTAL2 must not be used as a clock output to drive other CPUs
CLKOUT Programmable clock output This push-pull output may be used to drive the oscillator of the
CPU
RESET Warm Reset (V
CC
remains valid while RESET is asserted) Reset must be driven to a low
level for 1 ns minimum
Cold Reset (V
CC
is driven to a valid level while Reset is asserted) Reset must be driven
low for 1 ns minimum measured from a valid V
CC
level No falling edge on the Reset pin is
required during a cold reset event
CS A low level on this pin enables the CPU to access the 82527
INT or The interrupt pin is an open collector output (requires external pullup resistor) to the CPU
V
CC
2 is the power supply for the ISO low speed physical layer The function of this pin is (V
CC
2)
determined by the MUX bit in the CPU Interface Register (Address 02H) when the DcR1 bit
(Address 2FH) is set
when MUX
e
1 and DcR1
e
1 then pin 24
e
V
CC
2 pin 11
e
INT
when MUX
e
0 then pin 24
e
INT
RX0 Inputs from the CAN bus line(s) to the input comparator
RX1
A recessive level is read when RX0
l
RX1 A dominant level is read when RX1
l
RX0 When
the CoBy bit (Bus Configuration register) is programmed as a 1 the input comparator is
bypassed and RX0 is the CAN bus line input
TX0 Serial push-pull data output to the CAN bus line During a recessive bit TX0 is high and TX1 is
low During a dominant bit TX0 is low and TX1 is high TX1
TX0TX1 suggestion
Unlike the Intel 82526 the 82527 TX0 and TX1 output drivers can not be individually
programmed to transmit either recessive or dominant bits this is fixed as described in the
TX0TX1 definition If 82527 and 82526 devices are not communicating on a CAN bus the
problem may be due to TX0TX1 configuration differences Reversing the TX0TX1
connections for either device may allow these devices to communicate
Ports12 Port1 and Port2 pins are weakly held high until the Port configuration registers have been
written (locations 9FH and AFH respectively)
5
9
82527
30 PIN DESCRIPTION(Continued)
Pin Description
AD0AD15 The functions of these pins are defined below
8-Bit 8-Bit 16-Bit 8-Bit
Serial
Intel Non-Intel Intel Non-
Interface
Multiplexed Multiplexed Multiplexed Multiplexed
AD0 AD0 AD0 AD0 A0 ICP
AD1 AD1 AD1 AD1 A1 CP
AD2 AD2 AD2 AD2 A2 CSAS
AD3 AD3 AD3 AD3 A3 STE
AD4 AD4 AD4 AD4 A4 MOSI
AD5 AD5 AD5 AD5 A5 Unused
AD6 AD6 AD6 AD6 A6 SCLK
AD7 AD7 AD7 AD7 A7 Unused
AD8 Port 10 Port 10 AD8 D0 Port 10
P20 Port 2 function in all CPU interface modes
P21
P22
P23
P24
P25
P26INT P26 is INT when MUX
e
1 in the CPU Interface register (02H)
P27WRH P27 is WRH in 16-bit multiplexed mode (Mode1)
Mode0 These pins select one of the four parallel interfaces
Mode1 Mode1 Mode0
0 0 8-bit multiplexed Intel
0 1 16-bit multiplexed Intel
1 0 8-bit multiplexed non-Intel
1 1 8-bit non-multiplexed
Note If upon reset Mode0
e
Mode1
e
0 RD e
0 and WR e
0 then the serial
interface mode is entered
Mode0 and Mode1 pins are internally connected to weak pulldowns These pins will be
pulled low during reset if unconnected Following reset these pins float
ALE ALE used for Intel CPU Interface Modes 0 and 1
AS AS used for non-Intel modes Except Mode 3 this pin must be tied high
6
10
82527
30 PIN DESCRIPTION(Continued)
Pin Description
RD RD used for CPU Interface Modes 0 and 1
E E used for non-Intel modes Except Mode 3 Asynchronous this pin must be tied high
WRWRL WR used for Intel CPU Interface Modes 0 and 1 (WRL function in Mode1 16-bit
Mode) RW used for CPU Interface Mode3 RW
READY READY is an open-drain output to synchronize accesses from the CPU to the 82527 for
CPU Interface Modes 0 and 1 MISO is the serial data output for the serial interface MISO
mode
DSACK0 DSACK0 is an open-drain output to synchronize accesses from the CPU to the 82527
for CPU Interface Mode3
DSACK0 is often used as a pulldown output with a 33 kX pullup resistor and a 100 pF
load capacitance An open-drain output is used because many peripherals may be
connected to the DSACK0 line
The 82527 specifies a TCHKH timing (CS high to DSACK0 high) equal to 55 ns
however a 33 kX resistor will not sufficiently charge the line when DSACK0 is floated
by the 82527 To meet this timing the 82527 has an active pullup that drives the
DSACK0 output until it is high and then the pullup is turned off Therefore the pullup is
only active for a short time
7
11
82527
31 Hardware Reset
Duiing powei up, the RFSFT pin must be diiven to a
vaIid Iow IeveI (0.8V) foi 1 ms measuied fiom a vaIid
V
CC
IeveI to ensuie the osciIIatoi is stabIe. The iegisteis
of the 82527 have the foIIowing vaIues aftei waim ieset:
Register Reset Value
Control Register (00H) 01H
Status Register (01H) Undefined
CPU Interface Register (02H) 61H
High Speed Register (0405H) Unchanged
Global Mask Short (0607H) Unchanged
Global Mask Long (080BH) Unchanged
Mask Last Message (0C0FH) Unchanged
Clockout Register (1FH) 00H or 01H
depending on
CPU Interface
Mode
Bus Configuration (2FH) 00H
Bit Timing Register 0 (3FH) Unchanged
Bit Timing Register 1 (4FH) Unchanged
Interrupt Register (5FH) 00H
P1 Configuration Register (9FH) 00H
P2 Configuration Register (AFH) 00H
P1 In (BFH) FFH
P2 In (CFH) FFH
PI Out (DFH) 00H
P2 Out (EFH) 00H
SPI Reset Address (FFH) Undefined
Messages 115 Unchanged
The eiioi management counteis and the busoff state
aie ieset by a haidwaie ieset.
If a haidwaie ieset occuis at powei on, iegisteis de-
fined as unchanged shouId be inteipieted as undefined.
Pins have the foIIowing states aftei ieset:
Pin Reset state
Mode 01 0 - while RESET is active
(high impedance - after reset)
Port 12 1 - weakly pulled high
(following configuration output
or high impedance input)
Clockout 0
TX0 1 - recessive state
TX1 0 - recessive state
INT Float
DSACK0 Float
32 Software Initialization
Softwaie initiaIization is staited by setting the Init bit
in the ContioI Registei, eithei by softwaie, haidwaie
ieset, oi by going busoff. WhiIe Init is set, aII message
tiansfeis to and fiom the 82527 aie stopped and the
TX0 and TX1 outputs aie iecessive. The eiioi counteis
aie unchanged. InitiaIization is used to configuie the
82527 RAM without iisk of CAN bus ieceptions oi
tiansmissions.
Resetting Init compIetes initiaIization and the 82527
synchionizes itseIf to the CAN bus by waiting foi 11
consecutive iecessive bits (caIIed bus idIe) befoie it wiII
take pait in bus activities.
Note that busoff iecoveiy cannot be hastened by setting
oi iesetting the Init bit. If the 82527 goes busoff, the
82527 wiII set the Init bit itseIf and theieby stopping its
bus activities. Once Init is cIeaied by the CPU, the
82527 wiII wait foi 128 occuiiences of bus idIe befoie
iesuming noimaI opeiation. Duiing the initiaIization
sequence, each time eIeven iecessive bits aie ieceived, a
Bit0 Fiioi code is wiitten to the status iegistei enabIing
the CPU to ieadiIy check whethei oi not the CAN bus
is stuck in a dominant state.
Softwaie initiaIization does not change configuiation
iegistei vaIues.
40 FUNCTIONAL DESCRIPTION
This section discusses the functionaI opeiation of the
82527 by desciibing the iegisteis used to configuie the
chip and message objects. The 82527 addiess map is
shown in Section 4.1.
8
12
82527
41 82527 Address Map
00H Control Register
01H Status Register
02H CPU Interface Reg
03H Reserved
0405H High Speed Read
0607H Global Mask - Standard
080BH Global Mask - Extended
0C0FH Message 15 Mask
101EH Message 1
1FH CLKOUT Register
202EH Message 2
2FH Bus Config Reg
303EH Message 3
3FH Bit Timing Reg 0
404EH Message 4
4FH Bit Timing Reg 1
505EH Message 5
5FH Interrupt Register
606EH Message 6
6FH Reserved
70H7EH Message 7
7FH Reserved
808EH Message 8
8FH Reserved
909EH Message 9
9FH P1CONF
A0AEH Message 10
AFH P2CONF
B0BEH Message 11
BFH P1IN
C0CEH Message 12
CFH P2IN
D0DEH Message 13
DFH P1OUT
E0EEH Message 14
EFH P2OUT
F0FEH Message 15
FFH Serial Reset Address
NOTE
denotes configuration registers The CPU may write to
these registers if CCE bit e 1 (Control register)
42 Control Register (00H)
7 6 5 4 3 2 1 0
0 CCE 0 0 EIE SIE IE Init
rw rw r r rw rw rw rw
r e readable
w e writable
The defauIt vaIue of the ContioI Registei aftei a haid-
waie ieset is 01H.
CCE Change Configuiation FnabIe
one The CPU has wiite access to configuiation
iegisteis.
zeio The CPU has no wiite access to configuiation
iegisteis.
Configuiation iegistei addiesses aie 1FH,
2FH, 3FH, 4FH, 9FH, AFH. This bit is ie-set
by the CPU to piovide piotection against un-
intentionaI ie-wiiting of ciiticaI iegisteis by
the CPU foIIowing the initiaIization sequence.
EIE Fiioi Inteiiupt FnabIe
one Fiioi inteiiupts enabIed. A change in the ei-
ioi status of the 82527 wiII cause an inteiiupt
to be geneiated.
zeio Fiioi inteiiupts disabIed. No eiioi inteiiupt
wiII be geneiated.
Fiioi inteiiupts aie BOff and Wain in the
status iegistei. Fiioi Inteiiupt FnabIe is set
by the CPU to aIIow the 82527 to inteiiupt
CPU when an abnoimaI numbei of CAN bus
eiiois have been detected. It is iecommended
to enabIe this inteiiupt duiing noimaI opeia-
tion.
SIE Status Change Inteiiupt FnabIe
one Status Change inteiiupt enabIed. An inteiiupt
wiII be geneiated when a CAN bus eiioi is
detected in the Status Registei oi a tiansfei
(ieception oi tiansmission) is successfuIIy
compIeted, independent of the inteiiupt en-
abIe bits in any message object.
zeio Status Change inteiiupt disabIed. No status
inteiiupt wiII be geneiated.
Status change inteiiupts aie Wake, RXOK,
TXOK, and LFC0-2 in the status iegistei and
this bit is set by the CPU. RXOK occuis upon
eveiy successfuI message tiansmission on the
CAN bus, iegaidIess of whethei the message
is stoied by the 82527.
9
13
82527
This inteiiupt is usefuI foi haidwaie deveIop-
ment to detect bus eiiois caused by physicaI
Iayei issues such as noise. The LFC bits aie
veiy heIpfuI to indicate whethei bit oi foim
eiiois aie occuiiing. In noimaI opeiation it is
not advised to enabIe this inteiiupt foi LFC
eiiois since the CAN piotocoI was designed
to handIe these eiioi conditions in haidwaie
by eiioi fiames and the automatic ietiansmis-
sion of messages. When cumuIative LFC ei-
iois iesuIt, the waining and busoff fIags wiII
be set and the Fiioi Inteiiupt shouId be en-
abIed to detect these conditions.
In most appIications, this bit shouId not be set.
Since this inteiiupt wiII occui foi eveiy mes-
sage, the CPU wiII be unnecessaiiIy buidened.
Instead, inteiiupts shouId be impIemented on
a message object basis so inteiiupts occui onIy
foi messages that aie used by the CPU.
If the Status Change Inteiiupts and message
object ieceive/tiansmit inteiiupts aie enabIed,
theie wiII be two inteiiupts foi each message
successfuIIy ieceived by a message object.
IE Inteiiupt FnabIe
one OIobaI inteiiupts enabIed. AppIies to FIF,
SIF, and message object TX/RX inteiiupts.
zeio OIobaI inteiiupts disabIed. The 82527 wiII
geneiate no inteiiupts aIthough the inteiiupt
iegistei (5FH) wiII stiII be updated. If the in-
teiiupt contains some vaIue othei than zeio
when this bit is set to one, an inteiiupt wiII be
geneiated. Foi exampIe, no inteiiupt wiII be
Iost because of peiiodic setting oi iesetting of
this bit.
The Inteiiupt FnabIe bit is set by the CPU.
Init InitiaIization
one Softwaie initiaIization is enabIed.
zeio Softwaie initiaIization is disabIed.
FoIIowing a haidwaie ieset, this bit wiII be set.
The Init bit is wiitten by the CPU and is set
by the 82527 when it goes busoff. InitiaIiza-
tion is a state which aIIows the usei to config-
uie the 82527 RAM without the chip paitici-
pating in any CAN bus tiansmissions. WhiIe
Init equaIs one, aII message tiansfeis to and
fiom the CAN bus aie stopped, and the status
of the CAN bus outputs, TX0 and TX1 aie
iecessive.
InitiaIization wiII most often be used the fiist
time aftei powei-up and when the 82527 has
iemoved itseIf fiom the CAN bus aftei going
busoff. Init shouId not be used in noimaI opei-
ation when the CPU is modifying tiansmit
data, the CPU Update bit in each message ob-
ject is used in this case.
Init set to one does not bieak a tiansmission
oi ieception of a message in piocess, but wiII
stop the 82527 fiom tiansmitting oi ieceiving
the next message.
PIease see section 3.2 foi additionaI infoima-
tion.
Reseived Bits 7, 5, and 4
one This vaIue must not be piogiammed by the
usei.
zeio A zeio must aIways be wiitten to this bit.
43 Status Register (01H)
7 6 5 4 3 2 1 0
BOff Warn Wake RXOK TXOK LEC2 LEC1 LEC0
r r r rw rw rw rw rw
The defauIt vaIue of the Status Registei aftei a haid-
waie ieset is undefined.
BOff Bus Off Status
one Theie is an abnoimaI iate of occuiiences of
eiiois on the CAN bus. This condition occuis
when an eiioi countei in the 82527 has
ieached the Iimit of 256. This iesuIts in the
82527 going busoff. Duiing busoff, no mes-
sages can be ieceived oi tiansmitted. The onIy
way to exit this state is by iesetting the Init bit
in the ContioI iegistei (Iocation 00H). When
this bit is ieset, the busoff iecoveiy sequence
begins. The busoff iecoveiy sequence iesets
the tiansmit and ieceive eiioi counteis. Aftei
the 82527 counts 128 packets of 11 consecu-
tive iecessive bits on the CAN bus, the busoff
state is exited.
zeio The 82527 is not busoff.
The Bus Off Status bit is wiitten by the 82527.
Warn Waining Status
one Theie is an abnoimaI iate of occuiiences of
eiiois on the CAN bus. This condition occuis
when an eiioi countei in the 82527 has
ieached the Iimit of 96.
zeio Theie is no abnoimaI occuiience of eiiois.
The Waining Status bit is wiitten by the
82527. When this bit is set, an inteiiupt wiII
occui if the FIF and IF bits of the ContioI
Registei (00H) aie set. The Waining Status bit
is wiitten by the 82527.
Wake Wake up Status
one This bit is set when the 82527 had been pievi-
ousIy set into SIeep mode by the CPU, and bus
activity occuis. The SIeep bit oi the Powei-
down bit in the CPU Inteiface iegistei is ieset
(Iocation 02H) by the CPU.
10
14
82527
zeio The Wake Up inteiiupt is ieset by ieading the
Status Registei.
Setting the SLFFP bit (bit 3, iegistei 02H) to
a 1 wiII pIace the 82527 into SLFFP mode.
WhiIe in SLFFP mode, the WAKF bit is 0.
The WAKF bit wiII become 1 when bus ac-
tivity is detected oi when the CPU wiites the
SLFFP bit to 0. The WAKF bit wiII aIso be
set to 1 aftei the 82527 comes out of Powei
Down mode. This bit is wiitten by the 82527.
RXOK Receive Message SuccessfuIIy
one Since this bit was Iast ieset to zeio by the
CPU, a message has been successfuIIy ie-
ceived.
zeio Since this bit was Iast ieset by the CPU, no
message has been successfuIIy ieceived. This
bit is nevei ieset by the 82527.
A successfuIIy ieceived message may be any
CAN bus tiansmission that is eiioi-fiee, ie-
gaidIess of whethei the 82527 has configuied
a message object to ieceive that paiticuIai
message identifiei. This bit may be cIeaied by
the CPU. The 82527 wiII set this bit, but wiII
not cIeai it.
TXOK Tiansmit Message SuccessfuIIy
one Since this bit was Iast ieset to zeio by the
CPU, a message has been successfuIIy tians-
mitted (eiioi fiee and acknowIedged by at
Ieast one othei node).
zeio Since this bit was Iast ieset by the CPU, no
message has been successfuIIy tiansmitted.
This bit is nevei ieset by the 82527.
This bit may be cIeaied by the CPU. The
82527 wiII set this bit, but wiII not cIeai it.
LEC 02 Last Fiioi Code
This fieId contains a code which indicates the
type of the fiist eiioi to occui in a fiame on
the CAN bus. If a message is without eiioi
the fieId wiII be cIeaied to 0. The code 7 is
unused and may be wiitten by the CPU to
check foi updates.
0 No eiioi
1 Stuff Fiioi
Moie than 5 equaI bits in a sequence have occuiied
in a pait of a ieceived message wheie this is not
aIIowed.
2 Foim Fiioi
The fixed foimat pait of a ieceived fiame has the
wiong foimat.
3 AcknowIedgment Fiioi (AckFiioi)
The message tiansmitted by this device was not ac-
knowIedged by anothei node.
4 Bit 1 Fiioi
Duiing the tiansmission of a message (with the ex-
ception of the aibitiation fieId), the 82527 wanted to
send a iecessive IeveI (bit of IogicaI vaIue 1), but the
monitoied CAN bus vaIue was dominant.
5 Bit 0 Fiioi
Duiing the tiansmission of a message (with the ex-
ception of the aibitiation fieId), the 82527 wanted to
send a dominant IeveI (bit of IogicaI vaIue 0), but the
monitoied CAN bus vaIue was iecessive. Duiing bu-
soff iecoveiy, this status is set each time a iecessive
bit is ieceived (indicating the CAN bus is not stuck
dominant).
6 CRC Fiioi
The CRC checksum was incoiiect in the message
ieceived. The CRC ieceived foi an incoming mes-
sage does not match with the CRC vaIue caIcuIated
by this device foi the ieceived data.
7 Unused
Status Interrupts
The status change inteiiupt has a vaIue of 1. The Status
Registei must be iead if a status change inteiiupt oc-
cuis. NOTE Reading the status iegistei wiII cIeai the
status change inteiiupt (vaIue
e
1) fiom the Inteiiupt
Registei (5FH), if a status change inteiiupt is pending.
A status change inteiiupt wiII occui on eveiy successfuI
ieception oi tiansmission, iegaidIess of the state of the
RXOK and TXOK bits. Theiefoie, if TXOK is set and
a subsequent tiansmission occuis, an inteiiupt wiII oc-
cui (if enabIed) even though TXOK was pieviousIy
equaI to one.
Theie aie two ways to impIement ieceive and tiansmit
inteiiupts. The diffeience between these two methods is
one ieIies on the haidwiied piioiity of the message ob-
jects and the othei is suitabIe foi poIIing. The fiist and
piefeiied method uses the TXIF and RXIF bits in the
message contioI iegistei foi each coiiesponding mes-
sage object. Whenevei a message is tiansmitted oi ie-
ceived by this message object, the coiiesponding intei-
iupt is seiviced in accoidance with its piioiity (if the IF
bit of iegistei 00H is set). This method uses the haid-
wiied piioiity scheme of the 82527 which iequiies min-
imaI CPU inteivention.
The second method sets the SIF bit of the ContioI Reg-
istei to 1 which wiII foice an inteiiupt whenevei suc-
cessfuI message tiansmissions oi ieceptions occui. The
RXOK and TXOK bits wiII be set when any of the
message objects tiansmits oi ieceives a message. A suc-
cessfuIIy ieceived message may be any CAN bus tians-
mission that is eiioi-fiee, iegaidIess of whethei the
82527 has configuied a message object to ieceive that
paiticuIai message identifiei. This method aIIows the
usei to moie easiIy define the inteiiupt piioiity of each
message object by poIIing the message objects foIIowing
an SIF inteiiupt.
11
15
82527
44 CPU Interface Register (02H)
7 6 5 4 3 2 1 0
RstST DSC DMC PwD Sleep MUX 0 CEn
r rw rw rw rw rw rw rw
The defauIt vaIue of the CPU Inteiface Registei in
haidwaie ieset is F1H. The defauIt vaIue of the CPU
Inteiface Registei aftei haidwaie ieset (RFSFT is de-
activated) is 61H.
RstSt Haidwaie Reset Status
one The haidwaie ieset of the 82527 is active (RF-
SFT is Iow). WhiIe ieset is active, no access
to the 82527 is possibIe.
zeio NoimaI opeiation. The CPU must ensuie this
bit is zeio befoie the fiist access to the 82527
aftei ieset.
This bit is wiitten by the 82527.
DSC Divide System CIock (SCLK). The SCLK may
not exceed 10 MHz. See section 4.5.
one The system cIock, SCLK, is equaI to
XTAL/2.
zeio The system cIock, SCLK, is equaI to XTAL.
This bit is wiitten by the CPU.
DMC Divide Memoiy CIock. The memoiy cIock may
not exceed 8 MHz. See section 4.5.
one The memoiy cIock, MCLK, is equaI to
SCLK/2.
zeio The memoiy cIock, MCLK, is equaI to SCLK.
PwD Powei Down Mode enabIe
SIeep SIeep Mode enabIe
PwD SIeep
zeio zeio Both Powei Down and SIeep
Modes aie not active.
one zeio Powei Down Mode is active.
zeio one SIeep Mode is active.
These bits aie wiitten by the CPU.
MUX MuItipIex foi ISO Low Speed PhysicaI Layei.
If V
CC
/2 is used to impIement the basic CAN
physicaI Iayei, pin 24 piovides the voItage out-
put V
CC
/2, and pin 11 is the inteiiupt output
tiansmitted to the CPU. Otheiwise, onIy the in-
teiiupt is avaiIabIe on pin 24. V
CC
/2 is onIy
avaiIabIe duiing noimaI opeiation and duiing
SIeep Mode and not duiing Powei Down Mode.
NOTE
The DcR1 bit (Addiess 2FH) must be set to
enabIe V
CC
/2 on Pin 24.
one ISO Iow speed physicaI Iayei active: Pin 24
e
V
CC
/2, Pin 11
e
INT.
zeio NoimaI opeiation: Pin 24
e
INT, Pin 11
e
P2.6.
Reserved Bit 1
usei.
CEn CIockout enabIe
one CIockout signaI is enabIed, (defauIt aftei ie-
set).
zeio CIockout signaI is disabIed.
Low Current Modes
Powei Down and SIeep Modes aie activated by the
PwD and SIeep bits in the CPU Inteiface iegistei (02H)
undei the contioI of the piogiammei. This iegistei is
accessibIe duiing ieset and noimaI opeiation. In both
modes the osciIIatoi and cIockout output aie not active
and no access to the message objects is possibIe. Access
to the CPU Inteiface iegistei (02H) is aIIowed.
The 82527 exits fiom Powei Down by eithei a haid-
waie ieset oi by iesetting the PwD bit to 0. The CPU
must iead the haidwaie ieset bit, RstSt, (bit 7, iegistei
02H) to ensuie the 82527 has exited Powei Down.
The 82527 enteis SIeep Mode aftei the SIeep bit in the
CPU Inteiface iegistei (bit 3, iegistei 02H) is set. The
SIeep cuiient is dependent on the MUX bit vaIue of the
CPU Inteiface iegistei (bit 2, iegistei 02H). When the
V
CC
/2 featuie is enabIed, ICC is specified to be 700 mA
maximum and is 100 mA with the INT featuie en-
abIed. SIeep mode is exited by iesetting the SIeep bit oi
when theie is activity on the CAN bus. The 82527 ie-
quiies a minimum of 10 ms to come out of SIeep Mode
aftei bus activity occuis.
Powei Down and SIeep Mode shouId not be enteied
diiectIy aftei RFSFT. The usei piogiam must peifoim
a minimum RAM configuiation at any time (piefeiabIy
duiing the initiaIization) piioi to enteiing these modes.
Piogiamming the foIIowing iegisteis satisfies the mini-
mum configuiation iequiiement.
ContioI Registei (00H) - set CCF bit to 1,
Bus Configuiation Registei (2FH)
Bit Timing Registei 1 (4FH)
ContioI Registei (00H) - Init bit ieset to 0
Wiiting these iegisteis wiII activate 82527 ciicuitiy ie-
quiied to ensuie minimum powei consumption.
12
16
82527
45 Clocking Description
The cIocking of the 82527 is dependent upon the osciI-
Iatoi (XTAL), the system cIock (SCLK) and the mem-
oiy cIock (MCLK). The SCLK and MCLK fiequencies
aie deteimined by the exteinaI osciIIatoi (XTAL) and
the DSC and DMC bits in the CPU Inteiface iegistei
(02H).
The 82527 is tested with XTAL set to 8 MHz and
16 MHz. Chaiacteiization data veiifies the 82527 wiII
opeiate with XTAL equaI to 4 MHz.
The SCLK may be equaI to XTAL oi XTAL/2 de-
pending upon the DSC bit vaIue of the CPU Inteiface
iegistei. The SCLK contioIs the piocessing functions of
the 82527 such as bit timing contioI and tiansceivei
contioI Iogic. The MCLK may be equaI to SCLK/2 oi
SCLK depending upon the vaIue of the DMC bit. The
MCLK contioIs the CPU inteiface timings and has a
diiect ieIationship to host CPU-to-82527 communica-
tions iate.
The SCLK is iestiicted to a 10 MHz maximum fie-
quency, and the MCLK is iestiicted to a 8 MHz maxi-
mum fiequency. The SCLK is used to caIcuIate tq
which is iefeienced in the Bit Timing Registei 0 (3FH)
desciiption. The MCLK is used to define AC timings
specifications.
The maximum MCLK fiequency foi vaiious osciIIatoi
fiequencies is shown beIow:
fXTAL SCLK (DSC bit) MCLK (DMC bit)
4 MHz 4 MHz (0) 4 MHz (0)
8 MHz 8 MHz (0) 8 MHz (0)
10 MHz 10 MHz (0) 5 MHz (1)
12 MHz 6 MHz (1) 6 MHz (0)
16 MHz 8 MHz (1) 8 MHz (0)
Fiequency of SCLK
e
fXTAL/(1
a
DSC bit)
Fiequency of MCLK
e
fSCLK/(1
a
DMC bit)
e
fXTAL/(1
a
DSC bit)
c
(1
a
DMC bit)
The SCLK (system cIock) is used to contioI bit timings
and the tiansceivei ciicuitiy oi in othei woids, the
CAN bus. The MCLK (memoiy cIock) is used to con-
tioI the 82527 timings used foi the 82527/CPU-host
inteiface.
46 High Speed Read Register
(0405H)
04H
7 6 5 4 3 2 1 0
Low Byte
r
05H
7 6 5 4 3 2 1 0
High Byte
r
The High Speed Read iegistei is a iead onIy iegistei
and is the output buffei foi the CPU Inteiface Logic.
This iegistei is pait of the CPU Inteiface Logic and is
not Iocated in the RAM. Duiing a iead to the RAM
(Iow speed iegisteis) this iegistei is Ioaded with the vaI-
ue of the Iow speed iegistei being accessed.
The High Speed Read iegistei is avaiIabIe to piovide a
method to iead the 82527 when the CPU (host micio-
contioIIei) is unabIe to satisfy iead cycIe timings foi
Iow speed 82527 iegisteis. In othei woids, if the iead
access time of the 82527 is too sIow foi the CPU and
the CPU cannot extend the iead bus cycIe, the foIIow-
ing method shouId be used.
The defauIt vaIue of the high speed iead iegistei aftei a
haidwaie ieset is unchanged. Unchanged defauIt vaI-
ues shouId be inteipieted as undefined if a haidwaie
ieset occuis duiing powei on.
Double Read Operation
The CPU can execute doubIe ieads wheie the fiist iead
addiesses the Iow speed iegistei and the second iead
addiesses the High Speed Read iegistei. The fiist iead
is a dummy iead foi the CPU, howevei the Iow speed
iegistei vaIue is stoied in the High Speed Read iegistei.
The second iead to the High Speed Read iegistei wiII
pioduce the data fiom the desiied Iow speed iegistei.
The advantage of doubIe ieads is both iead opeiations
have fast access times. The fiist iead of the Iow speed
iegistei iequiies 40 ns (veiify in cuiient data sheet) to
Ioad the High Speed Read Registei (the data on the
addiess/data pins is not vaIid). The second iead of the
High Speed Read iegistei iequiies 45 ns (veiify in cui-
ient data sheet) and the data on the addiess/data bus is
vaIid.
Theiefoie, if the access time of a Iow speed iegistei is
too Iong foi the CPU then a second iead to the High
Speed Registei wiII pioduce the coiiect data. PIease
note Iow and High Speed Registeis have diffeient ac-
cess timing specifications in the 82527 data sheet.
13
17
82527
Duiing a 16-bit iead access the Iow and high byte wiII
contain the 16-bit vaIue fiom the iead access. Foi an
8-bit iead access the Iow byte wiII contain the vaIue
fiom the iead access.
47 Global MaskStandard Register
(0607H)
06H
7 6 5 4 3 2 1 0
ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21
rw rw rw rw rw rw rw rw
07H
7 6 5 4 3 2 1 0
ID20 ID19 ID18 Reserved
rw rw rw
Reseived bits iead as 1
The defauIt vaIue of the OIobaI Mask - standaid aftei a
haidwaie ieset is unchanged.
The OIobaI Mask - standaid iegistei appIies onIy to
messages using the standaid CAN identifiei, oi foi
message objects with the XTD bit set to 0. This fea-
tuie, aIso caIIed message acceptance fiIteiing, aIIows
the usei to OIobaIIy Mask, oi dont caie any identifi-
ei bits of the incoming message. This mask is piogiam-
mabIe to aIIow the usei to deveIop an appIication spe-
cific masking stiategy.
A 0 vaIue means dont caie oi accept a 0 oi 1
foi that bit position. A 1 vaIue means that the incom-
ing bit vaIue must-match identicaIIy to the coiie-
sponding bit in the message identifiei.
When a iemote fiame is sent, an 82527 ieceivei node
wiII use the OIobaI Mask iegisteis to deteimine wheth-
ei the iemote fiame matches any of its message objects.
If the 82527 is piogiammed to tiansmit a message in
iesponse to a iemote fiame message identifiei, the
82527 wiII tiansmit a message with the message identi-
fiei of the 82527 message object. The iesuIt is the ie-
mote message and the iesponding 82527 tiansmit mes-
sage may have diffeient message identifieis because
some 82527 gIobaI mask iegistei bits aie 0.
NOTE
PIease see section 4.9, Acceptance FiIteiing ImpIica-
tions.
48 Global MaskExtended Register
(080BH)
08H
7 6 5 4 3 2 1 0
09H
7 6 5 4 3 2 1 0
0AH
7 6 5 4 3 2 1 0
0BH
7 6 5 4 3 2 1 0
ID4 ID3 ID2 ID1 ID0 Reserved
rw rw rw rw rw rw
Reseived bits iead as 000
The defauIt vaIue of the OIobaI Mask - extended aftei a
The OIobaI Mask - extended iegistei appIies onIy to
messages using the extended CAN identifiei, oi mes-
sage objects with the XTD bit set to 1. This featuie
aIIows the usei to OIobaIIy Mask, oi dont caie, any
identifiei bits of the incoming message. This mask is
piogiammabIe to aIIow the usei the deveIop an appIica-
tion specific masking stiategy. A 0 vaIue means
dont caie on that bit foi acceptance fiIteiing. A 1
vaIue means that the 82527 wiII considei this bit foi
acceptance fiIteiing.
When a iemote fiame is sent, an 82527 ieceivei node
wiII use its OIobaI Mask iegisteis to deteimine whethei
the iemote fiame matches any of its message objects. If
the 82527 is piogiammed to tiansmit a message in ie-
sponse to a iemote fiame message identifiei, the 82527
wiII tiansmit a message with the message identifiei of
the 82527 message object. The iesuIt is the iemote mes-
sage and the iesponding 82527 tiansmit message may
have diffeient message identifieis because some 82527
OIobaI Mask iegistei bits aie 0.
NOTE
PIease see section 4.9, Acceptance FiIteiing ImpIica-
tions.
14
18
82527
49 Acceptance Filtering Implications
The 82527 impIements two acceptance masks which aI-
Iow message objects to ieceive messages with a iange of
message identifieis (IDs) instead of just a singIe mes-
sage ID. This piovides the appIication the fIexibiIity to
ieceive a wide assoitment of messages fiom the bus.
The 82527 obseives aII messages on the CAN bus and
stoies any message that matches a messages ID pio-
giammed into an active message object. It is possibIe
to define which message ID bits must identicaIIy match
those piogiammed in the message objects to stoie the
message. Theiefoie, ID bits of incoming messages aie
eithei must-match oi dont-caie. By seIecting bits
to be dont-caie, message objects wiII ieceive muIti-
pIe message IDs.
NOTE
Message objects piogiammed to tiansmit aie aIso ef-
fected by the OIobaI Masks (standaid and extended).
The 82527 uses the OIobaI Mask iegisteis to identify
which of its message objects tiansmitted a message. If
two 82527 tiansmit message objects have message IDs
that aie non-distinct in aII must-match bit Iocations,
a successfuI tiansmission of the highei numbeied mes-
sage object wiII not be iecognized by the 82527. The
Iowei numbeied message object wiII be faIseIy identi-
fied as the tiansmit message object and its tiansmit ie-
quest bit wiII be ieset and its inteiiupt pending bit set.
The actuaI tiansmit message object wiII ie-tiansmit
without end because its tiansmit iequest bit wiII not
be ieset.
This couId iesuIt in a catastiophic condition since the
highei numbeied message object may dominate the
CAN bus by iesending its message without end.
To avoid this condition, appIications shouId iequiie aII
tiansmit message objects to use message IDs that aie
unique with iespect to the must-match bits. If this is
not possibIe, the appIication shouId disabIe Iowei num-
beied message objects with simiIai message IDs untiI
the highei numbeied message object has tiansmitted
successfuIIy.
Anothei configuiation to avoid fiIteiing issues is to
dedicate messages 114 foi tiansmit and use message
15 foi ieceive. The message 15 mask wiII have no im-
pact on messages 114.
The Acceptance Masks aIso appIy to iemote messages.
When the 82527 ieceives a iemote message, and a
tiansmit message ID matches aftei taking into account
the gIobaI masks, the 82527 wiII iespond by tiansmit-
ting a data message with its piogiammed message ID.
410 Message 15 Mask Register
(0C0FH)
0CH
7 6 5 4 3 2 1 0
0DH
7 6 5 4 3 2 1 0
0EH
7 6 5 4 3 2 1 0
0FH
7 6 5 4 3 2 1 0
rw rw rw rw r
Reseived iead as 000
The defauIt vaIue of the Message 15 Mask iegistei aftei
a haidwaie ieset is unchanged.
The Message 15 Mask iegistei is a piogiammabIe IocaI
mask. This featuie aIIows the usei to IocaIIy mask, oi
dont caie, any identifiei bits of the incoming mes-
sage foi message object 15. Incoming messages aie fiist
checked foi an acceptance match in message objects 1
14 befoie passing thiough to message object 15. Conse-
quentIy, the OIobaI Mask and the IocaI mask appIy to
messages ieceived in message object 15.
A 0 vaIue means dont caie oi accept a 0 oi 1
foi that bit position. A 1 vaIue means that the incom-
ing bit vaIue must-match identicaIIy to the coiie-
sponding bit in the message identifiei.
NOTE
The Message 15 Mask is ANDed with the OIobaI
Mask. This means that any bit defined as dont-caie
in the OIobaI Mask wiII automaticaIIy be a dont-
caie bit foi message 15.
411 CLKOUT (Clockout) Register
(1FH)
1FH
7 6 5 4 3 2 1 0
0 0 SL1 SL0 CD
V
r r rw rw rw
The CLKOUT iegistei contioIs the fiequency of the
CLKOUT signaI as weII as the sIew iate. The defauIt
fiequency of CLKOUT depends on the CPU inteiface
15
19
82527
mode. Foi Modes 0, 1 and seiiaI mode the defauIt fie-
quency is XTAL. Foi Modes 2 and 3 the defauIt fie-
quency is XTAL/2. The foIIowing aie the piogiamma-
bIe CLKOUT fiequencies and iecommended sIew
iates:
Table 2 Programming CLKOUT and Slew Rates
CDv
CLKOUT
Frequency
0 XTAL
1 XTAL2
10 XTAL3
11 XTAL4
100 XTAL5
101 XTAL6
110 XTAL7
111 XTAL8
1000 XTAL9
1001 XTAL10
1010 XTAL11
1011 XTAL12
1100 XTAL13
1101 XTAL14
1110 XTAL15
1111 Reserved
SL1 SL0 CLKOUT Conditions
0 0 CLKOUT
l
24 MHz
0 1 16 MHz
k
CLKOUT
s
24 MHz
1 0 8 MHz
k
CLKOUT
s
16 MHz
1 1 CLKOUT
k
8 MHz
The defauIt vaIue of the CLKOUT iegistei aftei a
haidwaie ieset is 00H (Modes 0 and 1 and seiiaI mode)
oi 01H (Modes 2 and 3). The sIew iate bits enabIe one
to foui puIIup and puIIdown iesistois which aIIows the
cIockout diivei stiength to be piogiammed.
412 Bus Configuration Register (2FH)
2FH
7 6 5 4 3 2 1 0
0 CoBy Pol 0 DcT1 0 DcR1 DcR0
Reserved Bits 7, 4 and 2
usei.
CoBy Compaiatoi Bypass
one The input compaiatoi is bypassed and the
RX0 input is iegaided as the vaIid bus input,
(DcR0 must be set to zeio).
zeio NoimaI opeiation: RX0 and RX1 aie the in-
puts to the input compaiatoi, (defauIt aftei
haidwaie ieset).
Pol PoIaiity
one If the input compaiatoi is bypassed then a Iog-
icaI one is inteipieted as dominant and a Iogi-
caI zeio is iecessive on the RX0 input.
zeio If the input compaiatoi is bypassed then a Iog-
icaI one is inteipieted as iecessive and a Iogi-
caI zeio is dominant bit on the RX0 input,
(defauIt aftei haidwaie ieset).
DcT1 Disconnect TX1 output
one DisabIes the TX1 output diivei. This mode is
foi use with a singIe wiie bus Iine, oi in the
case of a diffeientiaI bus when the two bus
Iines aie shoited togethei.
zeio FnabIes the TX1 output diivei, (defauIt aftei
haidwaie ieset).
DcR1 Disconnect RX1 input
one RX1 is disabIed and the RX1 input is discon-
nected fiom the inveiting compaiatoi input
and is iepIaced by a V
CC
/2 iefeience voItage.
zeio RX1 is enabIed and the RX1 input is connect-
ed to the inveiting input of the input compaia-
toi, (defauIt aftei haidwaie ieset).
DcR0 Disconnect RX0 input
one RX0 is disabIed and the RX0 input is discon-
nected fiom the non-inveiting compaiatoi in-
put and iepIaced by a V
CC
/2 iefeience voIt-
age. The MUX bit in the CPU Inteiface iegis-
tei (02H) must be set to one to activate the
V
CC
/2 iefeience voItage.
zeio RX0 is enabIed and the RX0 input is connect-
ed to the non-inveiting input of the input com-
paiatoi, (defauIt aftei haidwaie ieset).
The defauIt vaIue of the bus configuiation iegistei aftei
a haidwaie ieset is 00H.
413 Bit Timing Overview
A CAN message consists of a seiies of bits that aie
tiansmitted in consecutive bit times. A bit time ac-
counts foi piopagation deIay of the bit, CAN chip in-
put and output deIay, and synchionization toIeiances.
This section desciibes components of a bit time fiom
the peispective of the CAN Specification and the
82527.
16
20
82527
CAN Specification Bit Timing
Definitions
The bit timing iequiiements of the CAN Specification
Veision 2.0 (Septembei 1991) aie defined in section 8.
The nominaI bit time is composed of foui time seg-
ments: SYNC
-
SFO, PROP
-
SFO, PHASF
-
SFO1,
and a PHASF
-
SFO2. These time segments aie sepa-
iate and non-oveiIapping as shown beIow.
2724103
SYNC
-
SFO: This pait of the bit time is used to syn-
chionize the vaiious nodes on the bus. An edge is ex-
pected to Iie within this segment.
PROP
-
SFO: This pait of the bit time is used to com-
pensate foi the physicaI deIay times within the netwoik.
It is twice the sum of the signaIs piopagation time on
the bus Iine, the input compaiatoi deIay and the output
diivei deIay.
NOTE
The factoi of two accounts foi eiioi detection which
iequiies nodes to monitoi aII bus tiansmissions.
PHASF
-
SFO1, PHASF
-
SFO2: These phases aie
used to compensate foi edge phase eiiois. These seg-
ments can be Iengthened oi shoitened by iesynchioni-
zation.
SAMPLF POINT: The sampIe point is the point of
time at which the bus IeveI is iead and inteipieted as
the vaIue of that iespective bit. Its Iocation is at the end
of PHASF
-
SFO1.
82527 Bit Timing Definitions
The 82527 iepiesents SYNC
-
SFO, PROP
-
SFO,
PHASF
-
SFO1, and PHASF
-
SFO2 by dividing the
bit time into thiee time segments: t
SYNC
-
SFO
, t
TSFO1
and t
TSFO2
. The t piefix indicates the segment is a
Iength of time (i.e. nanoseconds, micioseconds). These
thiee time segments aie defined by iegistei fieIds caIIed
SYNC
-
SFO, TSFO1 and TSFO2, iespectiveIy. These
iegistei fieIds aie digitaI vaIues piogiammed into the
82527 Bit Timing Registeis.
2724104
17
21
82527
The pieceding figuie iepiesents a bit time fiom the pei-
spective of the 82527. A bit time is subdivided into time
quanta. One time quantum is deiived fiom the osciIIa-
toi (SCLK) and the baud iate piescaIei (BRP). The
Iength of the bit time iesuIts fiom the addition of the
piogiammabIe segments: SYNC
-
SFO, TSFO1 and
TSFO2.
TIMF QUANTUM (tq): A fixed unit of time deiived
fiom the system cIock peiiod (t
SCLK
) equaI to t
SCLK
x
(baud iate piescaIei
a
1).
t
SYNC
-
SFO
: Synchionizes the vaiious nodes on the
bus and an edge fiom the tiansmittei is expected to Iie
within this segment. The SYNC
-
SFO is 1 time quan-
tum.
t
TSFO1
: The sum of PROP
-
SFO and the
PHASF
-
SFO1 as defined by the CAN Specification.
TSFO1 is a vaIue piogiammed into the 82527 CAN
device to specify t
TSFO1
. In thiee sampIe mode, 2 time
quanta must be added to t
TSFO1
. This aIIows the 82527
to sampIe the bit two additionaI times piioi to sampIe
point at the end of TSFO1.
t
TSFO2
: This time segment is equivaIent to
PHASF
-
SFO2 as defined by the CAN Specification.
Bit Timing Relationships
The foIIowing aie ieIationships of the 82527 bit timing:
1. bittime
e
t
SYNC
-
SFO
a
t
TSFO1
a
t
TSFO2
(see pieceding figuie)
2. tq
e
t
SCLK
c
(BRP
a
1) wheie t
SCLK
is the peii-
od of the system cIock.
3. t
SYNC
-
SFO
e
1 tq
4. t
TSFO1
e
(TSFO1
a
1)
c
tq
(the 82527 adds one to TSFO1 in haidwaie)
5. TSFO1
e 2 . . . 15
(fieId in Bit Timing Registei 1)
6. t
TSFO2
e
(TSFO2
a
1)
c
tq
(the 82527 adds one to TSFO2 in haidwaie)
7. TSFO2
e 1 . . . 7
8. t
SJW
e
(SJW
a
1)
c
tq
(the 82527 adds one to SJW in haidwaie)
9. SJW
e 0 . . . 3
10. t
piop
e
two times the maximum of the sum of the
deIay of the physicaI bus deIay, the output diivei
deIay and the input compaiatoi deIay iounded up
to the neaiest muItipIe of tq.
11. The maximum osciIIatoi toIeiance equaIs
3.84 x t
SJW
/t
bittime
.
The foIIowing conditions must be met to maintain syn-
chionization.
1. t
TSFO2
t
2tq
(minimum toIeiance foi iesynchionization)
2. t
TSFO2
t
t
SJW
(If t
SJW
l
t
TSFO2
, sampIing may occui aftei the bit
time)
3. t
TSFO1
t
3tq
(minimum toIeiance foi iesynchionization with 1tq
piopagation deIay aIIowance)
4. t
TSFO1
t
t
SJW
a
t
piop
5. Foi thiee sampIe mode (SPL bit
e
1, iegistei 4Fh),
t
TSFO1
t
t
SJW
a
t
piop
a
2tq
414 Bit Timing Registers (3FH 4FH)
Bit timing iegisteis aie used to define the CAN bus
fiequency, the sampIe point within a bit time, and the
mode of synchionization.
Bit Timing Register 0 (3FH)
3FH
7 6 5 4 3 2 1 0
SJW BRP
rw rw
SJW (Re)Synchionization Jump Width
The vaIid piogiammed vaIues aie 03. The SJW
defines the maximum numbei of time quanta a
bit time may be shoitened oi Iengthened by one
iesynchionization. The actuaI inteipietation of
this vaIue by the haidwaie is to use one moie
than the piogiammed vaIue.
BRP Baud Rate PiescaIei
The vaIid piogiammed vaIues aie 063. The
baud iate piescaIei piogiams the Iength of one
time quantum as foIIows:
tq
e
t
SCLK
c
(BRP
a
1) wheie t
SCLK
is the
peiiod of the system cIock (SCLK).
The defauIt vaIue of the bit timing iegistei 0 aftei
a haidwaie ieset is unchanged.
Bit Timing Register 1 (4FH)
4FH
7 6 5 4 3 2 1 0
Spl TSEG2 TSEG1
rw rw rw
18
22
82527
Spl SampIing Mode
SampIing mode
e
zeio may iesuIt in fastei bit
tiansmissions iates, whiIe sampIing mode
e
one is moie immune to noise spikes on the
CAN bus.
one Thiee sampIes aie used foi deteimining the
vaIid bit vaIue using majoiity Iogic. The CAN
bus is sampIed thiee times pei bit time.
zeio One sampIe is used foi deteimining the vaIid
bit vaIue. The CAN bus is sampIed once pei
bit time.
TSEG1 Time Segment 1
The vaIid piogiammed vaIues aie 215.
TSFO1 is the time segment befoie the sampIe
point. The actuaI inteipietation of this vaIue
by the haidwaie is one moie than the vaIue
piogiammed by the usei.
TSEG2 Time Segment 2
The vaIid piogiammed vaIues aie 17.
TSFO2 is the time segment aftei the sampIe
point. The actuaI inteipietation of this vaIue
by the haidwaie is one moie than the vaIue
piogiammed by the usei.
NOTE
In oidei to achieve coiiect opeiation accoiding to the
CAN piotocoI, the totaI bit Iength shouId be a mini-
mum of 8tq with (TSFO1
a
TSFO2
t
5).
The defauIt vaIue of the bit timing iegistei 1 aftei a
415 Comparison of 82526 and 82527
Bit Timings Calculations
82527
The 82527 timings caIcuIations diffei fiom the 82526
since the 82527 timing equation impIicitIy accounts foi
synchionization jump widths.
CAN bus fiequency
e
XTAL fiequency/(DSC
a
1)
x (BRP
a
1) x (3
a
TSFO1
a
TSFO2) wheie the
DSC bit is found in the CPU inteiface iegistei, Iocation
02H.
FxampIe: Reg 02H
e
41H, Reg 3FH
e
4AH,
Reg 4FH
e
25H
with iesuIting bit timing paiameteis:
BRP
e
10 DSC
e
1
SJW
e
2 XTAL
e
16 MHz
TSFO1
e
5 TSFO2
e
2
CAN bus fiequency
e
16 MHz/(1
a
1) x (10
a
1) x
(3
a
5
a
2) e
72,727 bits/seconds
82526
CAN bus fiequency
e
XTAL fiequency/(BRP
a
1)
x 2 x (5
a
TSFO1
a
TSFO2
a
2 x SJW)
FxampIe: Reg 03H
e
C5H, Reg 04H
e
25H
with iesuIting bit timing paiameteis
INSYNC
e
1 BRP
e
5
SJW
e
3 XTAL
e
16 MHz
TSFO1
e
5 TSFO2
e
2
CAN bus fiequency
e
16 MHz/(5
a
1) x 2 x (5
a
5
a
2
a
2 x 3) e
74,074 bits/seconds
416 Interrupt Register (5FH)
5FH
7 6 5 4 3 2 1 0
Intld
r
IntId Inteiiupt Identifiei
The inteiiupt iegistei is a iead-onIy iegistei. The vaIue
in this iegistei indicates the souice of the inteiiupt.
When no inteiiupt is pending, this iegistei hoIds the
vaIue 0. If the SIF bit in the ContioI Registei (00H)
is set and the 82527 has updated the Status Registei,
the inteiiupt iegistei wiII contain a 1. This indicates
an inteiiupt is pending due to a change in the status
iegistei. The vaIue 2
a
message numbei indicates the
IntPnd bit in the coiiesponding message object is set.
Theie is an exception in that message object 15 wiII
have the vaIue 2, giving message object 15 the highest
piioiity of aII message objects. The defauIt vaIue of the
inteiiupt iegistei aftei a haidwaie ieset is undefined.
19
23
82527
Interrupt Register Value (hex)
none 0
Status Register 1
message object 15 2
message object 1 3
message object 2 4
message object 3 5
message object 4 6
message object 5 7
message object 6 8
message object 7 9
message object 8 AH
message object 9 BH
message object 10 CH
message object 11 DH
message object 12 EH
message object 13 FH
message object 14 10H
Foi exampIe, a message is ieceived by message object
13 with the IF (ContioI iegistei) and RXIF (message
object 13 ContioI 0 iegistei) bits set. The inteiiupt pin
wiII be puIIed Iow and the vaIue 15 (0FH) wiII be pIaced
in the inteiiupt iegistei.
If the vaIue of iegistei 5FH equaIs 1, then the status
iegistei at Iocation 01H must be iead to update this
inteiiupt iegistei. The status change inteiiupt (SIF bit
in iegistei 00H) has highei piioiity than inteiiupts
fiom message objects. Registei 5FH is automaticaIIy set
to 0 oi to the Iowest vaIue coiiesponding to a mes-
sage with IntPnd set. When the vaIue of this iegistei is
two oi moie, the IntPnd bit of the coiiesponding mes-
sage object contioI iegistei is set.
The 82527 wiII iespond to each status change event
independentIy and wiII not bundIe inteiiupt events in a
singIe inteiiupt signaI. Howevei, if two status change
events occui befoie the fiist is acknowIedged by the
CPU, the next event wiII not geneiate a sepaiate intei-
iupt output. Theiefoie, when seivicing status change
inteiiupts, the usei code shouId check aII usefuI status
bits upon each status change inteiiupt.
Aftei iesetting the INTPND bit in the ContioI 0 Regis-
tei of individuaI message objects, the minimum deIay of
the 82527 iesetting the inteiiupt pin and updating the
Inteiiupt Registei (5FH) is 3 MCLK cycIes and a max-
imum of 14 MCLK cycIes (aftei the CPU wiite opeia-
tion to this iegistei is finished). When a status change
inteiiupt occuis, ieading the Status Registei (01H) wiII
ieset the inteiiupt pin in a maximum of 4 MCLK cy-
cIes
a
145 ns. CIeaiing the INTPND bit of the mes-
sage object wiII de-activate the INT pin.
417 Serial Reset Address (FFH)
FFH
7 6 5 4 3 2 1 0
Serial Reset Address
w
The seiiaI ieset addiess is used to synchionize accesses
between the 82527 and the CPU when the CPU cannot
piovide a chip seIect. The CPU must wiite a stiing of
16 FFH bytes to achieve synchionization.
The defauIt vaIue of the seiiaI ieset addiess aftei a
haidwaie ieset is undefined.
418 82527 Message Objects
The message object is the means of communication be-
tween the host miciocontoIIei and the CAN contioIIei
in the 82527. Message objects aie configuied to tians-
mit oi ieceive messages.
Theie aie 15 message objects Iocated at fixed addiesses
in the 82527. Fach message object staits at a base ad-
diess that is a muItipIe of 16 bytes and uses 15 consecu-
tive bytes. Foi exampIe, message object 1 staits at ad-
diess 10H and ends at addiess 1FH. The iemaining
byte in the 16 byte fieId is used foi othei 82527 func-
tions. In the above exampIe the byte at addiess 1FH is
used foi the cIockout iegistei.
Message object 15 is a ieceive-onIy message object that
uses a IocaI mask caIIed the message 15 mask iegistei.
This mask aIIows a Iaige numbei of infiequent mes-
sages to be ieceived by the 82527. In addition, message
object 15 is buffeied to aIIow the CPU moie time to
ieceive messages.
20
24
82527
Message Object Structure
Base Address
a
0 Control 0
a
1 Control 1
a
2 Arbitration 0
a
3 Arbitration 1
a
4 Arbitration 2
a
5 Arbitration 3
a
6 Mess Conf
a
7 Data 0
a
8 Data 1
a
9 Data 2
a
10 Data 3
a
11 Data 4
a
12 Data 5
a
13 Data 6
a
14 Data 7
419 Control 0 and Control 1
Registers
(Base Address
a
0 Base Address
a
1)
ContioI 0 Registei
7 6 5 4 3 2 1 0
Base Address
a
0
MsgVal TXIE RXIE IntPnd
rw rw rw rw
ContioI 1 Registei
7 6 5 4 3 2 1 0
Base Address
a
1
RmtPnd TxRqst
MsgLst
NewDat
CPUUpd
rw rw rw rw
Fach bit in the ContioI 0 and ContioI 1 bytes occuis
twice, once in tiue foim and once in compIement foim.
This bit iepiesentation makes testing and setting these
bits as efficient as possibIe. The advantage of this bit
iepiesentation is to aIIow wiite access to singIe bits of
the byte, Ieaving the othei bits unchanged without the
need to peifoim a iead/modify/wiite cycIe. The iepie-
sentation of these two bits is desciibed beIow:
MSB LSB Meaning
Write 0 0 Not allowed
(indeterminate)
0 1 reset
1 0 set
1 1 unchanged
Read 0 1 reset
1 0 set
These bit paiis eIiminate the need to execute a iead-
modify-wiite opeiation used to set oi ieset a bit. The
bit paiis aIIow the softwaie to set oi ieset any bit with-
out disiupting the othei bits using a singIe wiite opeia-
tion.
Foi exampIe, a CPU wouId set the TxRqst bit of the
ContioI 1 byte with the foIIowing instiuctions:
LDB Dummy 0EFH load 11101111 into
accumulator
register
STB Dummy CTR1 write 11101111 to
Control 1
setting TXRqst
MsgVal Message VaIid
The MsgVaI bit is an individuaI haIt bit foi
each message object. WhiIe this bit is ieset the
82527 wiII not access this message object foi
any ieason.
one The message object is vaIid.
zeio The message object is invaIid.
The Message VaIid bit is set to indicate the
message object is configuied and is ieady foi
communications tiansactions. This bit may be
ieset at any time if the message is no Iongei
iequiied, oi if the identifiei is being changed.
If a message identifiei is changed, the message
object must be made invaIid fiist, and it is not
necessaiy to ieset the chip foIIowing this mod-
ification. The CPU must ieset the MsgVaI bit
of aII unused messages duiing initiaIization of
the 82527 befoie the Init bit of the ContioI
Registei (00H) is ieset. The contents of mes-
sage objects may be ieconfiguied dynamicaIIy
duiing opeiation and the MsgVaI bit assists
ieconfiguiation in many cases. This bit is wiit-
ten by the CPU.
Two oi moie message objects may not have
the same message identifiei and aIso be vaIid
at the same time.
21
25
82527
TXIE Tiansmit Inteiiupt FnabIe
one An inteiiupt wiII be geneiated aftei a success-
fuI tiansmission of a fiame.
zeio No inteiiupt wiII be geneiated aftei a success-
fuI tiansmission of a fiame.
The Tiansmit Inteiiupt FnabIe bit enabIes the
82527 to initiate an inteiiupt aftei the success-
fuI tiansmission by the coiiesponding message
object. This bit is wiitten by the CPU.
RXIE Receive Inteiiupt FnabIe
one An inteiiupt wiII be geneiated aftei a success-
fuI ieception of a fiame.
zeio No inteiiupt wiII be geneiated aftei a success-
fuI ieception of a fiame.
This bit enabIes the 82527 to initiate an intei-
iupt aftei the successfuI ieception by the coi-
iesponding message object. This bit is wiitten
by the CPU.
NOTE
In oidei foi TXIF oi RXIF to geneiate an inteiiupt,
IF in the ContioI Registei must be set.
IntPnd Inteiiupt Pending
one This message object has geneiated an intei-
iupt.
zeio No inteiiupt was geneiated by this message
object since the Iast time the CPU cIeaied this
bit.
This bit is set by the 82527 foIIowing a suc-
cessfuI tiansmission oi ieception as contioIIed
by the RXIF and TXIF bits. The CPU must
cIeai this bit when seivicing the inteiiupt.
RmtPnd Remote Fiame Pending
one The tiansmission of this message object has
been iequested by a iemote node and is not yet
done.
zeio Theie is no waiting iemote iequest foi the
message object.
This bit is onIy used by message objects with
diiection
e
tiansmit. This bit is set by the
82527 aftei ieceiving a iemote fiame which
matches its message identifiei, taking into ac-
count the gIobaI mask iegistei. The coiie-
sponding message object wiII iespond by
tiansmitting a message, if the CPUUpd bit
e
zeio. FoIIowing this tiansmission, the 82527
wiII cIeai the RmtPnd bit. In othei woids,
when this bit is set it indicates a iemote node
has iequested data and this iequest is stiII
pending because the data has not yet been
tiansmitted.
NOTE
Setting RmtPnd wiII not cause a iemote
fiame to be tiansmitted. The TxRqst bit is
used to send a iemote fiame fiom a ieceive
message object.
TxRqst Tiansmit Request
one The tiansmission of this message object has
been iequested and has not been compIeted.
zeio This message object is not waiting to be tians-
mitted.
This bit is set by the CPU to indicate the mes-
sage object data shouId be tiansmitted.
Conditions iequiied to tiansmit a data fiame:
1) Init bit
e
0
2) MsgVaI bit
e
1
3) diiection
e
tiansmit
4) NewDat bit
e
1
5) TxRqst
e
1
If diiection
e
ieceive, (Init
e
0 and MsgVaI
e
1) then a iemote fiame is sent to iequest a
iemote node to send the coiiesponding data.
TxRqst is aIso set by the 82527 (at the same
time as RmtPnd in message objects whose di-
iection
e
tiansmit) when it ieceives a iemote
fiame fiom anothei node iequesting this data.
This bit is cIeaied by the 82527 aIong with
RmtPnd when the message has been success-
fuIIy tiansmitted, if the NewDat bit has not
been set.
NOTE
Setting TxRqst wiII send a data fiame foi a
tiansmit message object and a iemote fiame
foi a ieceive message object.
MsgLst Message Lost
This definition is onIy vaIid foi message ob-
jects with diiection
e
ieceive. Foi message
objects with diiection
e
tiansmit, the defini-
tion is iepIaced by CPUUpd.
one The 82527 has stoied a new message in this
message object when NewDat was stiII set.
zeio No message was Iost since the Iast time this bit
was ieset by the CPU.
This bit is used to signaI that the 82527 stoied
a new message into this message object when
the NewDat bit was stiII set. Theiefoie, this
bit is set if the CPU did not piocess the con-
tents of this message object since the Iast time
the 82527 set the NewDat bit, this indicates
the Iast message ieceived by this message ob-
ject oveiwiote the pievious message which
was not iead and is Iost.
CPUUpd CPU Updating
OnIy vaIid foi message objects with diiection
e
tiansmit. Foi message objects with diiec-
tion
e
ieceive it is iepIaced by MsgLst.
22
26
82527
one This message object may not be tiansmitted.
zeio This message object may be tiansmitted, if di-
iection
e
tiansmit.
The CPU sets this bit to indicate it is updating
the data contents of the message object and
the message shouId not be tiansmitted untiI
this bit has been ieset. The CPU indicates
message updating has been compIeted by ie-
setting this bit (it is not necessaiy to use the
MsgVaI bit to update the message objects
data contents). The puipose of this bit is to
pievent a iemote fiame fiom tiiggeiing a
tiansmission of invaIid data.
NewDat New Data (This bit has diffeient meanings
foi ieceive and tiansmit message objects.)
one The 82527 oi CPU has wiitten new data into
the data section of this message object.
zeio No new data has been wiitten into the data
section of this message object since the Iast
time this bit was cIeaied by the CPU.
Foi message objects with diiection
e
ieceive,
the 82527 sets this bit whenevei new data has
been wiitten into the message object.
Foi message objects 114 pIease note: When
new data is wiitten into message objects, the
unused data bytes wiII be oveiwiitten with
non-specified vaIues. The CPU shouId cIeai
this bit befoie ieading the ieceived data and
then check if the bit iemained cIeaied when
aII bytes have been iead. If the NewDat bit is
set, the CPU shouId ie-iead the ieceived data
to pievent woiking with a combination of oId
and new data.
Foi message object 15, new data is wiitten
into the shadow iegistei. The foiegiound ieg-
istei is not ovei-wiitten with new data. Foi
message object 15 messages, the data shouId
be iead fiist, the IntPnd ieset, and then the
NewDat and RmtPnd bits aie ieset. Resetting
the NewDat and RmtPnd bits befoie ieset-
ting the IntPnd bit wiII iesuIt in the inteiiupt
Iine iemaining active.
Foi message objects with diiection
e
tians-
mit, the CPU must set this bit to indicate it
has updated the message contents. This is
done at the same time the CPU cIeais the
CPUUpd bit. This wiII ensuie that if the mes-
sage is actuaIIy being tiansmitted duiing the
time the message was being updated by the
CPU, the 82527 wiII not ieset the TxRqst bit.
In this way, the TxRqst bit is ieset onIy aftei
the actuaI data has been tiansfeiied.
Fach bit in the ContioI 0 and ContioI 1 iegis-
teis may be set and ieset by the CPU as ie-
quiied.
The defauIt vaIues of the ContioI 0 and Con-
tioI 1 iegisteis aftei a haidwaie ieset aie un-
changed.
The contioI iegisteis have been configuied
with two bits pei function to aIIow softwaie to
ieduce costIy iead/modify/wiite opeiations.
It is possibIe to modify bits individuaIIy by
using onIy wiite opeiations.
To piogiam a tiansfei iequest, the ContioI 1
iegistei of the message object shouId have the
TxRqst and NewDat bits set to 1. Theie-
foie, this iegistei may be wiitten with the vaI-
ue 066H to initiate a tiansmission.
A iemote fiame may be ieceived, an inteiiupt
fIag set, and no tiansmit sent in iesponse by
configuiing a message object in the foIIowing
mannei. Set the CPUUpd and RXIF bits in
the message object contioI iegistei to 1. Set
the Dii bit in the message configuiation iegis-
tei to 1. A iemote fiame wiII be ieceived by
this message object, the IntPnd bit wiII be set
to 1 and no tiansmit message wiII be sent.
Message Object Priority
If muItipIe message objects aie waiting to tiansmit, the
82527 wiII fiist tiansmit the message fiom the Iowest
numbeied message object, iegaidIess of message identi-
fiei piioiity.
If two message objects aie capabIe of ieceiving the same
message (possibIy due to message fiIteiing stiategies),
the message wiII be ieceived by the Iowest numbeied
message object. Foi exampIe, if aII acceptance mask
bits weie set as dont caie, message object 1 wiII ie-
ceive aII messages.
420 Arbitration 0 1 2 3 Registers
(Base Address
a
2Base Address
a
5)
Arbitration 0 Base
a
2
7 6 5 4 3 2 1 0
Arbitration 1 Base
a
3
Arbitration 2 Base
a
4
23
27
82527
Arbitration 3 Base
a
5
rw rw rw rw rw r
Reserved read as 000
ID0ID28 Message Identifiei
ID0ID28 is the identifiei foi an extended
fiame.
ID18ID28 is the identifiei foi a standaid
fiame.
NOTE
When the 82527 ieceives a message, the entiie mes-
sage identifiei, the data Iength code (DLC) and the
Diiection bit aie stoied into the coiiesponding mes-
sage object.
421 Message Configuration Register
(Base Address
a
6)
Base
a
6
7 6 5 4 3 2 1 0
DLC Dir Xtd Reserved
rw rw rw r
DLC Data Length Code
The vaIid piogiammed vaIues aie 08. The data
Iength code of a message object is wiitten with
the vaIue coiiesponding to the data Iength.
Dir Diiection
one Diiection
e
tiansmit. When TXRqst is set,
the message object wiII be tiansmitted.
zeio Diiection
e
ieceive. When TXRqst is set, a
iemote fiame wiII be tiansmitted. When a
message is ieceived with a matching identifiei,
the message wiII be stoied in the message ob-
ject.
Xtd Fxtended oi standaid identifiei
one This message object wiII use an extended 29-
bit message identifiei.
zeio This message object wiII use a standaid 11-bit
message identifiei.
The defauIt vaIue of the message configuiation
iegistei aftei a haidwaie ieset is unchanged.
If an extended fiame message identifiei is used
(aibitiation bits 017) and the message con-
figuiation iegistei Xtd bit is 0 to specify a
standaid fiame, the 82527 wiII ieset the ex-
tended bits in the aibitiation iegisteis to 0.
An extended ieceive message object (XTD
e
1) wiII not ieceive standaid messages.
If a message object ieceives a message fiom
the bus, the entiie message identifiei wiII be
stoied in the message object. Theiefoie, if ac-
ceptance fiIteiing (masking iegistei) is used,
the masked-off dont caie bits wiII be ie-
wiitten coiiesponding to the message ID of
the incoming message.
422 Data Bytes
(Base Address
a
7Base Address
a
14)
When the 82527 stoies a message aII 8 data bytes wiII
be wiitten into the message object.
The defauIt vaIue of the data bytes 07 aftei a haid-
waie ieset is unchanged. The vaIues of unused data
bytes aie iandom and change duiing opeiation.
423 Special Treatment of Message
Object 15
Message object 15 is a ieceive-onIy message object with
a piogiammabIe IocaI mask caIIed the Message 15
Mask Registei. Since this message object is a ieceive-
onIy message object, the TXRqst bit and the TXIF
have been haidwiied inactive and the CPUUpd bit has
no meaning.
The incoming messages foi message object 15 wiII be
wiitten into a two-message aIteinating buffeis to avoid
the Ioss of a message if a second message is ieceived
befoie the CPU has iead the fiist message. Once mes-
sage object 15 is iead, it is necessaiy to ieset the
NewDat and the RmtPnd bits to aIIow the CPU to iead
the shadow message buffei which wiII ieceive the next
message oi which may aIieady contain a new message.
If two messages have been ieceived by message object
15, the fiist wiII be accessibIe to the CPU. The aIteinate
buffei wiII be oveiwiitten if a subsequent (thiid ieceive)
ieceive message is ieceived. Once again, aftei ieading
message 15, the usei piogiam shouId ieset the IntPnd
bit foIIowed by a ieset of the NewDat and RmtPnd bits
in the ContioI 1 Registei.
The Xtd bit in the message configuiation iegistei detei-
mines whethei a standaid oi an extended fiame wiII be
ieceived by this message object.
24
28
82527
50 PORT REGISTERS
PORT 1 Registers
P1CONF (9FH)
9FH
7 6 5 4 3 2 1 0
P1CONF 07
rw
P1CONF 07
Poit 1 Input/Output Configuiation bits
one Poit pin configuied as a push-puII output.
zeio Poit pin configuied as a high-impedance in-
put.
The defauIt vaIue of the P1CONF iegistei af-
tei a haidwaie ieset is 00H.
P1IN (BFH)
BFH
7 6 5 4 3 2 1 0
P1IN 07
rw
P1IN 07
Poit 1 Data In
one A one (high voItage) is iead fiom the pin.
zeio A zeio (Iow voItage) is iead fiom the pin.
The defauIt vaIue of the P1IN iegistei aftei a
haidwaie ieset is FFH.
P1OUT (DFH)
DFH
7 6 5 4 3 2 1 0
P1OUT 07
rw
P1OUT 07
Poit 1 Data Out
one A IogicaI one (high voItage) is wiitten to the
pin.
zeio A IogicaI zeio (Iow voItage) is wiitten to the
pin.
The defauIt vaIue of the P1OUT iegistei aftei
PORT 2 Registers
P2CONF (AFH)
AFH
7 6 5 4 3 2 1 0
P2CONF 07
rw
P2CONF 07
Poit 2 Input/Output Configuiation bits
one Poit pin configuied as a push-puII output.
zeio Poit pin configuied as a high-impedance in-
put.
The defauIt vaIue of the P2CONF iegistei af-
tei a haidwaie ieset is 00H.
P2IN (CFH)
CFH
7 6 5 4 3 2 1 0
P2IN 07
rw
P2IN 07
Poit 2 Data In
one A one (high voItage) is iead fiom the pin.
zeio A zeio (Iow voItage) is iead fiom the pin.
The defauIt vaIue of the P2IN iegistei aftei a
haidwaie ieset is FFH.
P2 OUT (EFH)
EFH
7 6 5 4 3 2 1 0
P2OUT 07
rw
P2OUT 07
Poit 2 Data Out
one A IogicaI one (high voItage) is wiitten to the
pin.
zeio A IogicaI zeio (Iow voItage) is wiitten to the
pin.
The defauIt vaIue of the P2OUT iegistei aftei
25
29
82527
60 SERIAL RESET ADDRESS (FFH)
FFH
7 6 5 4 3 2 1 0
Serial Reset Address
w
The seiiaI ieset addiess is used to synchionize accesses
between the 82527 and the CPU when the CPU cannot
piovide a chip seIect. The CPU must wiite a stiing of
16 FFH bytes to achieve synchionization.
The defauIt vaIue of the seiiaI ieset addiess aftei a
haidwaie ieset is undefined.
70 PROGRAM FLOWS
The foIIowing fIowchaits desciibe the opeiation of the
82527 and suggested fIows foi the host-CPU.
26
30
82527
71 82527 Handling of Message Objects 114 (Direction
e
Transmit)
These aie the opeiations the 82527 executes to tiansmit messages. This diagiam is usefuI to identify when the 82527
sets bits in the contioI iegisteis.
2724106
27
31
82527
72 82527 Handling of Message Objects 114 (Direction
e
Receive)
These aie the opeiations the 82527 executes to ieceive messages. This diagiam is usefuI to identify when the 82527
sets bits in the contioI iegisteis.
2724107
28
32
82527
73 Host-CPU Handling of Message Object 15 (Direction
e
Receive)
These aie the opeiations the host-CPU executes to ieceive message object 15.
2724108
29
33
82527
74 Host-CPU Handling of Message Objects 114 (Direction
e
Transmit)
These aie the opeiations the host-CPU executes to tiansmit message objects 114.
2724109
30
34
82527
75 Host-CPU Handling of Message Objects 114 (Direction
e
Receive)
These aie the opeiations the host-CPU executes to ieceive message objects 114.
27241010
31
35
82527
80 CPU INTERFACE LOGIC
The CIL (CPU Inteiface Logic) is a fIexibIe inteiface
between the CPU and the 82527 RAM. The CIL aIIows
a diiect seiiaI inteiface oi paiaIIeI inteiface connection
to the 82527 foi most commonIy used CPUs.
The CIL conveits addiess/data/contioI signaIs fiom
the CPU to the inteinaI memoiy bus. The inteinaI
memoiy bus is a 16-bit non-muItipIexed bus that is used
by both the CPU and the CAN ContioIIei to iead and
wiite to the RAM.
CPU Interface Description
Theie aie five CPU inteiface modes used to inteiface a
CPU to the 82527. These incIude foui paiaIIeI inteiface
modes and one seiiaI inteiface mode.
Two mode pins (MODF0, MODF1) seIect one of the
foIIowing paiaIIeI inteiface modes:
Mode1 Mode0 Interface Mode
0 0 Mode 0 8-bit multiplexed
Intel architecture
Intel architecture
non-Intel architecture
1 1 Mode 3 8-bit non-multiplexed
non-Intel architecture
The seiiaI inteiface mode is enteied by seIecting paiaI-
IeI inteiface Mode 0 (MODF0
e
0, MODF1
e
0) and
connecting RD and WR to V
SS
.
The state of MODF0 and MODF1 as weII as RD and
WR aie Iatched on the iising edge of RFSFT. In an
appIication onIy one of the five CPU inteiface modes
may be enteied. Since the CPU inteiface mode is
Iatched on the iising edge of RFSFT it is necessaiy to
entei a haidwaie ieset (RFSFTe
0) in oidei to
change CPU inteiface modes.
Parallel Interfacing Techniques
Mode 0 is intended to inteiface to InteI aichitectuies
(ALF, RD, WR) using an 8-bit muItipIexed
addiess/data bus. A RFADY output is piovided to
foice wait states in the CPU.
Mode 1 is intended to inteiface to InteI aichitectuies
(ALF, RD, WR) using a 16-bit muItipIexed
addiess/data bus. A RFADY output is piovided to
foice wait states in the CPU.
Mode 2 is intended to inteiface to non-InteI aichitec-
tuies (AS, F, R/W) using an 8-bit muItipIexed
addiess/data bus.
Mode 3 is intended to inteiface to non-InteI aichitec-
tuies using an 8-bit non-muItipIexed addiess/data bus.
The asynchionous mode uses R/W, CS, and
DSACK0 (F
e
1). The synchionous mode uses
R/W, CS, and F. Mode 3 uses the addiess/data
bus as the addiess bus and Poit 1 as the data bus.
Foi CPUs which do not piovide a RFADY oi
DSACK0 input and do not meet the addiess/data
bus timing iestiictions, a doubIe iead mechanism must
be used. When wiiting to the 82527 the piogiammei
must ensuie that the time between two consecutive
wiite accesses is not Iess than two memoiy cIock
(MCLK) cycIes. When ieading the 82527, a doubIe
iead is piogiammed. The fiist iead wiII be to the mes-
sage object memoiy addiess and the second iead wiII be
to the High Speed Read iegistei (04H, 05H). Aftei the
fiist CPU iead access, the 82527 stoies the data con-
tents to the High Speed Read iegistei foi the second
iead.
Serial Interface Techniques
The seiiaI inteiface on 82527 is fuIIy compatibIe to the
SPI piotocoI of MotoioIa and wiII inteiface to most
commonIy used seiiaI inteifaces. The seiiaI inteiface is
impIemented in sIave mode onIy, and iesponds to the
mastei using the speciaIIy designed seiiaI inteiface pio-
tocoI. This seiiaI inteiface aIIows an inteiconnection of
seveiaI CPUs and peiipheiaIs on the same ciicuit
boaid.
27241024
32
36
82527
MOSI: Mastei Out SIave In
The MOSI pin is the data output of the mastei
(CPU) device and the data input of the sIave
(82527) device. Data is tiansfeiied seiiaIIy
fiom the mastei to the sIave on the signaI Iine,
with the most significant bit fiist and Ieast sig-
nificant bit Iast.
MISO: Mastei In SIave Out
The MISO pin is the data output of the sIave
(82527) device and the input of the mastei
(CPU) device.
CS: Chip SeIect (used as SIave SeIect foi the SPI
inteiface)
An asseited state on the sIave seIect input
(CS) enabIes the 82527 to accept data on the
MOSI pin. The CS must not toggIe between
each tiansmitted byte. The 82527 wiII onIy
diive data to the seiiaI data iegistei if this pin
is asseited.
SCLK: SeiiaI CIock
The mastei device piovides the seiiaI cIock foi
the sIave device. Data is tiansfeiied synchio-
nousIy to this cIock in both diiections. The
mastei and the sIave devices exchange a data
byte duiing a sequence of eight cIock puIses.
Serial Interface Protocol
The geneiaI foimat of the data exchange fiom the
82527 to the mastei is a bit-foi-bit exchange on each
SCLK cIock puIse. Data is iead on the iising edge of
the SCLK, and is changed on the faIIing edge of SCLK.
Data is aiiianged in the 82527 such that the signifi-
cance of a bit is deteimined by its position fiom the
stait foi output and fiom the end foi input, most signif-
icant bit is sent fiist. The oidei is such that bit exchang-
es in muItipIes of 8 bits and up to 15 bytes of data aie
aIIowed. A maximum of 17 bytes can be sent to the
82527-SPI incIuding one addiess byte, one SPI ContioI
Byte and 15 data bytes.
At the beginning of a tiansmission ovei the seiiaI intei-
face, the fiist byte wiII be the addiess of the 82527 spe-
ciaI function iegistei oi the 82527 RAM to be accessed.
The next byte tiansmitted is a ContioI Byte, which con-
tains the numbei of bytes to be tiansmitted and wheth-
ei this is to be a iead oi wiite access to the 82527. The
fiist two bytes aie foIIowed by the data bytes (1 to 15).
To ensuie the 82527 device is not out of synchioniza-
tion, the 82527 wiII tiansmit the vaIues AAH and
then 55H thiough the MISO pin whiIe the mastei
tiansmits the Addiess and ContioI Byte. This can be
enabIed and disabIed depending on the state of the AD3
pin. This aIIows the mastei to know whethei the 82527
is synchionized.
If the 82527 is out of sync, the mastei SPI device can
ie-sync by tiansmitting a stiing of 16 FFH bytes. When
the SPI ieceives a command byte with the vaIue FFH,
it wiII assume the next byte is an addiess. If it ieceives
an addiess of FFH (the SPI Reset Addiess), it wiII
assume that the next byte is aIso an addiess.
The states of the pins AD0AD3 aie sampIed on the
iising edge of RFSFT. They have the foIIowing func-
tions:
Pin Function
AD0 (ICP) Idle Clock Polarity
zero SCLK is idle low
one SCLK is idle high
AD1 (CP) Clock Phase
zero Data is sampled on the
rising edge of SCLK (ICP
e
0) or data is sampled on the
falling edge of SCLK (ICP
e
1)
one Data sampled on the falling
edge of SCLK (ICP
e
0) or
data is sampled on the
rising edge of SCLK (ICP
e
1)
AD2 (CSAS) Chip select active state
zero Asserted state of CS is
logic low
one Asserted state of CS is
logic high
AD3 (STE) Synchronization Transmission
Enable
Enables the transmission of the
synchronization bytes while the
Address and Control Bytes are
transferred
zero The first two bytes which will
be sent to the CPU after
CS is asserted are 00H
and 00H
one The first two bytes which will
be sent to the CPU after
CS is asserted are AAH
and 55H
33
37
82527
27241011
81 Serial Control Byte
The SeiiaI ContioI Byte is tiansmitted by the CPU to
the 82527 as foIIows:
7 6 5 4 3 2 1 0
Dir 0 0 0 Serial data length code
Dir SeiiaI tiansmission diiection
zeio The data bytes oi SPI Configuiation Registei
wiII be iead, so the 82527 wiII tiansfei infoi-
mation to the CPU.
one The SPI Configuiation Registei oi the data
bytes wiII be sent fiom the CPU to the 82527.
SDLC SeiiaI Data Length Code
The fiist data byte (thiid byte of the SPI pio-
tocoI) wiII be wiitten to oi iead fiom the
82527 addiess (fiist byte of the SPI piotocoI).
Aftei this, the addiess is inciemented by the
SPI Iogic and the next data byte is wiitten oi
iead fiom this addiess. In one data stieam, a
maximum of 15 data bytes can be tiansfeiied.
A DLC of zeio is not aIIowed. Aftei a DLC of
zeio is ieceived, the SPI must be iesynchioniz-
ed.
The seiiaI inteiface is configuied fiom the
states of AD0-AD3 on the iising edge of RF-
SFT.
When the CPU conducts a RFAD, the CPU
sends an addiess byte and a seiiaI ontioI byte.
When the 82527 iesponds back with data, the
82527 ignoies the MOSI pin (tiansmission
fiom the CPU). The CPU may tiansmit an
addiess and seiiaI contioI byte aftei CS is
de-activated and then ie-activated. This means
the chip seIect shouId be activated and de-acti-
vated foi each iead oi wiite tiansmission.
Synchionization bytes must be monitoied
caiefuIIy. Foi exampIe, if the 82527 does not
tiansmit the AAH and 55H synchionization
bytes coiiectIy, then the pievious tiansmission
may be incoiiect too.
The MISO pin is tii-stated if CS is inactive.
82527 SPI Interface Schematic
27241032
34
38
82527
90 82527 FRAME TYPES
The 82527 communications contioIIei suppoits foui
diffeient fiame types:
- data fiame
- iemote fiame
- eiioi fiame
- oveiIoad fiame
91 Data Frame
A data fiame is composed of seven diffeient fieIds:
- stait bit
- aibitiation fieId
- contioI (identifiei) fieId
- data fieId
- CRC fieId
- acknowIedge fieId
- end of fiame
The foIIowing desciibes the standaid and extended
message foimats foi data and iemote fiames shown
above.
SOF: Stait Of Fiame (dominant bit) maiks the
beginning of a data/iemote fiame.
Aibitiation: One oi two fieIds which contain the mes-
sage identifiei bits. The standaid foimat
has one 11-bit fieId and the extended foi-
mat has two fieIds, 11- and 18-bits wide.
RTR: Remote Tiansmission Request bit is
dominant foi data fiames and iecessive
foi iemote fiames. This bit is in the aibi-
tiation fieId.
SRR: Substitute Remote Request bit is used in
extended messages and is iecessive. This
bit is a substitute foi the RTR bit in the
standaid foimat. This bit is in the aibitia-
tion fieId of the extended foimat.
IDF: Identifiei Fxtension bit is dominant foi
standaid foimat and iecessive foi extend-
ed foimat. This bit is in the aibitiation
fieId of the extended foimat and in the
contioI fieId of the standaid foimat.
ContioI Reseived bits i0 and i1 aie sent as domi-
FieId: nant bits. The 4-bit Data Length Code
(DLC) indicates the numbei of bytes in
the data fieId.
Data FieId: The data bytes aie Iocated in the data
fiame (08 bytes). A iemote fiame con-
tains zeio data bytes.
CRC FieId: This fieId is composed of a 15-bit CycIicaI
Redundancy Code eiioi code and a ieces-
sive CRC deIimitei bit.
ACK FieId: AcknowIedge is a dominant bit sent by
nodes ieceiving the data/iemote fiame
and is foIIowed by a iecessive ACK deI-
imitei bit.
Fnd of Seven iecessive bits ending the fiame.
Fiame:
INT: Inteimission is the thiee iecessive bits
which sepaiate data and iemote fiames.
The minimum message Iengths of standaid and extend-
ed message foimats aie summaiized foi data and ie-
mote fiames. The actuaI Iengths of these messages may
diffei because stuff bits aie added to the message.
Stuff bits assist synchionization by adding tiansitions
to the message. A stuff bit is inseited in the bit stieam
aftei five consecutive-equaI vaIue bits aie tiansmitted,
the stuff bit is the opposite poIaiity of the five consecu-
tive bits. AII message fieIds aie stuffed except the CRC
deIimitei, the ACK fieId and the Fnd of Fiame.
Standard Format
27241012
35
39
82527
Extended Format
27241013
CAN Message Formats
Standard Format
Message Field Number of Bits
SOF 1
Arbitration (ID) 11
RTR 1
IDE 1
r0 1
DLC 4
Data Field 064
CRC Field 16
ACK Field 2
End of Frame 7
Total 44108 bits
Extended Format
Message Field Number of Bits
SOF 1
Arbiration (ID) 11
SRR 1
IDE 1
Arbitration (ID) 18
RTR 1
r1 1
r0 1
DLC 4
Data Field 064
CRC Field 16
ACK Field 2
End of Frame 7
Total 64128 bits
92 Remote Frame
A data fiame is composed of six diffeient fieIds:
- stait bit
- aibitiation fieId
- contioI (identifiei) fieId
- data fieId
- CRC fieId
- acknowIedge fieId
- end of fiame
Contiaiy to the Data Fiame, the RTR-bit of the Re-
mote Fiame is iecessive and no data segment is
tiansmitted independent of the Data Length Code set
by the Desciiptoi of the coiiesponding Communication
Object.
The RTR-bit aIIows Remote Tiansmission Requests
fiom any node to the system. This piovides the capabiI-
ity to iequest infoimation in addition to the standaid
bioadcast chaiacteiistics. It aIso suppoits poweifuI di-
agnostic capabiIity by being abIe to deteimine if the
piimaiy tiansmittei (data souice) of a specific paiame-
tei(s) is on the bus and functionaI.
93 Error Frame
The Fiioi Fiame contains a sequence of vaiiabIe Iength
dominant bits as a iesuIt of eiioi fIags being tiansmit-
ted by diffeient system-nodes. This is an impoitant as-
pect of the 82527 communication piotocoI with iegaids
to data consistency within a communication netwoik.
The eiioi fiame is foIIowed by an eiioi deIimitei.
27241014
Figure 1 Error Frame Format
ERROR FLAG consists of six consecutive dominant
bits. Since this vioIates bit stuffing iuIes, it is used as
an eiioi indicatoi to the system (see Coding/Decod-
ing).
36
40
82527
An Fiioi FIag is tiansmitted if an 82527 opeiates as an
eiioi active node and has detected an eiioi condition
duiing oi aftei a message tiansfei. If an Fiioi FIag is
geneiated by a tiansmittei, oi a ieceivei, aII othei
nodes inteipiet the Fiioi FIag as a bit stuffing iuIe
vioIation. As a consequence, they, in tuin, tiansmit an
eiioi fIag. A vaiiabIe sequence of dominant bits iesuIt
fiom the supeiposition of the diffeient Fiioi FIags
tiansmitted by individuaI nodes. The totaI Iength of the
Fiioi FIag sequence vaiies between six bits minimum
to tweIve bits maximum.
An eiioi condition is signaIed by the tiansmission of
six iecessive bits whiIe in the eiioi passive opeiation
mode. This way an eiioi passive node with a tempoiaiy
IocaI ieceivei piobIem wiII not destioy messages ie-
ceived coiiectIy by othei nodes. The iecessive bits may
be oveiwiitten by an Fiioi FIag geneiated by one oi
moie eiioi active system nodes, but the eiioi passive
82527 waits foi at Ieast six bits of equaI poIaiity befoie
enteiing into the next inteinaI ieceive oi tiansmit
mode. (See Fiioi HandIing foi eiioi active/passive
mode.)
NOTE
The 82527 wiII not peifoim stoiage of a message (pos-
itive acceptance fiIteiing) into the communication
buffei, if ieception of the message was foIIowed by an
Fiioi FIag on the seiiaI bus.
The eiioi-deIimitei consists of eight iecessive bits gen-
eiated by the 82527 aftei the end of an Fiioi FIag on
the seiiaI bus Iine. This is monitoied by detection of a
tiansition fiom the dominant to iecessive bit IeveI.
Detected eiiois duiing the tiansmission of a data oi
iemote fiame can be signaIed within the tiansmission
time of the iespective fiame. This pioceduie associates
an Fiioi FIag to the coiiesponding fiame, and initiates
a ietiansmission of the fiame. As the 82527 monitois,
any deviation of its eiioi fiame wiII stait ietiansmitting
an eiioi fiame. If this occuis seveiaI times in a se-
quence the 82527 wiII become eiioi passive.
94 Overload Frame
The oveiIoad fiame consists of two bit fieIds, the ovei-
Ioad fIag and the oveiIoad deIimitei.
Theie aie two cases of oveiIoad conditions which iesuIt
in the tiansmission of an oveiIoad fIag:
1. InteinaI conditions of the ieceivei ciicuitiy of a
CAN chip which iequiie a deIay time befoie ieceiv-
ing the next fiame (ieceivei not ieady). The 82527
wiII not geneiate oveiIoad fiames when CAN bus
tiansmission iates aie 1 Mbit/sec oi Iess.
2. Detection of a dominant bit duiing Inteifiame
Space.
The oveiIoad fiame consists of six dominant bits that
coiiespond to the Fiioi FIag and destioy the fixed
foim of the Inteifiame Space FieId. As a consequence,
aII othei nodes see the dominant bit duiing the Intei-
fiame Space time and inteipiet the iecessive to domi-
nant edge as a stait of fiame and tiansmit an oveiIoad
fIag because of the oveiIoad condition.
The oveiIoad deIimitei consists of seven iecessive bits
geneiated by the CAN chip.
Aftei tiansmission of an oveiIoad fiame, each 82527
within the system monitois the bus Iine untiI a tian-
sition fiom a dominant to a iecessive IeveI occuis. This
indicates to each 82527 the end of oveiIoad fiames and
each node simuItaneousIy staits the tiansmission of six
moie iecessive bits.
NOTE
The eaiIiest time an oveiIoad fiame can be tiansmitted
is at the fiist bit time of the Inteifiame Space FieId.
This is contiaiy to the Fiioi Fiame and aIIows the
82527 to diffeientiate between the Fiioi Fiame and
OveiIoad Fiame.
27241015
Figure 2 Overload Frame Format
37
41
82527
Interframe-Space
Data Fiame and Remote Fiame aie sepaiated fiom
pieceding fiames by an Inteifiame Space consisting of
the Inteimission bit fieId and a possibIe Bus IdIe time.
An eiioi fiame is not pieceded by an Inteifiame Space.
27241016
Figure 3 Interframe Space Format
INTERMISSION consists of thiee iecessive bits. Dui-
ing Inteimission time the 82527 wiII not stait tiansmis-
sion of a fiame. Inteimission is a fixed time peiiod foi
the 82527 to execute inteinaI piocesses piioi to the next
ieceive oi tiansmit task.
Data ieceived within a data fiame wiII be stoied in the
communication buffei and the contioI bits aie updated
if no eiioi condition has occuiied thiough the Iast bit
of the end of fiame fieId.
The bus idIe time may be of aibitiaiy Iength. Aftei the
Inteifiame Space peiiod, the 82527 Iooks foi bus idIe
befoie initiating tiansmission, if iequested by a CPU.
The detection of a dominant bit aftei Inteimission oi
bus idIe is inteipieted by the 82527 as Stait of Fiame.
95 CodingDecoding
Coding
The fiame segments (stait of fiame, aibitiation fieId,
contioI fieId, data fieId and CRC sequence) aie coded
using bit stuffing. Whenevei the tiansmit Iogic of the
82527 detects five consecutive bits of identicaI IeveIs to
be tiansmitted, the Iogic inseits a compIement bit in the
tiansmitted bit stieam.
Bit stuffing is used to guaiantee enough edges in the
NRZ Bit Stieam to maintain synchionization.
Decoding
Whenevei the 82527 has ieceived five identicaI consec-
utive bit IeveIs in the ieceived bit stieam the Iogic auto-
maticaIIy deIetes the next bit fiom the data stieam (de-
stuffing). Some fieId foimats do not use bit stuffing. In
these cases the bit stuffing and destuffing Iogic is tuined
off.
96 Arbitration
In the case when two oi moie 82527s stait tiansmission
concuiientIy, the bus access confIict is soIved by a bit-
wise aibitiation method duiing tiansmission of the ai-
bitiation fieId.
The tiansmit Iogic compaies the bit IeveI tiansmitted to
the IeveI monitoied on the seiiaI bus. Both the tians-
mittei and ieceivei aie on the bus at the same time. The
tiansmit Iogic stops message tiansfei if a iecessive bit
was sent but a dominant bit was monitoied. This meth-
od guaiantees tiansmission of the message with the
highest piioiity even if theie is a coIIision duiing the
aibitiation fieId of one oi moie message Identifiei(s).
The 82527 piotocoI aichitectuie iequiies each message
used in the communication netwoik to have a unique
Identifiei chaiacteiizing the type of data within the
data fieId. Using this method, the Identifiei assigns a
name to the data fiame and automaticaIIy impIies the
piioiity of the message.
As a iesuIt, the Identifiei duiing bus access iepiesents
not onIy the message name but, moie impoitant, the
piioiity of each specific message. Since the most signifi-
cant bit (MSB) of an Identifiei is tiansmitted fiist, the
Identifiei with the smaIIest digitaI vaIue has the highest
piioiity foi bus access.
An Identifiei shouId not be used foi moie than one
specific message to ensuie that two oi moie nodes nev-
ei simuItaneousIy stait a tiansmission of a data fiame
with the same message piioiity. FoIIowing this iuIe, bus
access confIicts aie iesoIved duiing the tiansmission of
the Identifiei.
One exception wouId be the simuItaneous tiansmittei
and ieceivei initiated fiame tiansfei foi the same mes-
sage. If one 82527 geneiates a iequest foi actuaI data of
a ceitain type by tiansmitting a iemote fiame and
simuItaneousIy, the 82527 iesponsibIe foi this type of
data staits the tiansmission, aibitiation can not be
soIved by the Identifiei itseIf and actuaIIy is not ie-
quiied.
To deaI with this exception, the RTR-bit is incIuded in
the aibitiation fieId. The RTR-bit of the tiansmittei is
aIways set dominant and, theiefoie, has a highei piioii-
ty than the iequesting 82527 (RTR-bit iecessive). This
way the iemote fiame iequest by the ieceivei gets an
immediate iesponse by the tiansmittei.
38
42
82527
FxampIe: Non-Destiuctive piioiitized bitwise aibitia-
tion
27241017
NOTES
Node 1 wins the arbitration with the lowest identifier
(0B1H)
Zero is the dominant bit on the bus
Node detected the loss of the arbitration and stopped
transmitting but continues to receive the message
The CAN piotocoI aichitectuie defines that each Com-
munication Object used must have a unique Identifiei
chaiacteiizing the piioiity of the message. This aIIows
bitwise aibitiation of the bus if a confIict aiises. The
tiansmit Iogic compaies the IeveI monitoied on the seii-
aI bus with that tiansmitted. The tiansmit Iogic imme-
diateIy stops tiansmission if theie is a confIict. This
guaiantees the data tiansfei of the Communication Ob-
ject with the highest piioiity even if theie is a coIIision.
100 ERROR DETECTION AND
CONFINEMENT
The Fiioi Detection mechanism is impIemented in
haidwaie foi efficiency.
101 Bit Error
Duiing a tiansmit opeiation, the 82527 monitois the
bus on a bit-by-bit basis. If the bit IeveI monitoied is
diffeient fiom the tiansmitted bit, a bit eiioi is sig-
naIed.
Fxceptions: Aibitiation and ACK-SLOT. Duiing aibi-
tiation, a iecessive bit can be oveiwiitten by a domi-
nant bit. In this case, the 82527 inteipiets a bit eiioi as
an aibitiation Ioss. Duiing the ACK-SLOT, a tiansmit-
tei may detect a faIsified bit (iecessive to dominant)
meaning that at Ieast one ieceivei has ieceived the mes-
sage coiiectIy.
NOTE
Fxcept duiing tiansmission of the aibitiation fieId and
duiing the time window of the ACK-SLOT, aII gIobaI
and IocaI eiiois at the tiansmittei aie detected.
102 Bit Stuffing Error
As desciibed eaiIiei, the fiame segments aie coded by a
method of bit stuffing.
Theie aie two possibiIities wheie bit stuffing eiiois may
occui:
1. A distuibance geneiates moie consecutive bits of
equaI IeveI than aIIowed by the iuIe of bit stuffing.
These eiiois aie detected by aII nodes.
2. A distuibance faIsifies one oi moie of the five bits
pieceeding the stuff bit. This eiioi is not iecognized
by a ieceivei, howevei, if the eiioi aIso appeais at
the tiansmittei, it wiII be detected as a bit eiioi
(tiansmittei monitois bus as it tiansmits).
In any case, the eiioi is detected by a ieceivei eithei by
the bit stuffing mechanism (the stuff bit of the tiansmit-
tei is not diopped but taken as an infoimation bit) oi
by the CRC check.
103 CRC Error
To ensuie the vaIidity of a tiansmitted message, aII ie-
ceiveis peifoim a CRC check. In addition to the infoi-
mation bits, the CRC incIudes contioI bits used foi ei-
ioi detection.
Description of the CRC Code
The code used foi the 82527 is a (shoitened) BCH
Code, extended by a paiity check and the foIIowing
attiibutes:
- 127 bits as maximum Iength of the code woid
- Iength of the CRC sequence is 15 bits
- Hamming distance d
e
6
d
e
min A (x FXOR y) / x, y diffeient code woids
A(x)
e
numbei of iecessive bits in the code
woid x
f(x) e (x
14 a x
9 a x
8 a x
6 a x
5 a x
4 a x
2 a x a 1) (x a 1)
f(x) e 1100 0101 1001 1001
f(x) e C599 Hex
Buist eiiois aie detected up to a Iength of 15 (degiee of
f(x)). MuItipIe eiiois (numbei of distuibed bits at Ieast
d
e
6) aie not detected with a iesiduaI eiioi piobabiIity
of 3
c
10
b5
.
104 Form Error
Foim Fiiois iesuIt fiom the vioIation of the fixed foim
of the foIIowing bit fieIds:
- end of fiame
- inteifiame space
39
43
82527
- ACK deIimitei
- CRC deIimitei
Duiing the tiansmission of these bit fieIds, an eiioi
condition is iecognized if a dominant bit IeveI is de-
tected.
105 Error Detection Capabilities
OIobaI eiiois, which occui at aII fuIIy functionaI nodes,
aie 100% detectabIe.
Foi IocaI eiiois, e.g. eiiois which may appeai at some
nodes onIy, the shoitened BCH Code extended by the
paiity check has the foIIowing eiioi detection capabiIi-
ties:
- Up to 5 singIe bit eiiois aie detected 100% even if
those eiiois aie being distiibuted iandomIy within
the code woid.
- AII singIe bit eiiois aie detected if theii totaI num-
bei within the code woid is odd.
- The iesiduaI eiioi piobabiIity of the CRC check is
2
b15 e
3
c
10
b5
. As an eiioi may be detected by
the CRC check, and/oi by additionaI impIemented
eiioi detection mechanism, the iesiduaI eiioi piob-
abiIity is significantIy Iess than 3
c
10
b5
.
106 Error Confinement
Fiioi Confinement is impIemented on the 82527 as a
seIf-checking mechanism foi distinguishing tempoiaiy
eiiois fiom peimanent faiIuies. A peimanent faiI-
uie is noted when an aveiage of one in eight messages is
coiiupted. This type of eiioi condition can be caused
by a defective connectoi, tiansmittei, ieceivei oi a Iong
Iasting distuibance fiom outside the netwoik. If the
node continues to obseive a faiIuie ovei a peiiod of
time the node wiII be iemoved fiom the bus. A discon-
nected node is not pIaced again on the seiiaI bus untiI
the CPU has issued a softwaie ieset to the 82527, and
an 82527 inteinaI deIay time has eIapsed.
The impIementation of the eiioi confinement consists
of two counteis (RFCFIVF-FRROR-COUNT and
TRANSMIT-FRROR-COUNT) and some contioI Iog-
ic. These counteis aie modified accoiding to a numbei
of iuIes, which may be consideied as the coie of the
eiioi confinement. If a message is tiansmitted oi ie-
ceived without an eiioi the eiioi-countei is deciement-
ed by a fixed numbei, if it is not aIieady 0. The eiioi-
countei is incieased by a fixed numbei, if an eiioi is
detected on the seiiaI bus. No access is piovided to the
FRROR-COUNTFRS, howevei, two fIags aie piovid-
ed (Fiioi Status and Bus Status) as a summaiy of eiioi
events.
The count added to the eiioi-countei depends on the
type of the eiioi detected. Foi instance, whenevei a
node detects and iepoits an eiioi condition (eiioi fIag),
aII system nodes wiII aIso detect an eiioi condition due
to that eiioi fIag, even if the infoimation up to that
time was ieceived eiioi-fiee.
NOTE
In case an eiioi condition is not detected by aII nodes
at the exact same bit time, the node iepoiting the ei-
ioi fiist is moie IikeIy to be iesponsibIe foi such an
eiioi condition compaied to those nodes ieacting to
the eiioi fIag. Theiefoie, a node that is often iesponsi-
bIe foi eiioi conditions, as mentioned above, is the oi-
igin of the eiioi as a iesuIt of a defect.
In geneiaI, a defective node exchanges infoimation foi
a shoit time so as to pievent it fiom Ioading the bus and
sIowing down othei nodes on the bus.
Thiee eiioi states aie fIagged in the STATUS-
RFOISTFR as foIIows:
An 82527 in the busoff state wiII neithei tiansmit noi
ieceive messages. In oidei to iestait the 82527 it is
necessaiy to ieset the init bit in the contioI iegistei
(00H).
NOTE
Aftei this sequence, the CAN node wiII be active on
the seiiaI bus aftei 128 x 11 consecutive iecessive bits.
107 82527 States with Respect to the
Serial Bus
The 82527 may be in one of the thiee foIIowing states:
- Fiioi Active
- Fiioi Passive
- Bus Off
Fiioi-Active is the noimaI mode of opeiation, it is
chaiacteiized by the 82527 tiansmitting an FRROR-
FLAO of 6 dominant bits in case a ieceive oi a tians-
mit eiioi is detected.
An Fiioi Passive 82527 does not send an ACTIVF
FRROR FLAO (6 dominant bits). In this mode, the
82527 communicates on the bus but on detecting a ie-
ceive oi a tiansmit eiioi, it sends a PASSIVF FRROR
FRAMF (6 iecessive bits). Aftei tiansmitting a mes-
sage, an Fiioi Passive 82527 does not initiate anoth-
ei tiansmission immediateIy, instead, aftei the INTFR-
FRAMF SPACF, it tiansmits 7 iecessive bits. If
duiing this time peiiod (7 iecessive bits), anothei 82527
staits tiansmission on the bus, the eiioi passive
82527 becomes the ieceivei.
40
44
82527
A busoff 82527 does not tiansmit oi ieceive any infoi-
mation, its output diiveis aie put in a fIoat state. This
state is indicated to the usei by the BOff bit in the
Status Registei (01H).
Foi Fiioi Confinement two eiioi counteis aie impIe-
mented in the 82527 aichitectuie:
1. TRANSMIT AND RFCFIVF FRROR COUNTFR
These counteis aie modified by the 82527 with no iead
oi wiite access to the usei.
At the system stait-up, theie may be onIy one 82527
active on the bus. If this node tiansmits a message, it
wiII not get an acknowIedgement and hence detect an
eiioi, it wiII coiiespondingIy iepeat the message. Be-
cause of iepeated tiansmissions, 82527 wiII become
Fiioi Passive but not busoff.
SimiIaiIy, an 82527 sending a wake-up message may
become Fiioi Passive.
110 SAMPLE PROGRAM
The foIIowing pages contain a softwaie piogiam wiit-
ten foi the InteI 87C196KR miciocontioIIei which is
used in the InteI FV82527 FvaIuation Kit foi the 82527
chip. This code may seive as a guide to configuie the
82527. This code configuies a tiansmit, ieceive, and
iemote messages. Inteiiupts aie used to ieceive mes-
sages. The piogiam uses Poits 1 and 2 extensiveIy to
iead dip switches and the contioI an LFD dispIay. Foi
iIIustiative puiposes, the dip switch contioI featuies aie
shown beIow and these functions aie aII impIemented in
the foIIowing code.
The DIP Switch Definitions:
27241018
Switch 1
0 standaid foimat message objects (11-bit ID)
1 extended foimat message objects (29-bit ID)
Switch 2
0 dispIay tiansmitted data
1 dispIay ieceived data
Switch 34
0 0 ieceive message on ID 0 (switch 8
e
0) oi ID
2048 (switch 8
e
1)
e
0) oi ID
2049 (switch 8
e
1)
e
0) oi ID
2050 (switch 8
e
1)
e
0) oi ID
2051 (switch 8
e
1)
Switch 56
0 0 tiansmit message on ID 0 (switch 8
e
0) oi ID
2048 (switch 8
e
1)
e
0) oi ID
2049 (switch 8
e
1)
e
0) oi ID
2050 (switch 8
e
1)
e
0) oi ID
2051 (switch 8
e
1)
Switch 7
0 ieceive message using ieceive message object
1 send iemote message fiom ieceive message object
Switch 8
0 tiansmit sIow countei vaIues
1 tiansmit vaIue cuiientIy on DIP switches
41
45
82527
27241025
42
46
82527
27241026
43
47
82527
27241027
44
48
82527
27241028
45
49
82527
27241029
46
50
82527
27241030
47
51
82527
27241031
48
52

82527

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