Static Random Access Memory

( )

CONTENTS

1. Introduction of SRAM 2. SRAM Cell and Basic Core Operation 3. SRAM Chip Architecture 4. High Speed SRAM Circuit Technique

1. Introduction of Static Random Access Memory

1-1. Basic Architecture and AC/DC Characteristics 1-1-1. Functional Block Diagram of Standard SRAM
Clk Gen. A1 A2 A3 . . . . . An I/O1 . . I/Oi Pre-Charge Circuit

Row Decoder

MEMORY ARRAY 2 n Rows 2m Columns

Vdd Vss

Write Driver

I/O Circuit Column Decoder

Clk Gen. An+1 An+2 . . . . An+m

/CS /WE /OE

1-1-2. Typical Read Cycle Timing

tRC Address tAA tCO /CS t LZ tOHZ tOE /OE tOLZ Data Out High-Z Data Valid tOH t HZ

Example of 1Mb SRAM

KM68V1002-12 Parameter Symbol Min Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Output Enable to Low -Z Output Chip Enable to Low -Z Output Output Disable to High-Z Output Chip Disable to High-Z Output Output Hold from Address Change tRC tAA tCO tOE tOLZ tLZ tOHZ tHZ tOH 12 0 3 0 0 3 Max 12 12 6 6 6 Min 15 0 3 0 0 3 Max 15 15 7 7 7 Min 20 0 3 0 0 3 Max 20 20 8 8 8 ns ns ns ns ns ns ns ns ns KM68V1002-15 KM68V1002-20 Unit

(From SAMSUNG SRAM Databook 1996)

1-1-3. Typical Write Cycle Timing

tWC Address tAW /OE tCW /CS t WR

tAS /WE

t WP

tDW High-Z Data In tWHZ Data Out High-Z Data Valid tOW

tDH

Example of 1Mb SRAM

KM68V1002-12 Parameter Symbol Min Read Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low -Z tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW 12 8 0 8 12 0 0 6 0 3 Max 6 Min 15 10 0 10 15 0 0 7 0 3 Max 7 Min 20 12 0 12 20 0 0 8 0 3 Max 9 ns ns ns ns ns ns ns ns ns ns KM68V1002-15 KM68V1002-20 Unit

(From SAMSUNG SRAM Databook 1996)

1-1-4. DC and Operating Characteristics

Example of 1Mb SRAM DC Power

Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC Test Conditions VIN=Vss to Vcc /CS=VIH or /OE=VIH or /WE=VIL VOUT=VSS to Vcc Min. Cycle, 100% Duty /CS=VIL, VIN=VIH or VIL, IOUT=0mA Standby Current ISB ISB1 Output Low Voltage Output High Voltage VOL VOH Min. Cycle, /CS=VIH f=0MHz, IOL=8mA IOH = - 4mA /CS Vcc -0.2V, Normal L-ver. VIN Vcc -0.2V or VIN 0.2V 2.4 20 10 0.1 0.4 mA mA V V 200 mA Min -2 -2 Max 2 2 Unit uA uA

(TA= 0 to 70 0 Vcc=3.3V 0.3V) C,

(From SAMSUNG SRAM Databook 1996)

1-2. SRAM Features 1-2-1. Low Power SRAM

= Low Power Supply Voltage : 5V -> 3V -> 1.8V -> sub 1.0V -> Low Power Dissipation for Handheld Application = Low Standby Power Dissipation : 100uA -> 10uA -> 1uA -> support for Data Retention Application = Small Size Package : sTSOP, CSP(uBGA, FPBGA), MCP -> reduce the package area for Handheld Application

Data Retention Mode

Transition Timing to Battery
set-up Vdd 3.0V 2.2V VDR /CS GND /CS Vdd-0.2V Recovery Data Retention Mode

Battery Back-Up System

Main Power Supply Voltage

to SRAM Power Supply Voltage Battery Back-Up Voltage C L

1-2-2. FAST SRAM

= Power Supply Voltage : 5V, 3.3V -> JEDEC standard power supply voltage = Low Operating Power Dissipation -> Application for large amount of SRAM usage = FAST Speed requirements : 8ns-20ns

1-2-3. Synchronous SRAM

= Low Power Supply Voltage : 3.3V -> 2.5V -> 1.8V -> Small geometry Transistor technology to improve speed = Various Sync. SRAM Features : LW(Late Write), DLW(Deep Late Write), DDR(Double Data Rate) -> Late Write operation to enhance the bus efficiency = High Bandwidth Interface : LVTTL -> LVCMOS -> HSTL = FAST Speed Requirements : 150MHz-over 500MHz(1Gbps) = High Performance Package Solution : TQFP, BGA, FCBGA

Various Sync. SRAM Features

Standard Write (Register-Register/Pipe Line) tCYC
CLK

ADDRESS

RA1 Q1
Read

WA2 D2
Write

A3 Q3

DQx

Standard Write (Register-Latch/Flow Through) tCYC

CLK

ADDRESS

RA1 Q1
Read

WA2 D2
Write

A3 Q3

DQx

Late Write (Register-Register/Pipe Line)

tCYC
CLK ADDRESS

RA1 Q1
tCD
Read

WA2

RA3 D2 Q3
Read

WA4

DQx

Write

Late Write (Register-Latch/Flow Through) tCYC

CLK ADDRESS

RA1

WA2 Q1
tCD
Read Write

RA3 D2
Read

WA4 Q3
Write

DQx

D4

Deep Late Write (Register-Register/Pipe Line)

tCYC
CLK ADDRESS

A1

A2 Q1
Read

A3

A4 D2
Read

DQx

Q3
Write

D4

tCD=5ns
Write

Double Data Rate (Register-Register/Pipe Line)

1X CLK 2X Data Rate ADDR.
RD1 WR2 RD3

DQ (Burst)

Q11

Q12

Q13

Q14

D21

D22

D23

D24

Q31

Q32

Q33

Q34

Read

Write

Read

High Bandwidth Interface Voltage

5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0

5V Interface

3.3V Interface

2.2V

2.5V Interface
2.0V

Min. 1.4V Swing

0.8V

Min. 1.2V Swing

0.8V

1.7V

Min. 1.0V Swing

0.7V

1.5V Interface
0.85~1.1V Min. 0.2V Swing 0.65~0.9V

TTL

LVTTL

LVCMOS

HSTL
(V REF =0.75~1.0V)

1-3. SRAM cell Technology

= Low cost, High Density Commodity SRAM for Small Microprocessor controlled system . Change from NMOS Cell to Mix-MOS Cell = Low Standby power for Battery Back-Up and Battery Operated System . Change from Mix-MOS Cell to TFT(Thin Film Transistor) or Full CMOS Cell

= FAST speed for Cache SRAM . Change from NMOS Cell to Mix-MOS or Full CMOS Cell

1-3-1. History of SRAM memory cells PMOS Enhancement Load Cell

- Substituting Bipolar SRAM Cell . High device yield and low cost . Low standby power dissipation as compared with the bipolar SRAM cell - Use diffusion process to make MOS transistor in mid of 1960s . Limitation of the low power supply voltage due to increase Vtp

-Vdd Y X X Y
. 64 bit Array . SiO2 120nm . Vdd = -18V . 150 - 200ns ( From Joseph H. Friedrich [1], Fairchild 1968 )

Data Line

Data Line

NMOS Enhancement Load Cell

- Substituting PMOS Load SRAM Cell . Meet sub 100ns speed - Use high doping substrate or substrate bias in end of 1960s . High stand-by power dissipation . Limitation of small cell size

Vdd X X
. 144 bit Array . Vdd = 12V . 40ns write cycle

Bit Line

Bit Line

( From Yasuo Tarui. et al., [2] NEC 1969)

NMOS Depletion Load Cell

- Substituting NMOS Enhancement Load SRAM Cell . Fully static with no dynamic or bootstrapped node . Low voltage operation (5V supply voltage) due to the low threshold voltage - Use ion implantation process . High stand-by power dissipation . Limitation of small cell size

Bit Line

Bit Line

. 1K bit Array . SiO2 120nm . Vdd = 5V . 150ns ( From R.M. Jecmen. et al.,
[3]

Intel 1974)

High-Resistivity Poly Load Cell (Mix-MOS)

- Substituting NMOS Load SRAM Cell . Cost effective chip size . Low stand-by dissipation - Negative Temperature Coefficient Resistance: Isb = I0 exp (-Ea/KT) . Compensate the temperature dependence of the junction leakage current and the subthreshold current - Have been used 16Kb SARM to 1Mb SRAM since end of 1970s . Limitation of low stand-by power dissipation for high density SRAM . Limitation of low power supply voltage (less 2.5V) operation - High density limitation [4] . SLOW : 4Mb (with 1uA stand-by current) . FAST : 4Gb (minimum 4mA stand-by current)
Arsenic Implanted region Length CVD SIO2

SIO2

Bit Line

Bit Line

Polysilicion Resistor

TFT (Thin Film Transistor) Load Cell

- Compatible cell size as compared with poly load cell - Low stand-by power dissipation with retaining data retention voltage - Improved SER (Soft Error Rate) - Using high density SRAM (4Mb SRAM) since end of 1980s . Complicated process . Limitation of low power supply voltage (less 3.0V) operation

Bit Line

Bit Line

TFT Gate
P+ P+

TFT Gate Gate N+ P-WELL

TFT Channel

P+

P+

TFT Channel

Gate N+ N+ P-WELL N+

Bottom Gate TFT

Top Gate TFT

Full CMOS Cell

- Ultra low stand-by power dissipation with good data retention characteristics - Good stability for wide noise margin . Less 2.0V low power supply voltage operation - Good SER (Soft Error Rate) Characteristics - Future SRAM Technology for Low Vdd/Ultra High speed product - Limitation of small cell size . Mainly used internal cache of MPU

Bit Line

Bit Line

1-3-2. Comparison of layout of load devices in SRAM memory cells

NMOS and Mix-MOS SRAM cell

Depletion mode Load

Single polysilicon Cell

Double polysilicon Cell

- Cell size reduction . scaling from 3um CMOS to 2um CMOS . adding the second level of polysilicon for the stacked load resistor [5]

Full CMOS SRAM cell

Single aluminum interconnect

Double aluminum interconnect

- Cell size reduction . adding the second level of metal for the local interconnection [6]

1-4. SRAM Technology for Peripheral Circuits

= MOS SRAMs are the fastest MOS memories. = Bipolar SRAMs are the fastest of all memories.

1-4-1. Bipolar
- Application for ultra high speed SRAM . Cache and Main Memory in high performance mainframe computers . ECL interface - High cost and High power dissipation

1-4-2. NMOS
- Lower cost than Bipolar - Limitation of high density and high performance due to complicated circuit design . need dynamic circuit and bootstrapped circuit technique - Limitation of low power dissipation and high speed

1-4-3. CMOS
- Low cost and low power dissipation - Easy to make high density SRAM - Limitation of high speed . improve the MOS Transistor . use Dynamic Gate Logic

1-4-4. BiCMOS
- High speed . application for small volume/high performance - Complicated process [7][8] . use triple diffused BiCMOS process - Limitation of low power supply voltage [9] . improve the MOS Transistor (Lower Vth) . use BiNMOS or NBiCMOS . Base boost technique

Propagation Delay with Process Technology

(From H.G. Byun et al. [10], Samsung 1995)

tPD (ps/stage) 500 C=1pF CMOS L 450 Temp=25 AMOS CMOS 400 BiCMOS 350 3D-BiCMOS 300 250 BiCMOS 200 150 1.5 2 2.5 3 3.5 4 4.5 5 5.5 Power Supply Voltage Vdd(V)

tPD (ps/stage)

800 700 600 500 400 300 200 100 0 0

CMOS Vdd=3.3V Temp=25 AMOS BiCMOS

CMOS 3D-BiCMOS BiCMOS

Laod capacitance CL(pF)

Propagation Delay with Inverter Logic

(From H.G. Byun et al. [10], Samsung 1995)

CMOS

BiCMOS tPD (ps/stage)

BiNMOS

NBiCMOS

C=1pF L2 Temp=25

Power Supply Voltage Vdd(V)

2. SRAM Cell and Basic Core Operation

2-1. SRAM Cell Operation 2-1-1 Chip Power-Down Mode (Stand-By)
Vdd X
R H

Isb
L

X
H L

Off

ON

Bit Line

Bit Line

Bit Line

Off

Bit Line

- One inverter is always ON for the Poly Laod or NMOS Load cells when in the standby mode. . Current(Isb) is drawn from Vdd - In the Full-CMOS cell, one transistor in each of the coupled inverters is OFF. . Only junction leakage current is drawn from Vdd

2-1-2. Data Retention

Vdd X
Vbl Isp Ij Isd R

Ion
Vnh

R Vnl

Bit Line

Bit Line

- Data Retention Voltage (Vdr) . Min. power supply voltage to retain high node data in the standby mode. - a prerequisite of Data Retention Ion [= (Vdd - Vnh) / R] > Isp + Isd + Ij
Where Ion = Charge Current Isp = Sbthreshold current of Pass Transistor @ VDS=Vnh-Vbl, Vgs=0V Isd = Sbthreshold current of Pull-down Transistor @ VDS=Vnh, Vgs=Vnl Ij = Junction leakage for high node @ Vnh

Data Retention Margin

10 -8 A 10 -13 A 10 -13 A ? ? ? ?

ON

Off

10 -13 A

Off
10 -15 A

Off

Off
10 -15 A

Off

Bit Line

Off

ON

Bit Line

Bit Line

Off

ON

Bit Line

High Resistive Poly Load Cell

TFT (Thin Film Transistor) Load Cell

No of Cells

Marginal

No of Cells

Large Margin

10 5

10 10

10 5

10 10

Charge Current / Leakage Current

Charge Current / Leakage Current

(From T.Y.OOTAMI. et al. [11], Toshiba 1990)

2-2. Read/Write Operation

Word Line

BL

/BL

BL

/BL

POLY LOAD CELL

FULL CMOS CELL

DATA BUS /DATA BUS

Column Select

To Sense Amplifier and Data Input Buffer

Column Select

Read/Write Margin Analysis

WL BL
L L

/BL
A B B A Iread

RM (Read Margin) Trip Point WM (Write Margin) /BL

Iwrite E

WL

2-2-1. Poly Load Cell Read/Write Operation

WL

Read Operating Region

BITLINE VOLTAGE

D:A TP A:B D:E Write Operating Region

A B B

A Iread

Iwrite E

TP: MEMORY CELL TRIP VOLTAGE

2-2-2. Full CMOS Cell Read/Write Operation

WL

Read Operating Region

BITLINE VOLTAGE

D:A TP C:A:B

C A B

C A B Iread

(D // C+A) : E Write Operating Region

Iwrite E

TP: MEMORY CELL TRIP VOLTAGE

2-3. SRAM Cell Stability 2-3-1 Static-Noise Margin (SNM) What is the Static-Noise margin (SNM)?
WL Vn + -

+ Vn BL

/BL

Vn : Static Noise Source

SNM : Maximum Value of Vn

Static-Noise margin (SNM) for Poly Load Cell

(From E. Seevink. et al. [12], 1987)

Assumption
Vdd

- Q1, Q2, Q3 : Saturation Region - Q4 : Linear Region

R a Q1 + I D1 I D3 ? d Q3 d Q4 Vn - + Vn ? I D4 R Q2 a I D2

MOS Models
- Id = 1/2 (Vgs - Vth) 2 Saturation Region - Id = Vds (Vgs - Vth - 1/2 Vds) Linear Region where = W/L eff Cox .

Analytic Expressions Results

- Kirchhoff Current Equation Id1 = Id3 , Id2 = Id4 - Kirchhoff Voltage Equation Vgs3 = Vn + Vds4 Vgs1 = Vdd - Vn - Vgs4 Vgs2 = Vdd - Vds4 SNM (Vn(MAX)) = 3/2 1 - 2 + + 1 - 1 + Vth + ( + 1) + 1 (Vdd - Vth)

d a where (Cell Ratio) = /

Saturated Enhancement Load Inverter

Vout

Vdd

Vdd
1 Subthreshold Region : sharply Drop to Vdd - Vth (with Body Effect)

Voh
R Vout I D1 I D3 Vin

2 Driver Saturated

3 Driver Nonsaturated

Vol Vin Vth Vdd

SNM of Poly Load Cell

static noise margin SNM [mV]

600 500 400 300 200 100 0

SNM with Supply voltage(From E. Seevink. et al. Theory Equation Simulation (Simple Model) Simulation (Extended Model)

[12],

1987)

DC Transfer Characteristics

Ratio = 3.5

(Source : IEEE Journal of Solid -State Circuits 1987)

Supply Voltage [V]

700
static noise margin SNM [mV]

SNM with Cell ratio (From E. Seevink. et al. Theory Equation Simulation (Simple Model) Simulation (Extended Model)

[12],

1987)

600 500 400 300 200 100

Vdd = 5V

- Good correlation between theory equation and simple model 0 - Slope difference for the extended model simulation 0 --> caused by omitted short channel effect from the simple model

(Source : IEEE Journal of Solid -State Circuits 1987)

Ratio

Static-Noise margin (SNM) for Full CMOS Cell

Assumption
- Q2, Q3 : Saturation Region - Q4, Q5 : Linear Region

(From E. Seevink. et al. [12], 1987)

Vdd

p a I D5 Q1 + ? Q2 - + Vn ? I D4 a I D2

Vn

MOS Models
- Id = 1/2 (Vgs - Vth) 2 Saturation Region - Id = Vds (Vgs - Vth - 1/2 Vds) Linear Region where = W/L eff Cox . SNM (Vn(MAX)) Results = Vth -

I D3

d Q3

d Q4

1 (k + 1)

Vdd -

2 1 +

Analytic Expressions
- Kirchhoff Current Equation Id3 = Id5 , Id2 = Id4 - Kirchhoff Voltage Equation Vgs3 = Vn + Vds4 Vgs5 = Vdd - Vn - Vds4 Vds5 = Vdd - Vn - Vgs4 Vgs2 = Vdd - Vds4 -

1 +

Vth

1 + k ( ) +1

Vdd - 2Vth ] 1 + k q + (1 + 2k + k 2 q ) q

q = /a p d where (Cell Ratio) = /a + 1 ( k = Vs - Vth - 1) k = +1 +1 + 1 - Vs2 / Vr2 Vs = Vdd - Vth

Saturated Enhancement Load Inverter

Vout
1 NMOS Saturated PMOS Nonsaturated

Vdd

Vdd

Voh
Vout I D1 I D3 Vin

2 NMOS Nonsaturated PMOS Saturated

Vol Vin Vth Vdd

SNM with Supply voltage(From E. Seevink. et al.

700 600 500 400 300 200 100 00

[12],

1987)

static noise margin SNM [mV]

SNM of Full CMOS Cell

Ratio = 2

DC Transfer Characteristics

Ratio = 1

Theory Equation Simulation (Simple Model) Simulation (Extended Model)

(Source : IEEE Journal of Solid -State Circuits 1987)

Supply Voltage [V]

SNM with Cell ratio (From E. Seevink. et al.

900

[12],

1987)

static noise margin SNM [mV]

800

Vdd = 5V
700

Vdd = 3V
600

500 Theory Equation Simulation (Simple Model) 400 Simulation (Extended Model) (Source : IEEE Journal of Solid -State Circuits 1987) 0 1 2 3 4 5 6

- Good correlation between theory equation and simulation --> Short channel effect is compensated by the PMOS transistor. - Optimum SNM can be obtained through proper choice of ratio (r and q) for Vdd.

300

Ratio

Static-Noise Source (Vn) - DC Disturbance . Layout Pattern Offset . Process mismatches : Non-uniformity of ion-implantation or Gate oxide thickness etc. - Dynamic Disturbance . Alpha( ) Particles . Crosstalk . Voltage supply ripple . Thermal noise Memory cell Asymetry
Vy Half Cell transfer curves SNM

A+

x
B-

y
B+

A-

Vx

2-3-2. Dynamic-Noise Margin (DNM) (From Barbara Chappel. et al.

[13],

1985)

WL

Assumptions
L L ?

Q1 Q3

Q2 Q4

- Q2, Q3 : Weaker Device . High Threshold Voltage . Longer channel Length . Narrow channel width
/BL

BL

- BL and /BL are precharged to Vdd

Region 4
Cell swtches state

Region 3
Some refresh of stored high

Region 2
Some discharging of stored high

Region 1
No change in stored high

Change in Voltage

Initial Stored High Voltage

(1) Region 1 - The device on the high node of the cell (Q3) did not conduct during the read. (2) Region 2 - Current through Q3 caused some discharging of the stored high during the read - the voltage on the low node ??having increased enough to turn Q3 momentarily while the large precharged bitline capacitance was being discharged. (3) Region 3 - The current through Q3 more than compensated the discharge current through Q1. (4) Region 4 - The cell switches to the opposite state because the devices have been mismatched.

2-4. SRAM Cell Speed and Power

D D

WL 1
L L

A B B

dt = [ Ctot / Iread ] dV

WL 2
L H L L

Where dt is read speed for core(bit line and data bus line) operation.
A

A B

Ctot is capacitance load fixed by SRAM density. Iread is cell current fixed by pass gate size (A) dV is voltage swing fixed by ratio (D : A) CBL

B Iread

CBL
E E

CDB

CDB

2-5. Memory Cell Alpha Particle Sensitivity

Vdd Vdd

BL

Load

IL(on)
B

/BL

WL A

delta V = Ccell Qalpha

Ground Ground

Qalpha / Ccell

To improve SER immunity

- Decreasing Q alpha [14] . Polyimid coating (blocks alphas) . Adopting a p-well structure is useful in reducing the collection efficiency . The area ratio of n+ storage region(A and B) to the other n+ region(Vdd and Ground., etc) has to be small to reduce the collection efficiency . The two individual storage nodes(A and B) are placed closely. - Decreasing Charging Time of the High Storage Node [15] . use DWL(Divided Word Line) architecture to increase average interval time ( ti ) . use TFT(Thin Film Transistor) Load or Full CMOS cell to decrease Charging time ( tch ) - Balance the Load characteristics to improve the stability - Increasing cell capacitance and cell stability (Cell size issue)

3. SRAM Chip Architecture

3-1. High Density SRAM Array 3-1-1. Problems
Example of 64K SRAM Architecture
Bit Line Precharge memory cell 10um x 10um Power Dissipation for Read operation : 256 Column @ 100uA/Column = 25.6mA Word Line Speed : Resistance (R) 256 x10um/1um x 5 Ohm/ = 12.8 Kohm : Capacitance (C) 2 x 256 Gates @ 2fF = 1.024 pF RC Delay = 13.1ns Bit Line Speed : Capacitance (C) 256 cells x 3.9fF/cell = 1 pF : Bit Line Slew Rate (dV/dt=Iread/CBL) = 100mV/ns 2ns for 200mV swing
Where Iread = 100uA/Column Poly1(for Word Line) Resistance 5 Ohm/ Line Width 1um capacitance 2fF/gate Bit Line Capacitance (C BL ) 3.9 fF/cell

Row Decoder Address

256 x 256 Memory Array

Column Decoder Sense Amplifier

I/O Circuitry

3-1-2. Divided Word Line & Bit Line Architecture

Example of 64K SRAM Architecture

Power Dissipation for Read operation : 64 Column @ 100uA/Column = 6.4mA Word Line Speed : Resistance (R) 64 x10um/1um x 5 Ohm/ = 3.2 Kohm : Capacitance (C) 2 x 64 Gates @ 2fF = 0.256 pF RC Delay = 0.8ns Bit Line Speed : Capacitance (C) 128 cells x 3.9fF/cell = 0.5 pF : Bit Line Slew Rate (dV/dt=Iread/CBL) = 200mV/ns 1ns for 200mV swing
Where Iread = 100uA/Column Poly1(for Word Line) Resistance 5 Ohm/ Line Width 1um capacitance 2fF/gate Bit Line Capacitance (C BL ) 3.9 fF/cell

BL Pre

BL Pre BL Pre

BL Pre

Row Decoder

Row Decoder Row Decoder

64 x 128

64 x 128

Column Decoder Sense Amplifier Column Decoder Row Decoder

64 x 128

64 x 128

64 x 256

64 x 128

BL Pre

BL Pre BL Pre

BL Pre

Address

I/O Circuitry

64 x 128

64 x 128

3-2. Chip Architecture for High Density SRAM 3-2-1. Divided word line (DWL) structure [16]

Simplified schematic concept of DWL

Performance enhancement on 64K RAM

3-2-2 Shared word-line and hierarchical word-line structure [17]

Shared word-line structure for a 72K SRAM

3-2-3 Divided bit-line structure[18]

Block diagrams of shorten the bit-lines

3-2-4. Variable Impedance Bitline Loads[19]

Ai

/WE

P2(/WE)

Word Line
Bit Line

P2(WE) Word Line

SAT BL CELL /BL /SAS

DB /DB SAT

4. High Speed SRAM Circuit Technique

4-1. Address transition detection (ATD) for improved speed[20]

ATD - Address transition Detection

Ai

SAT
Ai

AiD

SPi Delay
AiD

SPi
Aj

Aj

AjD

Delay

AjD

SPj

SPj

SAT

ATD - How it is used Bit Line Shorter

SAT SAT BL CELL /BL /SAS

Sense Amp. Shorter

SAS

Data Line Shorter

DB /DB SAT

WORDLINE SAT BIT LINE DATA BUS SENSE AMP

4-2. Fast sense amplifier

- Determine the sense amplifier scheme[21] . Current mirror amplifier with high CMRR(Common -mode rejection ratio) . Current multiplier with high driving capability - Determine the number of stage

Data Sensing Scheme

CLASICAL FULL DIFFERENTIAL

Biased Linear (Resistive)

CURRENT MIRRIOR SINGLE ENDED

(W/L)p1 (W/L)p2

Vref V0+ ViV0Vi+ Vref Vi+

(W/L)n1 (W/L)n2

Current Mirror (High Gain)

V0+ ViConstant Current (Biased Saturation)

Constant Current (Biased Saturation)

Vref

Current Mirrior:

(W/L)n2 (W/L)n1 (W/L)n2 =

(W/L)p2 (W/L)p1 (W/L)p2 (W/L)p1

= 1

Current Multiplier: (W/L)n1 =

= N>1

Speed vs. Gain - How many stages?

CASE 1: 1 Stage - A = 16

150mV
SLEW RATE = 150mV/ns

INPUT
8ns

OUTPUT

2.4V

SLEW RATE = 150mV/ns

CASE 2: 4 Stage - A = 2 150mV

SLEW RATE = 150mV/ns

INPUT
1ns
SLEW RATE = 150mV/ns

1ns
SLEW RATE = 300mV/ns

1ns

SLEW RATE = 600mV/ns

1ns

OUTPUT

2.4V

4ns

SLEW RATE = 1.2V/ns

4-3. Dynamic circuitry[22]

weak keeper Qs Qr N C Qf

IN
Precharge

IN
Qs Qf Qf Precharge

Out
N
Dynamic State Dynamic State

Out

- Separate pull-up and pull-down operation during transition time. - Lower the loading on output driver. - Decrease the switching logic threshold.

Basic Dynamic gate

IN

(From T. Chappell et al. [23], 1991)

OUT

Qs IN Qf Qf

Qr 2

Qf Qs Qr

Qs Qf

Qr OUT

Qs: Slow Keeper Transistor Qf: Fast Transistor for Enable Path Qr: Reset Transistor for Self-Resetting Reset Timing Chain

IN 1 2 Out

4-4. Fast datapath (From Sasaki, K. et al.

[24],

1988)

- Reduce the address decoder delay using PMOS load decoders and Divided wordline Architecture - Short bit-line & Data Bus using 90 rotated architecture
o

Address Decoder

PMOS load decoder

CMOS load decoder

trade-off in current and cycle time

Short bit-lines Architecture

traditional orientation of word-lins and bit-lines

(From Kohno, Y et al. [25], 1988)

layout at 90 o to traditional orientation intended to shorten the bit-lines

(From Sasaki, K. et al. [24], 1988)

4-5. Interface Circuit Technique

- Reduce the impedance variation with temperature and voltage

Impedance Controlled Output Driver Scheme

VDDQ R1 VZQ ZQPAD ZQ COMPARATOR EXT. RZQ UP/DOWN
ZQ COUNTER

(From Pilo, H. et al. [26], 1996)

ZQ DRIVER

VDDQ VDDQ R1 REF NMOS ARRAY ZQ DETECTOR (*From Cell Array) DLAT DLATB DOUT BUFFER DODx NMOS ARRAY DOUx UP MOS ARRAY DQ

Off Chip Driver

References
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