CONFIGURABLE DIRECT-CONVERSION / SUPERHETERODYNE

BASEBAND DOWN-LINK CHANNEL FOR W-CDMA APPLICATIONS

Paolo Cusinato
Texas Instruments France
821 Avenue Jack Kilby 06270 Villeneuve Loubet - France
p-cusinato@ti.com
ABSTRACT
A configurable W-CDMA Baseband Down-Link (BDL)
channel suitable to be used with both direct conversion
(DIR) and superheterodyne (SHT) architectures has been
integrated in a double-poly 0.6m CMOS technology.
The BDL is an analog signal processor consisting of
calibrated active-RC filters and oversampled 6-bit analog-to-
digital pipeline converters, which sufficiently suppresses the
adjacent channel and other interferers before digital signal-
processing on an external DSP.
The designed BDL channel achieves 38.4dB SNDR, 43dB
SFDR in DIR mode and 38.3dB SNDR, 42.8dB SFDR in
SHT mode with an overall power consumption of only
49mW/58mW (DIR/SHT) from a single 2.8V power supply.
A low power consumption mode allows to further reduce
these values down to 41mW/50mW (DIR/SHT) without
significant detrimental effects to BDL performance.
1. INTRODUCTION
A Baseband Down-Link (BDL) channel, integrated in an
analog baseband codec suitable for W-CDMA applications,
is presented. The BDL architecture can be configured to
work with both superheterodyne architectures (SHT) with no
baseband filtering in the RF IC and direct conversion
architectures (DIR) having all the baseband filtering already
in the RF IC. The BDL channel (Fig.1) is fully-differential
(to increase the immunity to interference and suppress even-
order distortion) and consists of analog signal-processing
circuitry, including internally calibrated active-RC filters and
oversampled pipeline Analog-to-Digital Converters (ADCs).
Figure 1. BDL channel
The programmable active-RC Butterworth filters perform the
channel selection filtering and fit the input dynamic range of
the ADCs, which are 6-bit 1.5bit/stage pipeline structures
with digital error correction and interstage gain. The offset
cancellation systems, controlled by dedicated digital Finite
State Machines (FSM) and based on voltage-scaling 8-bit
Digital-to-Analog Converters (DAC), allow to reduce the
channel offset down to 0.25LSBs of the downlink resolution.
2. CHANNEL FILTERING
The channel selection filtering is performed in the analog
domain in order to use high-speed but only medium
resolution ADCs. If channel selection is performed in the
digital domain, high-resolution ADCs are required, which
leads to large power consumption and large die size. The
former approach is thus preferable since power consumption
is a key concern in battery operated products (in particular
for W-CDMA applications). The channel filter, which is
composed of cascaded 3
rd
-order and 1
st
-order active-RC
Butterworth structures, can be configured for the two
operation modes: SHT and DIR.
Figure 2. 3
rd
-order Butterworth filter
In the SHT mode, the filtering requirements are fulfilled by a
3
rd
-order Butterworth filter with cut-off frequency at
1.92MHz (Fig.2). An 18dB DC-gain is distributed in the
filter to suppress the ADC quantization noise and to fit its
input dynamic range (2.05V
pp
). The measured integrated
input-referred noise in SHT mode is 180V
RMS
. The in-band
group-delay is 121ns with a group-delay deviation of 50ns.
In the DIR mode, the 3
rd
-order Butterworth filter is bypassed
and sent off in order to save power, and only a simple 1
st
-
order smoothing filter with a cut-off frequency of 7.68MHz
I +
calibration
DIR / SHT
RC
RC RC
RC
R
1
R
1
R
2
R
2
R
3
R
3 CC
R
4
R
4
CC
CC
CC
CC
CC
Calibration
5 bit
CC
FSM
DAC
6-bit
8-bit
ADC
3-rd
order
1-st
order
1-st
order
6-bit
8-bit
ADC
order
3-rd
I -
Q -
Q +
DAC
DAC
FSM
FSM
FILTER
IN+
IN- OUT-
OUT+
Q-OUT
I-OUT
R1=16.8k
RC=26.6k
R2=26.6k
R3=5.3k
I - 741 0-7803-8251-X/04/$17.00 2004 IEEE ISCAS 2004
Authorized licensed use limited to: TEXAS INSTRUMENTS VIRTUAL LIBRARY. Downloaded on March 8, 2009 at 16:22 from IEEE Xplore. Restrictions apply.
(F
S
/2, where F
S
is the channel master clock) is present in
front of the ADC. The programmable DC-gain of this filter
can be set to 0dB or 5.8dB depending on the full-scale (FS)
of the input signal (2.05V
pp
/1.05V
pp
).
The advantages of the active-RC technique in filters design
are the insensitivity to parasitics, the excellent linearity and
the large dynamic range. The main drawback of this
approach are the large variations in the absolute value of the
filter time constants, which can typically vary over a range of
50% from nominal values in CMOS technologies [1]. Thus,
a calibration system becomes necessary to restore the
nominal frequency response. This has been achieved by
replacing the filters capacitors by binary weighted
capacitors arrays (Fig.2), which can be programmed by a 5-
bit digital code generated on-chip by a FSM implementing a
novel algorithm, which allows to restore the nominal
frequency to 3% accuracy in less than 5s covering the
whole RC-product variation range (patent pending).
The opamp used in both the filters is a two-stage Miller-
compensated structure with NMOS input stage and NMOS
output stage and has a nominal GBW of 80MHz and a DC-
gain of 73dB. Its current consumption is close to 530A.
3. ADC
The A/D conversion of the I/Q components is performed by
means of two 6-bit 1.5-bit/stage pipeline ADCs with digital
error correction and interstage gain.
Since the input signal bandwidth is 1.92MHz and the
sampling frequency is 15.36MHz, each ADC works with an
oversampling factor of 4. Thus, the ideal SNR (limited only
by quantization noise) becomes:
SNR = (n + 1) 6.02 + 1.76 [dB] n = 6-bit
Figure 3. 6-bit 1.5/stage pipeline ADC
A low resolution per stage has been chosen because it allows
to achieve a high sample rate with low power consumption
[2], and in order to maximize the correction range of the
digital error correction system up to V
ref
/4, where V
ref
(1.025V) is the reference voltage which defines the input
dynamic range of the ADC. The main drawback of this
choice is the contribution of the later stages to the overall
noise of the ADC, due to the reduced interstage gain, which
reduces the allowable down-scaling of the capacitor values
along the architecture to save area and power consumption.
Thus, the capacitor values of the five pipeline stages are only
slightly scaled (0.4pF in the first two stages and 0.2pF in the
following three), but this is a minor issue since the low
resolution of the ADC allows the use of small capacitor
values, as dictated by kT/C thermal-noise considerations.
A continuous-time stage of a pipeline architecture consists of
a sample-and-hold (SAH) stage, a 2-bit flash ADC (FADC),
a 2-bit DAC (FDAC), a subtractor and an amplifier. By
using switched-capacitor techniques, a single circuit, referred
to as the Multiplying DAC (MDAC), can be realized to
implement the functions not only of the SAH and FADC, but
also of the subtractor and amplifier. Fig.3 shows the block
diagram of the pipeline ADC and of the MDAC. In such a
configuration, the major power dissipation component is the
opamp.
The opamp used in each stage to amplify the residue is a
folded cascode with 75dB DC-gain, a phase margin of 53deg
and a GBW close to 210MHz. Each opamp is autozeroed
during the sampling phase (SP, s) by connecting it in a
unity-gain feedback configuration.
Figure 4. I
VDD
k
vs. time with LPM
The ADC uses in default mode a standard current bias but a
Low-Power consumption Mode (LPM), which biases the
ADC differently during the sampling and integration (IP, i)
phases, can be enabled [3]. With the LPM, the bias current of
each opamp is reduced during the SP by approximately 45%.
Consequently, the bandwidth of the opamp is reduced down
to 100MHz during this phase. Thus, the current consumption
(I
VDD
k
, k=1,2,,5) of each opamp, which is 1.1mA (I
MAX
)
during IP, becomes 600A (I
MIN
) during SP, thus giving an
average value per period of 850A (I
AVG
) (Fig.4). By using
the LPM, an overall power consumption reduction close to
20% is achieved in the ADC (from 18mW down to 14mW)
without significant detrimental effects to the overall
linearity.
In order to increase the linearity of the ADC, constant-v
gs
boosted switches have been used at the input of each pipeline
stage (Fig.5). Since the opamps are autozeroed, the capacitor
C
C
is precharged to V
DD
when the switches (M1, M2) are off
(
i
); switches gate-voltages become (V
IN
+V
DD
) when they
1-st
stage
5-th
stage
Flash
ADC
BIAS
Digital Error Correction
In +
In -
2 bit 2 bit 1 bit
ADC
2b flash
00
01
10
Vin +
Vin -
Vin -
Vin +
+
+ -
-
Vout -
Vout +
s
s
i
i
s
s
10 00
10 00
Vref + Vref -
Vref - Vref +
Cs Cf
Cf Cs
6 bit
boosted
switch
MDAC
I
MAX
I
MIN
I
AVG
IP IP SP SP
I
VDD
k
Int / Sampl
Phase
01
I - 742
Authorized licensed use limited to: TEXAS INSTRUMENTS VIRTUAL LIBRARY. Downloaded on March 8, 2009 at 16:22 from IEEE Xplore. Restrictions apply.
get on (s) [4]. Therefore, the v
gs
of M1 and M2 is always
close to V
DD
(and independent of the input signal) when the
switches are on, thus maximizing the linearity of the stage.
Dynamic comparators without pre-amplification have been
used in the FADC to avoid DC power consumption (Fig.6).
Since even a small imbalance in load capacitors (Ca, Cb)
may cause large equivalent input offsets, balanced loads
were assured by means of a symmetrical layout and by
adding a differential latch close to the outputs of the
comparator [2]. The residual offset, mainly caused by the
mismatch in the input NMOS transistors M1-M4 (to the
order of a few tens of mV [5]), can be tolerated thanks to the
digital error correction circuit of the ADC.
Figure 5. Input boosted switches
Figure 6. Dynamic comparator
4. DC OFFSET CANCELLATION
The resolution of the on-chip DC offset cancellation is
limited at the start-up to 6-bit (effective resolution of the
channel) since the offsets of the I and Q paths are evaluated
by using the output digital codes of the ADCs. The on-chip
offset cancellation time is 4.5s. However, 8-bit resolution
offset cancellation may be achieved during the normal
operation, if the baseband codec is used with the complete
W-CDMA chipset it is designed to work with. This is
achieved by using an external calibration loop (Fig.1), where
the I and Q 8-bit offset cancellation codes, elaborated by the
companion Digital Baseband IC, are fed to the BDL via its
serial interface. The BDL channel offset cancellation is
performed by using two fully-differential 8-bit DACs based
on voltage-scaling architectures. The digital codes
corresponding to the detected offsets are converted to the
analog domain by the 8-bit DACs and added to the processed
I and Q analog signals before the 1
st
-order smoothing filter
stage.
5. EXPERIMENTAL RESULTS
The BDL channel has been integrated in a double-poly
0.6m CMOS technology with three metal layers.
Fig.7 shows the performance of the BDL I-channel in DIR
mode (input signal at -1dB with f
IN
=1MHz) using the
standard bias. The power consumption of the BDL channel (I
and Q paths) in this configuration is 49mW.
0 2 4 6 8 10 12 14 16
x 10
6
100
90
80
70
60
50
40
30
20
10
0
Figure 7. Output spectrum of the BDL I-channel for a 1dB input
signal at 1MHz (DIR mode, standard bias)
0 2 4 6 8 10 12 14 16
x 10
6
100
90
80
70
60
50
40
30
20
10
0
Figure 8. Output spectrum of the BDL I-channel for a 19dB input
signal at 1MHz (SHT, LPM)
Fig.8 shows the performance of the same channel using the
SHT mode (input signal at -19dB with f
IN
=1MHz) when the
LPM is enabled to save power in the I/Q ADCs. In this case,
the overall power consumption raises to 50mW since the 3
rd
-
order Butterworth filter is enabled.
It is worth noting that the linearity of the BDL channel is
only slightly influenced by the operation mode (SHT/DIR).
Output spectrum [dB]
Frequency [Hz]
SNDR = 38.4dB
SNR = 39.7dB
SFDR = 43dB
SNDR = 38.1dB
SNR = 39.7dB
SFDR = 40dB

i
i

s

s

C
CC

C
Frequency [Hz]
Output spectrum [dB]
1
2
A
B
A
B
Ca
Cb
Ca = Cb
Vin + Vin - Vref - Vref +
s s
M1 M2 M3 M4
I - 743
Authorized licensed use limited to: TEXAS INSTRUMENTS VIRTUAL LIBRARY. Downloaded on March 8, 2009 at 16:22 from IEEE Xplore. Restrictions apply.
Fig.9 shows the output spectrum of the BDL Q-channel for a
25dB input signal at low frequency (f
IN
=100kHz) using the
SHT mode (with LPM enabled).
The measured in-band I/Q gain mismatch is 0.2dB.
0 2 4 6 8 10 12 14 16
x 10
6
100
90
80
70
60
50
40
30
20
10
0
Figure 9. Output spectrum of the BDL Q-channel for a 25dB
input signal at 100kHz (SHT, LPM)
Features and performance measurements of the BDL channel
(I and Q paths) are summarized in table 1.
Features Performance
Operation mode SHT DIR
Input signal band 1.92MHz
Input res / cap 20k / 3pF
Channel master clock 15.36MHz
Input amplitude 1.05 / 2.05V
pp
1.05V
pp
ampl. 23.8dB 5.8dB Channel
gain 2.05V
pp
ampl. 18dB 0dB
Filter order 3
rd
-order 1
st
-order
Cut-off frequency 1.92MHz 7.68MHz
Input referred noise 180V
RMS
DC offset accuracy 0.25LSB
38.3dB 38.4dB SNDR (standard bias)
SNDR (LPM) [f
IN
=1MHz] 38.1dB 38.2dB
39.7dB 39.7dB SNR (standard bias)
SNR (LPM) [f
IN
=1MHz] 39.7dB 39.7dB
42.8dB 43dB SFDR (standard bias)
SFDR (LPM) [f
IN
=1MHz] 40dB 40.1dB
I/Q gain mismatch 0.2dB
BDL area / complexity 8.3mm
2
/ 7e3 MOS
Power supply 2.8V
Normal 58mW 49mW Power
dissipation LPM 50mW 41mW
Technology double-poly 0.6m CMOS
Table 1. Features and performance
6. CONCLUSIONS
A BDL channel for a W-CDMA DIR / SHT baseband codec
(Fig.10) has been implemented.
Programmable active-RC filters allow to configure the BDL
for both architectures. Two 6-bit pipeline ADCs digitize the
pre-processed W-CDMA I and Q signals. Two 8-bit DAC-
based offset cancellation systems allow to detect and cancel
both the channel offset and the BDL input offset (output
offset of the RF counterpart). The BDL channel achieves
38.3dB SNDR, 42.8dB SFDR (38.1dB SNDR, 40dB SFDR
when LPM is enabled) in SHT mode and 38.4dB SNDR,
43dB SFDR (38.2dB SNDR, 40.1dB SFDR when LPM is
enabled) in DIR mode.
Figure 10. Chip microphotograph
The power consumption (I and Q paths) is 49mW/58mW
(DIR/SHT) from a 2.8V power supply. It can be reduced
down to 41mW/50mW by enabling the LPM mode. The area
is 3.22.6mm
2
in a 0.6m CMOS technology.
7. REFERENCES
[1] J.Hughes, N.Bird and R.Soin, A Novel Digitally Self-Tuned
Continuous-Time Filter Technique, Digest of 1986 IEEE
International Symposium on Circuits and Systems, pp.1177-
1180.
[2] T.B.Cho and P.R.Gray, A 10b, 20Msample/s, 35mW pipeline
A/D converter, IEEE Journal of Solid-State Circuits, vol.SC-
30, pp.166-172, Mar. 1995.
[3] P.Cusinato, F.Stefani, and A.Baschirotto, Reducing the Power
Consumption in High-Speed Bandpass Modulators, IEEE
Trans. on Circuits and Systems-II, vol.48, no.10, pp.952-960,
Oct. 2001.
[4] M.Dessouky and A.Kaiser, Very Low-Voltage Digital-Audio
Modulator with 88-dB Dynamic Range Using Local Switch
Bootstrapping, IEEE Journal of Solid-State Circuits, vol.36,
no.3, pp.349-355, March 2001.
[5] P.Cusinato, M.Bruccoleri, D.D.Caviglia and M.Valle, Analysis
of the Behaviour of a Dynamic Latch Comparator, IEEE
Trans. on Circuits and Systems-I, vol.45, no.3, pp.294-298,
Mar. 1998.
SNDR = 39.8dB
SNR = 40dB
SFDR = 50dB Note: results referred to FS
Output spectrum [dB]
Frequency [Hz]
Filter
BDL channel
Offset
control
system
Calibration
system
ADC
I - 744
Authorized licensed use limited to: TEXAS INSTRUMENTS VIRTUAL LIBRARY. Downloaded on March 8, 2009 at 16:22 from IEEE Xplore. Restrictions apply.