library IEEE;

use IEEE.std_logic_arith.all;
use IEEE.std_logic_1164.ALL;
ENTITY a7s IS
PORT (
p
: IN bit_vector(0 to 6) ;
s1,s2,s3,s4,s5,s6,s7 : OUT bit
);
END a7s;

ARCHITECTURE archi OF a7s IS

signal seg :bit_vector(6 DOWNTO 0);
BEGIN

PROCESS(p)
BEGIN
CASE p IS
WHEN "0000000" =>seg <= "1111110"
WHEN "0000001" =>seg <= "0110000"
WHEN "0000010" =>seg <= "1101101"
WHEN "0000011" =>seg <= "1111001"
WHEN "0000100" =>seg <= "0110011"
WHEN "0000101" =>seg <= "1011011"
WHEN "0000110" =>seg <= "1011111"
WHEN "0000111" =>seg <= "1110000"
WHEN "0001000" =>seg <= "1111111"
WHEN "0001001" =>seg <= "1111011"
WHEN "0001010" =>seg <= "1110111"
WHEN "0001011" =>seg <= "0011111"
WHEN "0001100" =>seg <= "1001110"
WHEN "0001101" =>seg <= "0111101"
WHEN "0001110" =>seg <= "1001111"
WHEN "0001111" =>seg <= "1000111"
WHEN OTHERS =>seg <= "0110111";
END CASE;
END PROCESS;
PROCESS (s7,s6,s5,s4,s3,s2,s1)
BEGIN
s7 <= not seg(6);
s6 <= not seg(5);
s5 <= not seg(4);
s4 <= not seg(3);
s3 <= not seg(2);
s2 <= not seg(1);
s1 <= not seg(0);
END PROCESS;

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END archi;